// Copyright (c) 1994-2006 Sun Microsystems Inc. // All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // // - Redistribution in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // - Neither the name of Sun Microsystems or the names of contributors may // be used to endorse or promote products derived from this software without // specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED // OF THE POSSIBILITY OF SUCH DAMAGE. // The original source code covered by the above license above has been modified // significantly by Google Inc. // Copyright 2012 the V8 project authors. All rights reserved. // // Copyright IBM Corp. 2012, 2013. All rights reserved. // #ifndef V8_PPC_ASSEMBLER_PPC_INL_H_ #define V8_PPC_ASSEMBLER_PPC_INL_H_ #include "ppc/assembler-ppc.h" #include "cpu.h" #include "debug.h" namespace v8 { namespace internal { int DwVfpRegister::ToAllocationIndex(DwVfpRegister reg) { int index = reg.code() - 1; // d0 is skipped ASSERT(index < kNumAllocatableRegisters); ASSERT(!reg.is(kDoubleRegZero)); ASSERT(!reg.is(kScratchDoubleReg)); return index; } void RelocInfo::apply(intptr_t delta) { if (RelocInfo::IsInternalReference(rmode_)) { // absolute code pointer inside code object moves with the code object. intptr_t* p = reinterpret_cast(pc_); *p += delta; // relocate entry CPU::FlushICache(p, sizeof(uintptr_t)); } // We do not use pc relative addressing on PPC, so there is // nothing else to do. } Address RelocInfo::target_address() { ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY); return Assembler::target_address_at(pc_); } Address RelocInfo::target_address_address() { ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY || rmode_ == EMBEDDED_OBJECT || rmode_ == EXTERNAL_REFERENCE); // Read the address of the word containing the target_address in an // instruction stream. // The only architecture-independent user of this function is the serializer. // The serializer uses it to find out how many raw bytes of instruction to // output before the next target. // For an instruction like LIS/ADDIC where the target bits are mixed into the // instruction bits, the size of the target will be zero, indicating that the // serializer should not step forward in memory after a target is resolved // and written. In this case the target_address_address function should // return the end of the instructions to be patched, allowing the // deserializer to deserialize the instructions as raw bytes and put them in // place, ready to be patched with the target. return reinterpret_cast
( pc_ + (Assembler::kInstructionsForPtrConstant * Assembler::kInstrSize)); } int RelocInfo::target_address_size() { return Assembler::kSpecialTargetSize; } void RelocInfo::set_target_address(Address target, WriteBarrierMode mode) { ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY); Assembler::set_target_address_at(pc_, target); if (mode == UPDATE_WRITE_BARRIER && host() != NULL && IsCodeTarget(rmode_)) { Object* target_code = Code::GetCodeFromTargetAddress(target); host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( host(), this, HeapObject::cast(target_code)); } } Address Assembler::target_address_from_return_address(Address pc) { return pc - kCallTargetAddressOffset; } Object* RelocInfo::target_object() { ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); return reinterpret_cast(Assembler::target_address_at(pc_)); } Handle RelocInfo::target_object_handle(Assembler* origin) { ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); return Handle(reinterpret_cast( Assembler::target_address_at(pc_))); } Object** RelocInfo::target_object_address() { ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); reconstructed_obj_ptr_ = reinterpret_cast(Assembler::target_address_at(pc_)); return &reconstructed_obj_ptr_; } void RelocInfo::set_target_object(Object* target, WriteBarrierMode mode) { ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); Assembler::set_target_address_at(pc_, reinterpret_cast
(target)); if (mode == UPDATE_WRITE_BARRIER && host() != NULL && target->IsHeapObject()) { host()->GetHeap()->incremental_marking()->RecordWrite( host(), &Memory::Object_at(pc_), HeapObject::cast(target)); } } Address* RelocInfo::target_reference_address() { ASSERT(rmode_ == EXTERNAL_REFERENCE); reconstructed_adr_ptr_ = Assembler::target_address_at(pc_); return &reconstructed_adr_ptr_; } Handle RelocInfo::target_cell_handle() { ASSERT(rmode_ == RelocInfo::GLOBAL_PROPERTY_CELL); Address address = Memory::Address_at(pc_); return Handle( reinterpret_cast(address)); } JSGlobalPropertyCell* RelocInfo::target_cell() { ASSERT(rmode_ == RelocInfo::GLOBAL_PROPERTY_CELL); return JSGlobalPropertyCell::FromValueAddress(Memory::Address_at(pc_)); } void RelocInfo::set_target_cell(JSGlobalPropertyCell* cell, WriteBarrierMode mode) { ASSERT(rmode_ == RelocInfo::GLOBAL_PROPERTY_CELL); Address address = cell->address() + JSGlobalPropertyCell::kValueOffset; Memory::Address_at(pc_) = address; if (mode == UPDATE_WRITE_BARRIER && host() != NULL) { // TODO(1550) We are passing NULL as a slot because cell can never be on // evacuation candidate. host()->GetHeap()->incremental_marking()->RecordWrite( host(), NULL, cell); } } Address RelocInfo::call_address() { ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); // The pc_ offset of 0 assumes patched return sequence per // BreakLocationIterator::SetDebugBreakAtReturn(), or debug break // slot per BreakLocationIterator::SetDebugBreakAtSlot(). return Assembler::target_address_at(pc_); } void RelocInfo::set_call_address(Address target) { ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); Assembler::set_target_address_at(pc_, target); if (host() != NULL) { Object* target_code = Code::GetCodeFromTargetAddress(target); host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( host(), this, HeapObject::cast(target_code)); } } Object* RelocInfo::call_object() { return *call_object_address(); } void RelocInfo::set_call_object(Object* target) { *call_object_address() = target; } Object** RelocInfo::call_object_address() { ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); return reinterpret_cast(pc_ + 2 * Assembler::kInstrSize); } bool RelocInfo::IsPatchedReturnSequence() { // // The patched return sequence is defined by // BreakLocationIterator::SetDebugBreakAtReturn() // FIXED_SEQUENCE Instr instr0 = Assembler::instr_at(pc_); Instr instr1 = Assembler::instr_at(pc_ + 1 * Assembler::kInstrSize); #if V8_TARGET_ARCH_PPC64 Instr instr3 = Assembler::instr_at(pc_ + (3 * Assembler::kInstrSize)); Instr instr4 = Assembler::instr_at(pc_ + (4 * Assembler::kInstrSize)); Instr binstr = Assembler::instr_at(pc_ + (7 * Assembler::kInstrSize)); #else Instr binstr = Assembler::instr_at(pc_ + 4 * Assembler::kInstrSize); #endif bool patched_return = ((instr0 & kOpcodeMask) == ADDIS && (instr1 & kOpcodeMask) == ORI && #if V8_TARGET_ARCH_PPC64 (instr3 & kOpcodeMask) == ORIS && (instr4 & kOpcodeMask) == ORI && #endif (binstr == 0x7d821008)); // twge r2, r2 // printf("IsPatchedReturnSequence: %d\n", patched_return); return patched_return; } bool RelocInfo::IsPatchedDebugBreakSlotSequence() { Instr current_instr = Assembler::instr_at(pc_); return !Assembler::IsNop(current_instr, Assembler::DEBUG_BREAK_NOP); } void RelocInfo::Visit(ObjectVisitor* visitor) { RelocInfo::Mode mode = rmode(); if (mode == RelocInfo::EMBEDDED_OBJECT) { visitor->VisitEmbeddedPointer(this); } else if (RelocInfo::IsCodeTarget(mode)) { visitor->VisitCodeTarget(this); } else if (mode == RelocInfo::GLOBAL_PROPERTY_CELL) { visitor->VisitGlobalPropertyCell(this); } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { visitor->VisitExternalReference(this); #ifdef ENABLE_DEBUGGER_SUPPORT // TODO(isolates): Get a cached isolate below. } else if (((RelocInfo::IsJSReturn(mode) && IsPatchedReturnSequence()) || (RelocInfo::IsDebugBreakSlot(mode) && IsPatchedDebugBreakSlotSequence())) && Isolate::Current()->debug()->has_break_points()) { visitor->VisitDebugTarget(this); #endif } else if (mode == RelocInfo::RUNTIME_ENTRY) { visitor->VisitRuntimeEntry(this); } } template void RelocInfo::Visit(Heap* heap) { RelocInfo::Mode mode = rmode(); if (mode == RelocInfo::EMBEDDED_OBJECT) { StaticVisitor::VisitEmbeddedPointer(heap, this); } else if (RelocInfo::IsCodeTarget(mode)) { StaticVisitor::VisitCodeTarget(heap, this); } else if (mode == RelocInfo::GLOBAL_PROPERTY_CELL) { StaticVisitor::VisitGlobalPropertyCell(heap, this); } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { StaticVisitor::VisitExternalReference(this); #ifdef ENABLE_DEBUGGER_SUPPORT } else if (heap->isolate()->debug()->has_break_points() && ((RelocInfo::IsJSReturn(mode) && IsPatchedReturnSequence()) || (RelocInfo::IsDebugBreakSlot(mode) && IsPatchedDebugBreakSlotSequence()))) { StaticVisitor::VisitDebugTarget(heap, this); #endif } else if (mode == RelocInfo::RUNTIME_ENTRY) { StaticVisitor::VisitRuntimeEntry(this); } } Operand::Operand(intptr_t immediate, RelocInfo::Mode rmode) { rm_ = no_reg; imm_ = immediate; rmode_ = rmode; } Operand::Operand(const ExternalReference& f) { rm_ = no_reg; imm_ = reinterpret_cast(f.address()); rmode_ = RelocInfo::EXTERNAL_REFERENCE; } Operand::Operand(Smi* value) { rm_ = no_reg; imm_ = reinterpret_cast(value); rmode_ = RelocInfo::NONE; } Operand::Operand(Register rm) { rm_ = rm; rmode_ = RelocInfo::NONE; // PPC -why doesn't ARM do this? } void Assembler::CheckBuffer() { if (buffer_space() <= kGap) { GrowBuffer(); } } void Assembler::CheckTrampolinePoolQuick() { if (pc_offset() >= next_buffer_check_) { CheckTrampolinePool(); } } void Assembler::emit(Instr x) { CheckBuffer(); *reinterpret_cast(pc_) = x; pc_ += kInstrSize; CheckTrampolinePoolQuick(); } bool Operand::is_reg() const { return rm_.is_valid(); } // Fetch the 32bit value from the FIXED_SEQUENCE lis/ori Address Assembler::target_address_at(Address pc) { Instr instr1 = instr_at(pc); Instr instr2 = instr_at(pc + kInstrSize); #if V8_TARGET_ARCH_PPC64 Instr instr4 = instr_at(pc + (3*kInstrSize)); Instr instr5 = instr_at(pc + (4*kInstrSize)); #endif // Interpret 2 instructions generated by lis/ori if (IsLis(instr1) && IsOri(instr2)) { #if V8_TARGET_ARCH_PPC64 // Assemble the 64 bit value. uint64_t hi = (static_cast((instr1 & kImm16Mask) << 16) | static_cast(instr2 & kImm16Mask)); uint64_t lo = (static_cast((instr4 & kImm16Mask) << 16) | static_cast(instr5 & kImm16Mask)); return reinterpret_cast
((hi << 32) | lo); #else // Assemble the 32 bit value. return reinterpret_cast
( ((instr1 & kImm16Mask) << 16) | (instr2 & kImm16Mask)); #endif } PPCPORT_UNIMPLEMENTED(); return (Address)0; } // This sets the branch destination (which gets loaded at the call address). // This is for calls and branches within generated code. The serializer // has already deserialized the lis/ori instructions etc. // There is a FIXED_SEQUENCE assumption here void Assembler::deserialization_set_special_target_at( Address instruction_payload, Address target) { set_target_address_at( instruction_payload - kInstructionsForPtrConstant * kInstrSize, target); } // This code assumes the FIXED_SEQUENCE of lis/ori void Assembler::set_target_address_at(Address pc, Address target) { Instr instr1 = instr_at(pc); Instr instr2 = instr_at(pc + kInstrSize); // Interpret 2 instructions generated by lis/ori if (IsLis(instr1) && IsOri(instr2)) { #if V8_TARGET_ARCH_PPC64 Instr instr4 = instr_at(pc + (3*kInstrSize)); Instr instr5 = instr_at(pc + (4*kInstrSize)); // Needs to be fixed up when mov changes to handle 64-bit values. uint32_t* p = reinterpret_cast(pc); uintptr_t itarget = reinterpret_cast(target); instr5 &= ~kImm16Mask; instr5 |= itarget & kImm16Mask; itarget = itarget >> 16; instr4 &= ~kImm16Mask; instr4 |= itarget & kImm16Mask; itarget = itarget >> 16; instr2 &= ~kImm16Mask; instr2 |= itarget & kImm16Mask; itarget = itarget >> 16; instr1 &= ~kImm16Mask; instr1 |= itarget & kImm16Mask; itarget = itarget >> 16; *p = instr1; *(p+1) = instr2; *(p+3) = instr4; *(p+4) = instr5; CPU::FlushICache(p, 20); #else uint32_t* p = reinterpret_cast(pc); uint32_t itarget = reinterpret_cast(target); int lo_word = itarget & kImm16Mask; int hi_word = itarget >> 16; instr1 &= ~kImm16Mask; instr1 |= hi_word; instr2 &= ~kImm16Mask; instr2 |= lo_word; *p = instr1; *(p+1) = instr2; CPU::FlushICache(p, 8); #endif } else { UNREACHABLE(); } } } } // namespace v8::internal #endif // V8_PPC_ASSEMBLER_PPC_INL_H_