/* * forcedeth.h -- Driver for NVIDIA nForce media access controllers for iPXE * Copyright (c) 2010 Andrei Faur * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA * 02110-1301, USA. * * Portions of this code are taken from the Linux forcedeth driver that was * based on a cleanroom reimplementation which was based on reverse engineered * documentation written by Carl-Daniel Hailfinger and Andrew de Quincey: * Copyright (C) 2003,4,5 Manfred Spraul * Copyright (C) 2004 Andrew de Quincey (wol support) * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane * IRQ rate fixes, bigendian fixes, cleanups, verification) * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation * * This header is a direct copy of #define lines and structs found in the * above mentioned driver, modified where necessary to make them work for iPXE. * */ FILE_LICENCE ( GPL2_OR_LATER ); #ifndef _FORCEDETH_H_ #define _FORCEDETH_H_ struct ring_desc { u32 buf; u32 flaglen; }; struct ring_desc_ex { u32 bufhigh; u32 buflow; u32 txvlan; u32 flaglen; }; #define DESC_VER_1 1 #define DESC_VER_2 2 #define DESC_VER_3 3 #define RX_RING_SIZE 16 #define TX_RING_SIZE 32 #define RXTX_RING_SIZE ( ( RX_RING_SIZE ) + ( TX_RING_SIZE ) ) #define RX_RING_MIN 128 #define TX_RING_MIN 64 #define RING_MAX_DESC_VER_1 1024 #define RING_MAX_DESC_VER_2_3 16384 #define NV_RX_ALLOC_PAD (64) #define NV_RX_HEADERS (64) #define RX_BUF_SZ ( ( ETH_FRAME_LEN ) + ( NV_RX_HEADERS ) ) #define NV_PKTLIMIT_1 1500 #define NV_PKTLIMIT_2 9100 #define NV_LINK_POLL_FREQUENCY 128 /* PHY defines */ #define PHY_OUI_MARVELL 0x5043 #define PHY_OUI_CICADA 0x03f1 #define PHY_OUI_VITESSE 0x01c1 #define PHY_OUI_REALTEK 0x0732 #define PHY_OUI_REALTEK2 0x0020 #define PHYID1_OUI_MASK 0x03ff #define PHYID1_OUI_SHFT 6 #define PHYID2_OUI_MASK 0xfc00 #define PHYID2_OUI_SHFT 10 #define PHYID2_MODEL_MASK 0x03f0 #define PHY_MODEL_REALTEK_8211 0x0110 #define PHY_REV_MASK 0x0001 #define PHY_REV_REALTEK_8211B 0x0000 #define PHY_REV_REALTEK_8211C 0x0001 #define PHY_MODEL_REALTEK_8201 0x0200 #define PHY_MODEL_MARVELL_E3016 0x0220 #define PHY_MARVELL_E3016_INITMASK 0x0300 #define PHY_CICADA_INIT1 0x0f000 #define PHY_CICADA_INIT2 0x0e00 #define PHY_CICADA_INIT3 0x01000 #define PHY_CICADA_INIT4 0x0200 #define PHY_CICADA_INIT5 0x0004 #define PHY_CICADA_INIT6 0x02000 #define PHY_VITESSE_INIT_REG1 0x1f #define PHY_VITESSE_INIT_REG2 0x10 #define PHY_VITESSE_INIT_REG3 0x11 #define PHY_VITESSE_INIT_REG4 0x12 #define PHY_VITESSE_INIT_MSK1 0xc #define PHY_VITESSE_INIT_MSK2 0x0180 #define PHY_VITESSE_INIT1 0x52b5 #define PHY_VITESSE_INIT2 0xaf8a #define PHY_VITESSE_INIT3 0x8 #define PHY_VITESSE_INIT4 0x8f8a #define PHY_VITESSE_INIT5 0xaf86 #define PHY_VITESSE_INIT6 0x8f86 #define PHY_VITESSE_INIT7 0xaf82 #define PHY_VITESSE_INIT8 0x0100 #define PHY_VITESSE_INIT9 0x8f82 #define PHY_VITESSE_INIT10 0x0 #define PHY_REALTEK_INIT_REG1 0x1f #define PHY_REALTEK_INIT_REG2 0x19 #define PHY_REALTEK_INIT_REG3 0x13 #define PHY_REALTEK_INIT_REG4 0x14 #define PHY_REALTEK_INIT_REG5 0x18 #define PHY_REALTEK_INIT_REG6 0x11 #define PHY_REALTEK_INIT_REG7 0x01 #define PHY_REALTEK_INIT1 0x0000 #define PHY_REALTEK_INIT2 0x8e00 #define PHY_REALTEK_INIT3 0x0001 #define PHY_REALTEK_INIT4 0xad17 #define PHY_REALTEK_INIT5 0xfb54 #define PHY_REALTEK_INIT6 0xf5c7 #define PHY_REALTEK_INIT7 0x1000 #define PHY_REALTEK_INIT8 0x0003 #define PHY_REALTEK_INIT9 0x0008 #define PHY_REALTEK_INIT10 0x0005 #define PHY_REALTEK_INIT11 0x0200 #define PHY_REALTEK_INIT_MSK1 0x0003 #define PHY_GIGABIT 0x0100 #define PHY_TIMEOUT 0x1 #define PHY_ERROR 0x2 #define PHY_100 0x1 #define PHY_1000 0x2 #define PHY_HALF 0x100 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 #define NV_PAUSEFRAME_RX_ENABLE 0x0004 #define NV_PAUSEFRAME_TX_ENABLE 0x0008 #define NV_PAUSEFRAME_RX_REQ 0x0010 #define NV_PAUSEFRAME_TX_REQ 0x0020 #define NV_PAUSEFRAME_AUTONEG 0x0040 /* MSI/MSI-X defines */ #define NV_MSI_X_MAX_VECTORS 8 #define NV_MSI_X_VECTORS_MASK 0x000f #define NV_MSI_CAPABLE 0x0010 #define NV_MSI_X_CAPABLE 0x0020 #define NV_MSI_ENABLED 0x0040 #define NV_MSI_X_ENABLED 0x0080 #define NV_MSI_X_VECTOR_ALL 0x0 #define NV_MSI_X_VECTOR_RX 0x0 #define NV_MSI_X_VECTOR_TX 0x1 #define NV_MSI_X_VECTOR_OTHER 0x2 #define NV_MSI_PRIV_OFFSET 0x68 #define NV_MSI_PRIV_VALUE 0xffffffff #define NV_MIIBUSY_DELAY 50 #define NV_MIIPHY_DELAY 10 #define NV_MIIPHY_DELAYMAX 10000 /* Hardware access */ #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */ #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */ #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */ #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */ #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */ #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */ #define DEV_HAS_MSI 0x0000040 /* device supports MSI */ #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */ #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */ #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */ #define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */ #define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */ #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */ #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */ #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */ #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */ #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */ #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */ #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */ #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */ #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */ #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */ #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */ #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */ #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */ #define FLAG_MASK_V1 0xffff0000 #define FLAG_MASK_V2 0xffffc000 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) #define NV_TX_LASTPACKET (1<<16) #define NV_TX_RETRYERROR (1<<19) #define NV_TX_RETRYCOUNT_MASK (0xF<<20) #define NV_TX_FORCED_INTERRUPT (1<<24) #define NV_TX_DEFERRED (1<<26) #define NV_TX_CARRIERLOST (1<<27) #define NV_TX_LATECOLLISION (1<<28) #define NV_TX_UNDERFLOW (1<<29) #define NV_TX_ERROR (1<<30) #define NV_TX_VALID (1<<31) #define NV_TX2_LASTPACKET (1<<29) #define NV_TX2_RETRYERROR (1<<18) #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) #define NV_TX2_FORCED_INTERRUPT (1<<30) #define NV_TX2_DEFERRED (1<<25) #define NV_TX2_CARRIERLOST (1<<26) #define NV_TX2_LATECOLLISION (1<<27) #define NV_TX2_UNDERFLOW (1<<28) /* error and valid are the same for both */ #define NV_TX2_ERROR (1<<30) #define NV_TX2_VALID (1<<31) #define NV_TX2_TSO (1<<28) #define NV_TX2_TSO_SHIFT 14 #define NV_TX2_TSO_MAX_SHIFT 14 #define NV_TX2_TSO_MAX_SIZE (1<