/* * This file is part of the coreboot project. * * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* * List of suported C-states in this processor. */ enum { C_STATE_C0, /* 0 */ C_STATE_C1, /* 1 */ C_STATE_C1E, /* 2 */ C_STATE_C3, /* 3 */ C_STATE_C6_SHORT_LAT, /* 4 */ C_STATE_C6_LONG_LAT, /* 5 */ C_STATE_C7_SHORT_LAT, /* 6 */ C_STATE_C7_LONG_LAT, /* 7 */ C_STATE_C7S_SHORT_LAT, /* 8 */ C_STATE_C7S_LONG_LAT, /* 9 */ C_STATE_C8, /* 10 */ C_STATE_C9, /* 11 */ C_STATE_C10, /* 12 */ NUM_C_STATES }; #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ .space_id = ACPI_ADDRESS_SPACE_FIXED, \ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ } static acpi_cstate_t cstate_map[NUM_C_STATES] = { [C_STATE_C0] = { }, [C_STATE_C1] = { .latency = 0, .power = C1_POWER, .resource = MWAIT_RES(0, 0), }, [C_STATE_C1E] = { .latency = 0, .power = C1_POWER, .resource = MWAIT_RES(0, 1), }, [C_STATE_C3] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(0), .power = C3_POWER, .resource = MWAIT_RES(1, 0), }, [C_STATE_C6_SHORT_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(1), .power = C6_POWER, .resource = MWAIT_RES(2, 0), }, [C_STATE_C6_LONG_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(2), .power = C6_POWER, .resource = MWAIT_RES(2, 1), }, [C_STATE_C7_SHORT_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(1), .power = C7_POWER, .resource = MWAIT_RES(3, 0), }, [C_STATE_C7_LONG_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(2), .power = C7_POWER, .resource = MWAIT_RES(3, 1), }, [C_STATE_C7S_SHORT_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(1), .power = C7_POWER, .resource = MWAIT_RES(3, 2), }, [C_STATE_C7S_LONG_LAT] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(2), .power = C7_POWER, .resource = MWAIT_RES(3, 3), }, [C_STATE_C8] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(3), .power = C8_POWER, .resource = MWAIT_RES(4, 0), }, [C_STATE_C9] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(4), .power = C9_POWER, .resource = MWAIT_RES(5, 0), }, [C_STATE_C10] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(5), .power = C10_POWER, .resource = MWAIT_RES(6, 0), }, }; static int cstate_set_s0ix[] = { C_STATE_C1E, C_STATE_C7S_LONG_LAT, C_STATE_C10 }; static int cstate_set_non_s0ix[] = { C_STATE_C1E, C_STATE_C3, C_STATE_C7S_LONG_LAT, }; static int get_cores_per_package(void) { struct cpuinfo_x86 c; struct cpuid_result result; int cores = 1; get_fms(&c, cpuid_eax(1)); if (c.x86 != 6) return 1; result = cpuid_ext(0xb, 1); cores = result.ebx & 0xff; return cores; } static void acpi_create_gnvs(global_nvs_t *gnvs) { const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; /* Set unknown wake source */ gnvs->pm1i = -1; /* CPU core count */ gnvs->pcnt = dev_count_cpu(); #if IS_ENABLED(CONFIG_CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif #if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; /* Fill in the Wifi Region id */ gnvs->cid1 = wifi_regulatory_domain(); /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); } unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, CONFIG_MMCONF_BASE_ADDRESS, 0, 0, (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); return current; } unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ current = acpi_create_madt_lapics(current); /* IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); return acpi_madt_irq_overrides(current); } void acpi_fill_fadt(acpi_fadt_t *fadt) { const struct device *dev = SA_DEV_ROOT; const config_t *config = dev ? dev->chip_info : NULL; const uint16_t pmbase = ACPI_BASE_ADDRESS; /* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; fadt->flush_stride = 16; fadt->duty_offset = 1; fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; fadt->iapc_boot_arch = 0; if (!IS_ENABLED(CONFIG_NO_FADT_8042)) fadt->iapc_boot_arch |= ACPI_FADT_8042; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; if (config && config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.resv = 0; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; fadt->reset_value = 6; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.resv = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.resv = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 0; fadt->x_gpe0_blk.bit_width = 0; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; fadt->x_gpe0_blk.addrl = 0; fadt->x_gpe0_blk.addrh = 0; fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; } static void generate_c_state_entries(int s0ix_enable, int max_cstate) { acpi_cstate_t map[max_cstate]; int *set; int i; if (s0ix_enable) set = cstate_set_s0ix; else set = cstate_set_non_s0ix; for (i = 0; i < max_cstate; i++) { memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); map[i].ctype = i + 1; } /* Generate C-state tables */ acpigen_write_CST_package(map, ARRAY_SIZE(map)); } static int calculate_power(int tdp, int p1_ratio, int ratio) { u32 m; u32 power; /* * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 * * Power = (ratio / p1_ratio) * m * tdp */ m = (110000 - ((p1_ratio - ratio) * 625)) / 11; m = (m * m) / 1000; power = ((ratio * 100000 / p1_ratio) / 100); power *= (m / 100) * (tdp / 1000); power /= 1000; return (int)power; } static void generate_p_state_entries(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; msr_t msr; /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ msr = rdmsr(MSR_MISC_PWR_MGMT); if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) coord_type = SW_ANY; else coord_type = HW_ALL; /* Get bus ratio limits and calculate clock speeds */ msr = rdmsr(MSR_PLATFORM_INFO); ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ /* Determine if this CPU has configurable TDP */ if (cpu_config_tdp_levels()) { /* Set max ratio to nominal TDP ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); ratio_max = msr.lo & 0xff; } else { /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); power_unit = 2 << ((msr.lo & 0xf) - 1); msr = rdmsr(MSR_PKG_POWER_SKU); power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ acpigen_write_empty_PCT(); /* Write _PPC with no limit on supported P-state */ acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ acpigen_write_PSD_package(core, 1, coord_type); /* Add P-state entries in _PSS table */ acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = PSS_RATIO_STEP; num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; if (num_entries > PSS_MAX_ENTRIES) { ratio_step += 1; num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; } /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ acpigen_write_package(num_entries + 2); msr = rdmsr(MSR_TURBO_RATIO_LIMIT); ratio_turbo = msr.lo & 0xff; /* Add entry for Turbo ratio */ acpigen_write_PSS_package( clock_max + 1, /* MHz */ power_max, /* mW */ PSS_LATENCY_TRANSITION, /* lat1 */ PSS_LATENCY_BUSMASTER, /* lat2 */ ratio_turbo << 8, /* control */ ratio_turbo << 8); /* status */ } else { /* _PSS package count without Turbo */ acpigen_write_package(num_entries + 1); } /* First regular entry is max non-turbo ratio */ acpigen_write_PSS_package( clock_max, /* MHz */ power_max, /* mW */ PSS_LATENCY_TRANSITION, /* lat1 */ PSS_LATENCY_BUSMASTER, /* lat2 */ ratio_max << 8, /* control */ ratio_max << 8); /* status */ /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min; ratio -= ratio_step) { /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); clock = ratio * CONFIG_CPU_BCLK_MHZ; acpigen_write_PSS_package( clock, /* MHz */ power, /* mW */ PSS_LATENCY_TRANSITION, /* lat1 */ PSS_LATENCY_BUSMASTER, /* lat2 */ ratio << 8, /* control */ ratio << 8); /* status */ } /* Fix package length */ acpigen_pop_len(); } void generate_cpu_entries(struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; int is_s0ix_enable = config->s0ix_enable; int max_c_state; if (is_s0ix_enable) max_c_state = ARRAY_SIZE(cstate_set_s0ix); else max_c_state = ARRAY_SIZE(cstate_set_non_s0ix); printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); if (config->eist_enable && config->speed_shift_enable) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); } for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < cores_per_package; core_id++) { if (core_id > 0) { pcontrol_blk = 0; plen = 0; } /* Generate processor \_PR.CPUx */ acpigen_write_processor( cpu_id*cores_per_package+core_id, pcontrol_blk, plen); /* Generate C-state tables */ generate_c_state_entries(is_s0ix_enable, max_c_state); if (config->eist_enable) { /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); if (config->speed_shift_enable) acpigen_write_CPPC_method(); } acpigen_pop_len(); } } } static unsigned long acpi_fill_dmar(unsigned long current) { struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ if (igfx_dev && igfx_dev->enabled && gfxvten && gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); /* Add RMRR entry */ tmp = current; current += acpi_create_dmar_rmrr(current, 0, sa_get_gsm_base(), sa_get_tolud_base() - 1); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_rmrr_fixup(tmp, current); } struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; /* General VTBAR has to be set and in 32-bit space. */ if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { const unsigned long tmp = current; /* P2SB may already be hidden. There's no clear rule, when. */ const u8 p2sb_hidden = pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic(current, 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); current += acpi_create_dmar_ds_msi_hpet(current, 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); acpi_dmar_drhd_fixup(tmp, current); } return current; } unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { const struct soc_intel_skylake_config *const config = dev->chip_info; acpi_dmar_t *const dmar = (acpi_dmar_t *)current; /* Create DMAR table only if we have VT-d capability. */ if ((config && config->ignore_vtd) || !soc_is_vtd_capable()) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); return current; } unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; uint16_t flags = MP_IRQ_TRIGGER_LEVEL; /* INT_SRC_OVR */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); if (sci >= 20) flags |= MP_IRQ_POLARITY_LOW; else flags |= MP_IRQ_POLARITY_HIGH; /* SCI */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); return current; } unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { current = acpi_write_dbg2_pci_uart(rsdp, current, uart_get_device(), ACPI_ACCESS_SIZE_DWORD_ACCESS); current = acpi_write_hpet(device, current, rsdp); return acpi_align_current(current); } void southbridge_inject_dsdt(struct device *device) { global_nvs_t *gnvs; gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) memset(gnvs, 0, sizeof(*gnvs)); } if (gnvs) { acpi_create_gnvs(gnvs); acpi_mainboard_gnvs(gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); /* Add it to DSDT. */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_pop_len(); } } /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; uint32_t gpe0_std; int i; const int last_index = GPE0_REG_MAX - 1; ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps == NULL) return -1; pm1_en = ps->pm1_en; gpe0_std = ps->gpe0_en[3]; /* * Chipset state in the suspend well (but not RTC) is lost in Deep S3 * so enable Deep S3 wake events that are configured by the mainboard */ if (ps->prev_sleep_state == ACPI_S3 && (config->deep_s3_enable_ac || config->deep_s3_enable_dc)) { pm1_en |= PWRBTN_STS; /* Always enabled as wake source */ if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN) gpe0_std |= LAN_WAK_EN; if (config->deep_sx_config & DSX_EN_WAKE_PIN) pm1_en |= PCIEXPWAK_STS; } *pm1 = ps->pm1_sts & pm1_en; /* Mask off GPE0 status bits that are not enabled */ *gpe0 = &gpe0_sts[0]; for (i = 0; i < last_index; i++) gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std; return GPE0_REG_MAX; } __weak void acpi_mainboard_gnvs(global_nvs_t *gnvs) { } const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0"; if (dev->path.type == DEVICE_PATH_USB) { switch (dev->path.usb.port_type) { case 0: /* Root Hub */ return "RHUB"; case 2: /* USB2 ports */ switch (dev->path.usb.port_id) { case 0: return "HS01"; case 1: return "HS02"; case 2: return "HS03"; case 3: return "HS04"; case 4: return "HS05"; case 5: return "HS06"; case 6: return "HS07"; case 7: return "HS08"; case 8: return "HS09"; case 9: return "HS10"; } break; case 3: /* USB3 ports */ switch (dev->path.usb.port_id) { case 0: return "SS01"; case 1: return "SS02"; case 2: return "SS03"; case 3: return "SS04"; case 4: return "SS05"; case 5: return "SS06"; } break; } return NULL; } if (dev->path.type != DEVICE_PATH_PCI) return NULL; switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_IGD: return "GFX0"; case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_USBOTG: return "XDCI"; case PCH_DEVFN_THERMAL: return "THRM"; case PCH_DEVFN_CIO: return "ICIO"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; case PCH_DEVFN_CSE: return "CSE1"; case PCH_DEVFN_CSE_2: return "CSE2"; case PCH_DEVFN_CSE_IDER: return "CSED"; case PCH_DEVFN_CSE_KT: return "CSKT"; case PCH_DEVFN_CSE_3: return "CSE3"; case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; case PCH_DEVFN_I2C5: return "I2C5"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; case PCH_DEVFN_PCIE4: return "RP04"; case PCH_DEVFN_PCIE5: return "RP05"; case PCH_DEVFN_PCIE6: return "RP06"; case PCH_DEVFN_PCIE7: return "RP07"; case PCH_DEVFN_PCIE8: return "RP08"; case PCH_DEVFN_PCIE9: return "RP09"; case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDIO: return "SDIO"; case PCH_DEVFN_SDCARD: return "SDXC"; case PCH_DEVFN_LPC: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; case PCH_DEVFN_SPI: return "FSPI"; case PCH_DEVFN_GBE: return "IGBE"; case PCH_DEVFN_TRACEHUB:return "THUB"; } return NULL; } static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) { /* op (gpio_num) */ acpigen_emit_namestring(op); acpigen_write_integer(gpio_num); return 0; } static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) { /* Store (op (gpio_num), Local0) */ acpigen_write_store(); acpigen_soc_gpio_op(op, gpio_num); acpigen_emit_byte(LOCAL0_OP); return 0; } int acpigen_soc_read_rx_gpio(unsigned int gpio_num) { return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); } int acpigen_soc_get_tx_gpio(unsigned int gpio_num) { return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); } int acpigen_soc_set_tx_gpio(unsigned int gpio_num) { return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); } int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) { return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); }