Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: INTRODUCTION

Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide
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INTRODUCTION

1 Introduction

1.1 Purpose

The purpose of this document is to describe the steps required to integrate the Intel® Firmware Support Package (FSP) into a boot loader solution. It supports Kabylake platforms with Kabylake/Skylake processor and Sunrise point Platform Controller Hub (PCH).

1.2 Intended Audience

This document is targeted at all platform and system developers who need to consume FSP binaries in their boot loader solutions. This includes, but is not limited to: system BIOS developers, boot loader developers, system integrators, as well as end users.

1.3 Related Documents

  • Platform Initialization (PI) Specification v1.4 located at http://www.uefi.org/specifications
  • UEFI Specification v2.5 located at http://www.uefi.org/specifications
  • Intel® Firmware Support Package: External Architecture Specification (EAS) v2.0 located at http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf
  • Boot Setting File Specification (BSF) v1.0 https://firmware.intel.com/sites/default/files/BSF_1_0.pdf
  • Binary Configuration Tool for Intel® Firmware Support Package available at http://www.intel.com/fsp

1.4 Acronyms and Terminology

Acronym | Definition
BCT | Binary Configuration Tool
BSF | Boot Setting File
BSP | Boot Strap Processor
BWG | BIOS Writer's Guide
CAR | Cache As Ram
CRB | Customer Reference Board
FIT | Firmware Interface Table
FSP | Firmware Support Package
FSP API | Firmware Support Package Interface
FW | Firmware
PCH | Platform Controller Hub
PMC | Power Management Controller
SBSP | System BSP
SMI | System Management Interrupt
SMM | System Management Mode
SPI | Serial Peripheral Interface
TSEG | Memory Reserved at the Top of Memory to be used as SMRAM
UPD | Updatable Product Data
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP OVERVIEW

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FSP OVERVIEW

FSP Overview

2.1 Technical Overview

The Intel® Firmware Support Package (FSP) provides chipset and processor initialization in a format that can easily be incorporated into many existing boot loaders.

The FSP will perform the necessary initialization steps as documented in the BWG including initialization of the CPU, memory controller, chipset and certain bus interfaces, if necessary.

FSP is not a stand-alone boot loader; therefore it needs to be integrated into a host boot loader to carry out other boot loader functions, such as: initializing non-Intel components, conducting bus enumeration, and discovering devices in the system and all industry standard initialization.

The FSP binary can be integrated easily into many different boot loaders, such as Coreboot, EDKII etc. and also into the embedded OS directly.

Below are some required steps for the integration:

  • Customizing The static FSP configuration parameters are part of the FSP binary and can be customized by external tools that will be provided by Intel.
  • Rebasing The FSP is not Position Independent Code (PIC) and the whole FSP has to be rebased if it is placed at a location which is different from the preferred address during build process.
  • Placing Once the FSP binary is ready for integration, the boot loader build process needs to be modified to place this FSP binary at the specific rebasing location identified above.
  • Interfacing The boot loader needs to add code to setup the operating environment for the FSP, call the FSP with correct parameters and parse the FSP output to retrieve the necessary information returned by the FSP.

2.2 FSP Distribution Package

  • The FSP distribution package contains the following:
    • FSP Binary
    • FSP Integration Guide
    • BSF Configuration File
    • Data Structure Header File
  • The FSP configuration utility called BCT is available as a separate package. It can be downloaded from link mentioned in Section 1.3.

2.2.1 Package Layout

  • Docs (Auto generated)
    • Kabylake_FSP_Integration_Guide.pdf (this doc)
    • Kabylake_FSP_Integration_Guide.chm
  • Include
    • FsptUpd.h, FspmUpd.h and FspsUpd.h (FSP UPD structure and related definitions)
    • GpioSampleDef.h (Sample enum definitions for Gpio table)
  • KabylakeFspBinPkg.dec (EDKII declaration file for package)
  • Fsp.bsf (BSF file for configuring the data using BCT tool)
  • Fsp.fd (FSP Binary)


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP INTEGRATION

FSP INTEGRATION

3 FSP Integration

3.1 Assumptions Used in this Document

The FSP for the Kabylake platform is built with a preferred base address of 0xFFF40000 and so the reference code provided in the document assumes that the FSP is placed at this base address during the final boot loader build. Users may rebase the FSP binary at a different location with Intel's Binary Configuration Tool (BCT) before integrating to the boot loader.

For other assumptions and conventions, please refer section 8 in the FSP External Architecture Specification version 2.0.

3.2 Boot Flow

Please refer Chapter 7 in the FSP External Architecture Specification version 2.0 for Boot flow chart.

3.3 FSP INFO Header

The FSP has an Information Header that provides critical information that is required by the bootloader to successfully interface with the FSP. The structure of the FSP Information Header is documented in the FSP External Architecture Specification version 2.0 with a HeaderRevision of 3.

3.4 FSP Image ID and Revision

FSP information header contains an Image ID field and an Image Revision field that provide the identification and revision information of the FSP binary. It is important to verify these fields while integrating the FSP as API parameters could change over different FSP IDs and revisions. All the FSP FV segments(FSP-T, FSP-M and FSP-S) must have same FSP Image ID and revision number, using FV segments with different revision numbers in a single FSP image is not valid. The FSP API parameters documented in this integration guide are applicable for the Image ID and Revision specified as below.

The current FSP ImageId string in the FSP information header is $KBLFSP$ and the ImageRevision field is 0x03060000.(3.6.0.0).

3.5 FSP Global Data

FSP uses some amount of TempRam area to store FSP global data which contains some critical data like pointers to FSP information headers and UPD configuration regions, FSP/Bootloader stack pointers required for stack switching etc. HPET Timer register(2) 0xFED00148 is reserved to store address of this global data, and hence boot loader should not use this register for any other purpose. If TempRAM initialization is done by boot loader, then HPET has to be initialized to the base so that access to this register will work fine.

3.6 FSP APIs

This release of the Kabylake FSP supports the all APIs required by the FSP External Architecture Specification version 2.0. The FSP information header contains the address offset for these APIs. Register usage is described in the FSP External Architecture Specification version 2.0. Any usage not described by the specification is described in the individual sections below.

The below sections will highlight any changes that are specific to this FSP release.

3.6.1 TempRamInit API

Please refer Chapter 8.5 in the FSP External Architecture Specification version 2.0 for complete details including the prototype, parameters and return value details for this API.

TempRamInit does basic early initialization primarily setting up temporary RAM using cache. It returns ECX pointing to beginning of temporary memory and EDX pointing to end of temporary memory + 1. The total temporary ram currently available is from 0xFEF0_0000 to 0xFEF4_0000 out of which 0xFEF0_0000(ECX) to 0xFEF3_FF00(EDX) is usable area for both bootloader and FSP binary, remaining 0x100 bytes of space reserved by FSP for TempRamInit if temporary RAM initialization is done by FSP.

TempRamInit** also sets up the code caching of the region passed CodeCacheBase and CodeCacheLength, which are input parameters to TempRamInitApi. if 0 is passed in for CodeCacheBase, the base used will be 4 GB - 1 - length to be code cached instead of starting from CodeCacheBase.

Note
: when programming MTRR CodeCacheLength will be reduced, if SKU LLC size is smaller than the requested.

It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. If more than microcode update for the CPU is present, the microcode update with the latest revision is loaded.

FSPT_UPD.MicrocodeRegionBase** and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. If a region is passed, then if a newer microcode update revision is in the region, it will be loaded by the FSP.

MTRRs are programmed to the default values to have the following memory map:

Memory range | Cache Attribute
0xFEF00000 - 0x00040000 | Write back
CodeCacheBase - CodeCacheLength | Write protect

3.6.2 FspMemoryInit API

Please refer to Chapter 8.6 in the FSP external Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

The FspmUpdPtr is pointer to FSPM_UPD structure which is described in header file FspmUpd.h.

Boot Loader must pass valid CAR region for FSP stack use through FSPM_UPD.FspmArchUpd.StackBase and FSPM_UPD.FspmArchUpd.StackSize UPDs.

The minimum FSP stack size required for this revision of FSP is 160KB, stack base is 0xFEF17F00 by default.

The base address of HECI device (Bus 0, Device 22, Function 0) is required to be initialized prior to perform FspMemoryInit flow. The default address is programmed to 0xFED1A000.

Calculate memory map determining memory regions TSEG, IED, GTT, BDSM, ME stolen, Uncore PMRR, IOT, MOT, DPR, REMAP, TOLUD, TOUUD. Programming will be done at a different time.

3.6.3 TempRamExit API

Please refer to Chapter 8.7 in the FSP external Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

If Boot Loader initializes the Temporary RAM (CAR) and skip calling TempRamInit API, it is expected that bootloader must skip calling this API and bootloader will tear down the temporary memory area setup in the cache and bring the cache to normal mode of operation.

This revision of FSP doesn't have any fields/structure to pass as parameter for this API. Pass Null for TempRamExitParamPtr.

At the end of TempRamExit the original code and data caching are disabled. FSP will reconfigure all MTRRs as described in the table below for performance optimization.

Memory range | Cache Attribute
0x00000000 - 0x0009FFFF | Write back
0x000C0000 - Top of Low Memory | Write back
0xFF800000 - 0xFFFFFFFF (Flash region) | Write protect
0x1000000000 - Top of High Memory | Write back

If the boot loader wish to reconfigure the MTRRs differently, it can be overridden immediately after this API call.

3.6.4 FspSiliconInit API

Please refer to Chapter 8.8 in the FSP external Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

The FspsUpdPtr is pointer to FSPS_UPD structure which is described in header file FspsUpd.h.

It is expected that boot loader will program MTRRs for SBSP as needed after TempRamExit but before entering FspSiliconInit. If MTRRs are not programmed properly, the boot performance might be impacted.

The region of 0x5_8000 - 0x5_8FFF is used by FspSilicionInit for starting APs. If this data is important to bootloader, then bootloader needs to preserve it before calling FspSilicionInit.

It is a requirement for bootloader to have Firmware Interface Table (FIT), which contains pointers to each microcode. The microcode is loaded for all cores before reset vector. If more than one microcode update for the CPU is present, the latest revision is loaded.

MicrocodeRegionBase and MicrocodeRegionLength are both input parameters to TempRamInit and UPD for SiliconInit API. UPD has priority and will be searched for a later revision than TempRamInit. If MicrocodeRegionBase and MicrocodeRegionLength values are 0, FSP will not attempt to update the microcode. If a microcode region is passed, and if a later revision of microcode is present in this region, FSP will load it.

FSP initializes PCH audio including selecting HD Audio verb table and initializes Codec.

PCH required initialization is done for the following HECI, USB, HSIO, Integrated Sensor Hub, Display, Sky Cam, Camera, PCI Express, Vt-d, straps (cores, hyper-threading, BIST, ..)

FSP initializes CPU features: XD, VMX, AES, IED, HDC, x(2)Apic, Intel® Processor Trace, Three strike counter, Machine check, Cache pre-fetchers, Core PMRR, Power management.

Initializes HECI, DMI, Internal Graphics. Publish EFI_PEI_GRAPHICS_INFO_HOB during normal boot but this HOB will not be published during S3 resume as FSP will not launch the PEI Graphics PEIM during S3 resume.

Programs SA Bars: MchBar, DmiBar, EpBar, GdxcBar, EDRAM (if supported). Please refer to section 2.8 (MemoryMap) for the corresponding Bar values. GttMmadr (0xDF000000) and GmAdr(0xC0000000) are temporarily programmed and cleared after use in FSP.

On normal boot CPU S3 Resume Data HOB is produced in this phase. This CPU S3 Resume Data HOB is described in section 4.4. Unless UPD SkipMpInit is enabled, on S3 resume, this data (not the entire HOB) must be passed through UPD CpuS3ResumeData, and optionally final S3 boot MTRRs is passed through UPD CpuS3ResumeMtrrData. During S3 resume unless SkipMpInit is enabled, GDT base and length and IDT base and length on APs are programmed to that of the BSP.

3.6.5 NotifyPhase API

Please refer Chapter 8.9 in the FSP External Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

3.6.5.1 PostPciEnumeration Notification

This phase EnumInitPhaseAfterPciEnumeration is to be called after PCI enumeration but before execution of third party code such as option ROMs. Currently, nothing is done in this phase, but in the future updates, programming may be done in this phase.

3.6.5.2 ReadyToBoot Notification

This phase EnumInitPhaseReadyToBoot is to be called before giving control to boot. It includes some final initialization steps recommended by the BWG, including power management settings, Send ME Message EOP (End of Post).

3.6.5.3 EndOfFirmware Notification

This phase EnumInitEndOfFirmware is to be called before the firmware/preboot environment transfers management of all system resources to the OS or next level execution environment. It includes final locking of chipset registers

3.7 Memory Map

Below diagram represents the memory map allocated by FSP including the FSP specific regions.

System Memory Map

3.8 Porting recommendation

Here listed some notes or recommendation when porting with FSP.

3.8.1 Locking PAM register

FSP 2.0 introduced EndOfFirmware Notify phase callback which is a recommended place for locking PAM registers so FSP by default implemented this way. If it is still too early to lock PAM registers then the PAM locking code inside FSP can be disabled by UPD -> FSP_S_TEST_CONFIG -> SkipPamLock or SA policy -> _SI_PREMEM_POLICY_STRUCT -> SA_MISC_PEI_CONFIG -> SkipPamLock, and platform or wrapper code should do the PAM locking right before booting OS (so do it outside FSP instead) by programming one PCI config space register as below.

This PAM locking step has to been applied in all boot paths including S3 resume.To lock PAM regsiter:

MmioOr32 (B0: D0: F0: Register 0x80, BIT0)

3.8.2 Locking SMRAM register

Since SMRAM locking is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation, the FSP code by default will not lock it. The platform or FSP Wrapper code should lock SMRAM by below programming step before any 3rd partiy OpRom execution (and should be locked in S3 resume right before OS waking vector).

PciOr8 (B0: D0: F0: Register 0x88, BIT4); Note: it must be programmed by CF8/CFC Standard PCI access mechanism. (MMIO access will not work)

3.8.3 Locking SMI register

Global SMI bit is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation after SMM configuration. FSP by default will not lock it. Boot loader is responsible for locking below regsiters after SMM configuration. Set AcpiBase + 0x30[0] to 1b to enable global SMI. Set PMC PCI offset A0h[4] = 1b to lock SMI.

3.8.4 Verify below settings are correct for your platforms

Settings | Values
PCIEXBAR_BASE_ADDRESS | 0xE0000000 -> PciExBar
MCH_BASE_ADDRESS | 0xFED10000 -> MchBar
DMI_BASE_ADDRESS | 0xFED18000 -> DmiBar
EP_BASE_ADDRESS | 0xFED19000 -> EpBar
EDRAM_BASE_ADDRESS | 0xFED80000 -> EdramBar
DEFAULT_OPTION_ROM_TEMP_BAR | 0x80000000 -> OpRomScanTempMmioBar
DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT | 0xC0000000 -> OpRomScanTempMmioLimit
Note
:
  • It is recommended that you do not change these settings as it may require significant changes to the System Agent reference code.
  • Those memory regions should be reserved from any memory service functions in platform code so it will not cause any conflict when other modules or drivers allocating memory resource.
  • Boot Loader can use different value for PCIEXBAR_BASE_ADDRESS either by modifying the UPD (under FSP-T) or by overriding the PCIEXBAR (B0:D0:F0:R60h) before calling FspMemoryInit Api.
  • Boot Loader should avoid using conflicting address when reprogramming PCIEXBAR_BASE_ADDRESS than the recommended one.

3.8.5 FSP_STATUS_RESET_REQUIRED

As per FSP External Architecture Specification version 2.0, Any reset required in the FSP flow will be reported as return status FSP_STATUS_RESET_REQUIREDx by the API.It is the bootloader responsibility to reset the system according to the reset type requested.

Below table specifies the return status returned by FSP API and the requested reset type.

FSP_STATUS_RESET_REQUIRED Code | Reset Type requested
0x40000001 | Cold Reset
0x40000002 | Warm Reset
0x40000003 | Global Reset - Puts the system to Global reset through Heci or Full Reset through PCH
0x40000004 | Reserved
0x40000005 | Reserved
0x40000006 | Reserved
0x40000007 | Reserved
0x40000008 | Reserved


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP OUTPUT

FSP OUTPUT

4 FSP Output

The FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon.

Please refer to the Platform Initialization (PI) Specification - Volume 3: Shared Architectural Elements specification for PI Architectural HOBs.Please refer Chapter 9 in the FSP External Architecture Specification version 2.0 for details about FSP Architectural HOBs.

Below section describe the HOBs not covered in the above two specifications.

4.1 SMRAM Resource Descriptor HOB

The FSP will report the system SMRAM T-SEG range through a generic resource HOB if T-SEG is enabled. The owner field of the HOB identifies the owner as T-SEG.

#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }

4.2 SMBIOS INFO HOB

The FSP will report the SMBIOS through a HOB with below GUID. This information can be consumed by the bootloader to produce the SMBIOS tables. These structures are included as part of MemInfoHob.h , SmbiosCacheInfoHob.h & SmbiosProcessorInfoHob.h. Note: The Smbios Cache Info Hob & Smbios Processor Info Hob won't be published on S3 boot.

#define SI_MEMORY_INFO_DATA_HOB_GUID \
{ 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } };
typedef struct {
MrcDimmStatus Status; ///< See MrcDimmStatus for the definition of this field.
UINT8 DimmId;
UINT32 DimmCapacity; ///< DIMM size in MBytes.
UINT16 MfgId;
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE_DATA]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
} DIMM_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this channel should be used.
UINT8 ChannelId;
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
MRC_CH_TIMING Timing[MAX_PROFILE]; ///< The channel timing values.
DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
} CHANNEL_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this controller should be used.
UINT16 DeviceId; ///< The PCI device id of this memory controller.
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
} CONTROLLER_INFO;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
UINT8 Revision;
UINT16 DataWidth;
/// As defined in SMBIOS 3.0 spec
/// Section 7.18.2 and Table 75
UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
/// As defined in SMBIOS 3.0 spec
/// Section 7.17.3 and Table 72
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
UINT32 FreqMax;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
BOOLEAN XmpProfileEnable;
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE];
CONTROLLER_INFO Controller[MAX_NODE];
} MEMORY_INFO_DATA_HOB;
#define SI_MEMORY_PLATFORM_DATA_HOB \
{ 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
typedef struct {
UINT8 Revision;
UINT8 Reserved[3];
UINT32 BootMode;
UINT32 TsegSize;
UINT32 TsegBase;
UINT32 PrmrrSize;
UINT32 PrmrrBase;
UINT32 GttBase;
UINT32 MmioSize;
UINT32 PciEBaseAddress;
} MEMORY_PLATFORM_DATA;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
MEMORY_PLATFORM_DATA Data;
UINT8 *Buffer;
} MEMORY_PLATFORM_DATA_HOB;
#define SMBIOS_CACHE_INFO_HOB_GUID \
{ 0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7} }
///
/// SMBIOS Cache Info HOB Structure
///
typedef struct {
UINT16 ProcessorSocketNumber;
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
///String Buffer - each string terminated by NULL "0x00"
///String buffer terminated by double NULL "0x0000"
} SMBIOS_CACHE_INFO;
#define SMBIOS_PROCESSOR_INFO_HOB_GUID \
{ 0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71} }
///
/// SMBIOS Processor Info HOB Structure
///
typedef struct {
UINT16 TotalNumberOfSockets;
UINT16 CurrentSocketNumber;
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
///This info is used for both ProcessorFamily and ProcessorFamily2 fields
///See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
UINT16 ProcessorFamily;
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
///This info is used for both CoreCount & CoreCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.6
UINT16 CoreCount;
///This info is used for both CoreEnabled & CoreEnabled2 fields
///See detailed description in SMBIOS Spec v3.0 Section 7.5.7
UINT16 EnabledCoreCount;
///This info is used for both ThreadCount & ThreadCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.8
UINT16 ThreadCount;
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
/// String Buffer - each string terminated by NULL "0x00"
/// String buffer terminated by double NULL "0x0000"
} SMBIOS_PROCESSOR_INFO;

4.3 CHIPSETINIT INFO HOB

The FSP will report the ChipsetInit CRC through a HOB with below GUID. This information can be consumed by the bootloader to check if ChipsetInit CRC is matched between BIOS and ME. These structures are included as part of FspsUpd.h

#define CHIPSETINIT_INFO_HOB_GUID \
{ 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
///
/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
///
typedef struct {
UINT8 Revision;
UINT8 Rsvd[3];
UINT16 MeChipInitCrc;
UINT16 BiosChipInitCrc;
} CHIPSET_INIT_INFO;

4.4 CPU S3 Resume Data HOB

The FSP will report the CPU S3 Resume Data through a GUIDED HOB with below GUID. This data (not the entire HOB) must be passed during S3 resume passed in UPD CpuS3ResumeData except if UPD SkipMpInit is enabled.

#define CPU_S3_RESUME_DATA_HOB_GUID \
{ 0x3972d4c1, 0xf206, 0x463f, { 0x80, 0xa4, 0xd9, 0x62, 0x79, 0x0a, 0xe5, 0x49 }}


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP POSTCODE

FSP POSTCODE

5 FSP PostCode

The FSP outputs 16 bit postcode to indicate which API and in which module the execution is happening.

Bit Range | Description
Bit15 - Bit12 (X) | used to indicate the phase/api under which the code is executing
Bit11 - Bit8 (Y) | used to indicate the module
Bit7 (ZZ bit 7) | reserved for error
Bit6 - Bit0 (ZZ) | individual codes

5.1 PostCode Info

Below diagram represents the 16 bit PostCode usage in FSP.

5.1.1 TempRamInit API Status Codes (0xFxxx)

PostCode | Module | Description
0x0000 | FSP | TempRamInit API Entry (The change in upper byte is due to not enabling of the Port81 early in the boot)
0x007F | FSP | TempRamInit API Exit

5.1.2 FspMemoryInit API Status Codes (0xDxxx)

PostCode | Module | Description
0xD800 | FSP | FspMemoryInit API Entry
0xD87F | FSP | FSpMemoryInit API Exit
0xDA00 | SA | Pre-Mem SaInit Entry
0xDA01 | SA | DeviceConfigurePreMem Start
0xDA02 | SA | OverrideDev0Did Start
0xDA04 | SA | OverrideDev2Did Start
0xDA06 | SA | Programming SA Bars
0xDA08 | SA | Install SA HOBs
0xDA0A | SA | Reporting SA PCIe code version
0xDA0C | SA | SaSvInit Start
0xDA10 | SA | Initializing DMI
0xDA1F | SA | Initializing DMI/OPI Max PayLoad Size
0xDA20 | SA | Initializing SwitchableGraphics
0xDA30 | SA | Initializing SA PCIe
0xDA3F | SA | Programming PEG credit values Start
0xDA40 | SA | Initializing DMI Tc/Vc mapping
0xDA42 | SA | CheckOffboardPcieVga
0xDA44 | SA | CheckAndInitializePegVga
0xDA50 | SA | Initializing Graphics
0xDA7F | SA | Pre-Mem SaInit Exit
0xDB00 | PCH | PCH API Entry
0xDC00 | CPU | Pre-Mem Entry
0xDC7F | CPU | Pre-Mem Exit

5.1.3 TempRamExit API Status Codes (0xBxxx)

PostCode | Module | Description
0xB800 | FSP | TempRamExit API Entry
0xB87F | FSP | TempRamExit API Exit

5.1.3 FspSiliconInit API Status Codes (0x9xxx)

PostCode | Module | Description
0x9800 | FSP | FspSiliconInit API Entry
0x987F | FSP | FspSiliconInit API Exit
0x9A00 | SA | Post-Mem SaInit Entry
0x9A01 | SA | DeviceConfigure Start
0x9A02 | SA | UpdateSaHobPostMem Start
0x9A03 | SA | Initializing Pei Display
0x9A04 | SA | PeiGraphicsNotifyCallback Entry
0x9A05 | SA | CallPpiAndFillFrameBuffer
0x9A06 | SA | GraphicsPpiInit
0x9A07 | SA | GraphicsPpiGetMode
0x9A08 | SA | FillFrameBufferAndShowLogo
0x9A0F | SA | PeiGraphicsNotifyCallback Exit
0x9A10 | SA | Initializing SA Overclocking
0x9A14 | SA | Initializing SA SkyCam device
0x9A16 | SA | Initializing SA GMM device
0x9A18 | SA | Internal Device and Misc Configurations
0x9A1A | SA | SaProgramLlcWays Start
0x9A20 | SA | Initializing PciExpressInitPostMem
0x9A30 | SA | Initializing Vtd
0x9A32 | SA | Initializing Pavp
0x9A34 | SA | PeiInstallSmmAccessPpi Start
0x9A36 | SA | EdramWa Start
0x9A4F | SA | Post-Mem SaInit Exit
0x9A50 | SA | SaSecurityLock Start
0x9A5F | SA | SaSecurityLock End
0x9A60 | SA | SaSResetComplete Entry
0x9A61 | SA | Set BIOS_RESET_CPL to indicate all configurations complete
0x9A62 | SA | SaSvInit2 Start
0x9A63 | SA | GraphicsPmInit Start
0x9A64 | SA | SaPeiPolicyDump Start
0x9A6F | SA | SaSResetComplete Exit
0x9A70 | SA | SaS3ResumeAtEndOfPei Callback Entry
0x9A7F | SA | SaS3ResumeAtEndOfPei Callback Exit
0x9B7F | PCH | Post-Mem ScInit Entry
0x9B01 | PCH | Post-Mem Program HSIO ModPHY settings
0x9B02 | PCH | Post-Mem SMBus configuration
0x9B03 | PCH | Post-Mem LPC configuration
0x9B04 | PCH | Post-Mem SATA initizalization
0x9B05 | PCH | Post-Mem PCIe initizalization
0x9B06 | PCH | Post-Mem xHCI initizalization
0x9B07 | PCH | Post-Mem xDCI initizalization
0x9B08 | PCH | Post-Mem HD Audio initizalization
0x9B09 | PCH | Post-Mem GMM configuration
0x9B0A | PCH | Post-Mem LPSS initizalization
0x9B0B | PCH | Post-Mem SCS initizalization
0x9B0C | PCH | Post-Mem ISH initizalization
0x9B0D | PCH | Post-Mem ITSS configuration
0x9B40 | PCH | Post-Mem OnEndOfPEI Entry
0x9B4F | PCH | Post-Mem OnEndOfPEI Exit
0x9B7F | PCH | Post-Mem ScInit Exit
0x9C00 | CPU | Post-Mem Entry
0x9C7F | CPU | Post-Mem Exit

5.1.4 NotifyPhase API Status Codes (0x6xxx)

PostCode | Module | Description
0x6800 | FSP | NotifyPhase API Entry
0x687F | FSP | NotifyPhase API Exit


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class List

  • Class List
  • Class Index
  • Class Members
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C AUDIO_AZALIA_VERB_TABLE | Audio Azalia Verb Table structure
C AZALIA_HEADER | Azalia Header structure
C DIMM_INFO | Memory SMBIOS & OC Memory Data Hob
C FSP_M_CONFIG | Fsp M Configuration
C FSP_M_TEST_CONFIG | Fsp M Test Configuration
C FSP_S_CONFIG | Fsp S Configuration
C FSP_S_TEST_CONFIG | Fsp S Test Configuration
C FSP_T_CONFIG | Fsp T Configuration
C FSPM_UPD | Fsp M UPD Configuration
C FSPS_UPD | Fsp S UPD Configuration
C FSPT_CORE_UPD | Fsp T Core UPD
C FSPT_UPD | Fsp T UPD Configuration
C GPIO_CONFIG | GPIO configuration structure used for pin programming
C MEMORY_PLATFORM_DATA | Memory Platform Data Hob
C SI_CHIPSET_INIT_INFO | The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC
C SI_PCH_DEVICE_INTERRUPT_CONFIG | The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device
C SMBIOS_CACHE_INFO | SMBIOS Cache Info HOB Structure
C SMBIOS_PROCESSOR_INFO | SMBIOS Processor Info HOB Structure


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: AUDIO_AZALIA_VERB_TABLE Struct Reference

  • Class Index
  • Class Members
Public Attributes | List of all members
AUDIO_AZALIA_VERB_TABLE Struct Reference

Audio Azalia Verb Table structure. More...

#include <FspsUpd.h>

Collaboration diagram for AUDIO_AZALIA_VERB_TABLE:
[legend]

Public Attributes

AZALIA_HEADER Header
AZALIA PCH header.
UINT32 * Data
Pointer to the data buffer. Its length is specified in the header.

Detailed Description

Audio Azalia Verb Table structure.

Definition at line 58 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

AUDIO_AZALIA_VERB_TABLE Member List

This is the complete list of members for AUDIO_AZALIA_VERB_TABLE, including all inherited members.

Data | AUDIO_AZALIA_VERB_TABLE
Header | AUDIO_AZALIA_VERB_TABLE


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: AZALIA_HEADER Struct Reference

Public Attributes | List of all members
AZALIA_HEADER Struct Reference

Azalia Header structure. More...

#include <FspsUpd.h>

Public Attributes

UINT16 | VendorId
Codec Vendor ID.
UINT16 | DeviceId
Codec Device ID.
UINT8 | RevisionId
Revision ID of the codec. 0xFF matches any revision.
UINT8 | SdiNum
SDI number, 0xFF matches any SDI.
UINT16 | DataDwords
Number of data DWORDs pointed by the codec data buffer.
UINT32 | Reserved
Reserved for future use. Must be set to 0.

Detailed Description

Azalia Header structure.

Definition at line 46 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

AZALIA_HEADER Member List

This is the complete list of members for AZALIA_HEADER, including all inherited members.

DataDwords | AZALIA_HEADER
DeviceId | AZALIA_HEADER
Reserved | AZALIA_HEADER
RevisionId | AZALIA_HEADER
SdiNum | AZALIA_HEADER
VendorId | AZALIA_HEADER


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: DIMM_INFO Struct Reference

Public Attributes | List of all members
DIMM_INFO Struct Reference

Memory SMBIOS & OC Memory Data Hob. More...

#include <MemInfoHob.h>

Public Attributes

UINT8 | Status
See MrcDimmStatus for the definition of this field.
UINT32 | DimmCapacity
DIMM size in MBytes.
UINT8 | ModulePartNum [20]
Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes.
UINT8 | RankInDimm
The number of ranks in this DIMM.
UINT8 | SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 | SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 | SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 | SpdSave [MAX_SPD_SAVE]
Save SPD Manufacturing information needed for SMBIOS structure creation.

Detailed Description

Memory SMBIOS & OC Memory Data Hob.

Definition at line 188 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

DIMM_INFO Member List

This is the complete list of members for DIMM_INFO, including all inherited members.

DimmCapacity | DIMM_INFO
ModulePartNum | DIMM_INFO
RankInDimm | DIMM_INFO
SpdDramDeviceType | DIMM_INFO
SpdModuleMemoryBusWidth | DIMM_INFO
SpdModuleType | DIMM_INFO
SpdSave | DIMM_INFO
Status | DIMM_INFO


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_M_CONFIG Struct Reference

Public Attributes | List of all members
FSP_M_CONFIG Struct Reference

Fsp M Configuration. More...

#include <FspmUpd.h>

Public Attributes

UINT64 | PlatformMemorySize
Offset 0x0040 - Platform Reserved Memory Size The minimum platform memory size required to pass control into DXE.
UINT32 | MemorySpdPtr00
Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 Pointer to SPD data in Memory.
UINT32 | MemorySpdPtr01
Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 Pointer to SPD data in Memory.
UINT32 | MemorySpdPtr10
Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 Pointer to SPD data in Memory.
UINT32 | MemorySpdPtr11
Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 Pointer to SPD data in Memory.
UINT16 | MemorySpdDataLen
Offset 0x0058 - SPD Data Length Length of SPD Data 0x100:256 Bytes, 0x200:512 Bytes.
UINT8 | DqByteMapCh0 [12]
Offset 0x005A - Dq Byte Map CH0 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent.
UINT8 | DqByteMapCh1 [12]
Offset 0x0066 - Dq Byte Map CH1 Dq byte mapping between CPU and DRAM, Channel 1: board-dependent.
UINT8 | DqsMapCpu2DramCh0 [8]
Offset 0x0072 - Dqs Map CPU to DRAM CH 0 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent.
UINT8 | DqsMapCpu2DramCh1 [8]
Offset 0x007A - Dqs Map CPU to DRAM CH 1 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent.
UINT16 | RcompResistor [3]
Offset 0x0082 - RcompResister settings Indicates RcompReister settings: Board-dependent.
UINT16 | RcompTarget [5]
Offset 0x0088 - RcompTarget settings RcompTarget settings: board-dependent.
UINT8 | DqPinsInterleaved
Offset 0x0092 - Dqs Pins Interleaved Setting Indicates DqPinsInterleaved setting: board-dependent $EN_DIS.
UINT8 | CaVrefConfig
Offset 0x0093 - VREF_CA CA Vref routing: board-dependent 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 2:VREF_CA to CH_A and VREF_DQ_B to CH_B.
UINT8 | SmramMask
Offset 0x0094 - Smram Mask The SMM Regions AB-SEG and/or H-SEG reserved 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both.
UINT8 | MrcFastBoot
Offset 0x0095 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC $EN_DIS.
UINT8 | UnusedUpdSpace0 [2]
Offset 0x0096.
UINT32 | IedSize
Offset 0x0098 - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied 0 : Disable, 0x400000 : Enable.
UINT32 | TsegSize
Offset 0x009C - Tseg Size Size of SMRAM memory reserved. More...
UINT16 | MmioSize
Offset 0x00A0 - MMIO Size Size of MMIO space reserved for devices. More...
UINT8 | ProbelessTrace
Offset 0x00A2 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable. More...
UINT8 | UnusedUpdSpace1 [2]
Offset 0x00A3.
UINT8 | SmbusEnable
Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller. More...
UINT8 | EnableTraceHub
Offset 0x00A6 - Enable Trace Hub Enable/disable Trace Hub function. More...
UINT8 | UnusedUpdSpace2 [60]
Offset 0x00A7.
UINT8 | IgdDvmt50PreAlloc
Offset 0x00E3 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. More...
UINT8 | InternalGfx
Offset 0x00E4 - Internal Graphics Enable/disable internal graphics. More...
UINT8 | ApertureSize
Offset 0x00E5 - Aperture Size Select the Aperture Size. More...
UINT8 | SaGv
Offset 0x00E6 - SA GV System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. More...
UINT8 | RMT
Offset 0x00E7 - Rank Margin Tool Enable/disable Rank Margin Tool. More...
UINT16 | DdrFreqLimit
Offset 0x00E8 - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. More...
UINT8 | UserBd
Offset 0x00EA - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server.
UINT8 | UnusedUpdSpace3 [105]
Offset 0x00EB.
UINT32 | MmaTestContentPtr
Offset 0x0154 - MMA Test Content Pointer Pointer to MMA Test Content in Memory.
UINT32 | MmaTestContentSize
Offset 0x0158 - MMA Test Content Size Size of MMA Test Content in Memory.
UINT32 | MmaTestConfigPtr
Offset 0x015C - MMA Test Config Pointer Pointer to MMA Test Config in Memory.
UINT32 | MmaTestConfigSize
Offset 0x0160 - MMA Test Config Size Size of MMA Test Config in Memory.
UINT8 | UnusedUpdSpace4 [19]
Offset 0x0164.
UINT8 | SpdProfileSelected
Offset 0x0177 - SPD Profile Selected Select DIMM timing profile. More...
UINT16 | VddVoltage
Offset 0x0178 - Memory Voltage Memory Voltage Override (Vddq). More...
UINT8 | RefClk
Offset 0x017A - Memory Reference Clock Automatic, 100MHz, 133MHz. More...
UINT8 | Ratio
Offset 0x017B - Memory Ratio Automatic or the frequency will equal ratio times reference clock. More...
UINT8 | OddRatioMode
Offset 0x017C - QCLK Odd Ratio Adds 133 or 100 MHz to QCLK frequency, depending on RefClk $EN_DIS.
UINT8 | tCL
Offset 0x017D - tCL CAS Latency, 0: AUTO, max: 31.
UINT16 | tFAW
Offset 0x017E - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63.
UINT16 | tRAS
Offset 0x0180 - tRAS RAS Active Time, 0: AUTO, max: 64.
UINT8 | tCWL
Offset 0x0182 - tCWL Min CAS Write Latency Delay Time, 0: AUTO, max: 20.
UINT8 | tRCDtRP
Offset 0x0183 - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63.
UINT16 | tREFI
Offset 0x0184 - tREFI Refresh Interval, 0: AUTO, max: 65535.
UINT16 | tRFC
Offset 0x0186 - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 1023.
UINT8 | tRRD
Offset 0x0188 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 15.
UINT8 | tRTP
Offset 0x0189 - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. More...
UINT8 | tWR
Offset 0x018A - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24.
UINT8 | tWTR
Offset 0x018B - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28.
UINT8 | NModeSupport
Offset 0x018C - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N.
UINT8 | DllBwEn0
Offset 0x018D - DllBwEn[0] DllBwEn[0], for 1067 (0..7)
UINT8 | DllBwEn1
Offset 0x018E - DllBwEn[1] DllBwEn[1], for 1333 (0..7)
UINT8 | DllBwEn2
Offset 0x018F - DllBwEn[2] DllBwEn[2], for 1600 (0..7)
UINT8 | DllBwEn3
Offset 0x0190 - DllBwEn[3] DllBwEn[3], for 1867 and up (0..7)
UINT8 | CmdTriStateDis
Offset 0x0191 - Command Tristate Support Enable/Disable Command Tristate; 0: Enable; 1: Disable. More...
UINT8 | UnusedUpdSpace5 [14]
Offset 0x0192.
UINT32 | Heci1BarAddress
Offset 0x01A0 - HECI1 BAR address BAR address of HECI1.
UINT32 | Heci2BarAddress
Offset 0x01A4 - HECI2 BAR address BAR address of HECI2.
UINT32 | Heci3BarAddress
Offset 0x01A8 - HECI3 BAR address BAR address of HECI3.
UINT8 | HeciTimeouts
Offset 0x01AC - HECI Timeouts Enable/Disable. More...
UINT8 | UnusedUpdSpace6 [115]
Offset 0x01AD.
UINT16 | SgDelayAfterPwrEn
Offset 0x0220 - SG dGPU Power Delay SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds.
UINT16 | SgDelayAfterHoldReset
Offset 0x0222 - SG dGPU Reset Delay SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds.
UINT16 | MmioSizeAdjustment
Offset 0x0224 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size.
UINT8 | DmiGen3ProgramStaticEq
Offset 0x0226 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Static Presets. More...
UINT8 | Peg0Enable
Offset 0x0227 - Enable/Disable PEG 0 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO.
UINT8 | Peg1Enable
Offset 0x0228 - Enable/Disable PEG 1 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO.
UINT8 | Peg2Enable
Offset 0x0229 - Enable/Disable PEG 2 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO.
UINT8 | Peg0MaxLinkSpeed
Offset 0x022A - PEG 0 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | Peg1MaxLinkSpeed
Offset 0x022B - PEG 1 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | Peg2MaxLinkSpeed
Offset 0x022C - PEG 2 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | Peg0MaxLinkWidth
Offset 0x022D - PEG 0 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8.
UINT8 | Peg1MaxLinkWidth
Offset 0x022E - PEG 1 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4 0:Auto, 1:x1, 2:x2, 3:x4.
UINT8 | Peg2MaxLinkWidth
Offset 0x022F - PEG 2 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
UINT8 | Peg0PowerDownUnusedLanes
Offset 0x0230 - Power down unused lanes on PEG 0 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 | Peg1PowerDownUnusedLanes
Offset 0x0231 - Power down unused lanes on PEG 1 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 | Peg2PowerDownUnusedLanes
Offset 0x0232 - Power down unused lanes on PEG 2 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 | InitPcieAspmAfterOprom
Offset 0x0233 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM programming will happen in relation to the Oprom. More...
UINT8 | PegDisableSpreadSpectrumClocking
Offset 0x0234 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking. More...
UINT8 | DmiGen3RootPortPreset [4]
Offset 0x0235 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. More...
UINT8 | DmiGen3EndPointPreset [4]
Offset 0x0239 - DMI Gen3 End port preset values per lane Used for programming DMI Gen3 preset values per lane. More...
UINT8 | DmiGen3EndPointHint [4]
Offset 0x023D - DMI Gen3 End port Hint values per lane Used for programming DMI Gen3 Hint values per lane. More...
UINT8 | DmiGen3RxCtlePeaking [2]
Offset 0x0241 - DMI Gen3 RxCTLEp per-Bundle control Range: 0-15, 3 is default for each bundle, must be specified based upon platform design.
UINT8 | DmiDeEmphasis
Offset 0x0243 - DeEmphasis control for DMI DeEmphasis control for DMI. More...
UINT8 | PegGen3RxCtlePeaking [8]
Offset 0x0244 - PEG Gen3 RxCTLEp per-Bundle control Range: 0-15, 12 is default for each bundle, must be specified based upon platform design.
UINT32 | PegDataPtr
Offset 0x024C - Memory data pointer for saved preset search results The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. More...
UINT8 | PegGpioData [16]
Offset 0x0250 - PEG PERST# GPIO information The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary.
UINT8 | UnusedUpdSpace7 [1]
Offset 0x0260.
UINT8 | PegRootPortHPE [3]
Offset 0x0261 - PCIe Hot Plug Enable/Disable per port 0(Default): Disable, 1: Enable.
UINT32 | GttMmAdr
Offset 0x0264 - Temporary MMIO address for GTTMMADR The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary.
UINT16 | GttSize
Offset 0x0268 - Selection of iGFX GTT Memory size 1=2MB, 2=4MB, 3=8MB, Default is 3 1:2MB, 2:4MB, 3:8MB.
UINT8 | PrimaryDisplay
Offset 0x026A - Selection of the primary display device 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics.
UINT8 | SaRtd3Pcie0Gpio [24]
Offset 0x026B - Switchable Graphics GPIO information for PEG 0 Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs.
UINT8 | SaRtd3Pcie1Gpio [24]
Offset 0x0283 - Switchable Graphics GPIO information for PEG 1 Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs.
UINT8 | SaRtd3Pcie2Gpio [24]
Offset 0x029B - Switchable Graphics GPIO information for PEG 2 Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs.
UINT8 | RootPortDev
Offset 0x02B3 - PEG root port Device number for Switchable Graphics dGPU Device number to indicate which PEG root port has dGPU.
UINT8 | RootPortFun
Offset 0x02B4 - PEG root port Function number for Switchable Graphics dGPU Function number to indicate which PEG root port has dGPU.
UINT8 | TxtImplemented
Offset 0x02B5 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. More...
UINT8 | SaOcSupport
Offset 0x02B6 - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport $EN_DIS.
UINT8 | GtsVoltageMode
Offset 0x02B7 - GT slice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
UINT8 | GtusVoltageMode
Offset 0x02B8 - GT unslice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
UINT8 | GtsMaxOcRatio
Offset 0x02B9 - Maximum GTs turbo ratio override 0(Default)=Minimal/Auto, 60=Maximum.
UINT16 | GtsVoltageOffset
Offset 0x02BA - The voltage offset applied to GT slice 0(Default)=Minimal, 1000=Maximum.
UINT16 | GtsVoltageOverride
Offset 0x02BC - The GT slice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 | GtsExtraTurboVoltage
Offset 0x02BE - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 | GtusVoltageOffset
Offset 0x02C0 - voltage offset applied to GT unslice 0(Default)=Minimal, 2000=Maximum.
UINT16 | GtusVoltageOverride
Offset 0x02C2 - GT unslice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 | GtusExtraTurboVoltage
Offset 0x02C4 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 | SaVoltageOffset
Offset 0x02C6 - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum.
UINT8 | EdramRatio
Offset 0x02C8 - EDRAM ratio override EdramRatio is deprecated on Kabylake.
UINT8 | GtusMaxOcRatio
Offset 0x02C9 - Maximum GTus turbo ratio override 0(Default)=Minimal, 60=Maximum.
UINT8 | BistOnReset
Offset 0x02CA - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable. More...
UINT8 | SkipStopPbet
Offset 0x02CB - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_DIS.
UINT8 | EnableC6Dram
Offset 0x02CC - C6DRAM power gating feature This feature is not supported. More...
UINT8 | OcSupport
Offset 0x02CD - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS.
UINT8 | OcLock
Offset 0x02CE - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. More...
UINT8 | CoreMaxOcRatio
Offset 0x02CF - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. More...
UINT8 | CoreVoltageMode
Offset 0x02D0 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override. More...
UINT8 | RingMinOcRatio
Offset 0x02D1 - Minimum clr turbo ratio override Minimum clr turbo ratio override. More...
UINT8 | RingMaxOcRatio
Offset 0x02D2 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. More...
UINT8 | HyperThreading
Offset 0x02D3 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable $EN_DIS.
UINT8 | CpuRatioOverride
Offset 0x02D4 - Enable or Disable CPU Ratio Override Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. More...
UINT8 | CpuRatio
Offset 0x02D5 - CPU ratio value CPU ratio value. More...
UINT8 | BootFrequency
Offset 0x02D6 - Boot frequency Sets the boot frequency starting from reset vector. More...
UINT8 | ActiveCoreCount
Offset 0x02D7 - Number of active cores Number of active cores(Depends on Number of cores). More...
UINT8 | FClkFrequency
Offset 0x02D8 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). More...
UINT8 | JtagC10PowerGateDisable
Offset 0x02D9 - Power JTAG in C10 and deeper power states Power JTAG in C10 and deeper power states; 0: Disable; 1: Enable. More...
UINT8 | VmxEnable
Offset 0x02DA - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. More...
UINT8 | Avx2RatioOffset
Offset 0x02DB - AVX2 Ratio Offset 0(Default)= No Offset. More...
UINT16 | CoreVoltageOverride
Offset 0x02DC - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies. More...
UINT16 | CoreVoltageAdaptive
Offset 0x02DE - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. More...
UINT16 | CoreVoltageOffset
Offset 0x02E0 - Core Turbo voltage Offset The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000.
UINT8 | CorePllVoltageOffset
Offset 0x02E2 - Core PLL voltage offset Core PLL voltage offset. More...
UINT8 | RingDownBin
Offset 0x02E3 - Ring Downbin Ring Downbin enable/disable. More...
UINT8 | BclkAdaptiveVoltage
Offset 0x02E4 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. More...
UINT8 | BiosGuard
Offset 0x02E5 - BiosGuard Enable/Disable. More...
UINT8 | EnableSgx
Offset 0x02E6 - EnableSgx Enable/Disable. More...
UINT8 | Txt
Offset 0x02E7 - Txt Enable/Disable. More...
UINT32 | PrmrrSize
Offset 0x02E8 - PrmrrSize Enable/Disable. More...
UINT32 | SinitMemorySize
Offset 0x02EC - SinitMemorySize Enable/Disable. More...
UINT64 | TxtDprMemoryBase
Offset 0x02F0 - TxtDprMemoryBase Enable/Disable. More...
UINT32 | TxtDprMemorySize
Offset 0x02F8 - TxtDprMemorySize Enable/Disable. More...
UINT32 | TxtHeapMemorySize
Offset 0x02FC - TxtHeapMemorySize Enable/Disable. More...
UINT8 | FlashWearOutProtection
Offset 0x0300 - FlashWearOutProtection Enable/Disable. More...
UINT8 | TvbRatioClipping
Offset 0x0301 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled. More...
UINT8 | TvbVoltageOptimization
Offset 0x0302 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default). More...
UINT8 | ReservedSecurityPreMem [7]
Offset 0x0303 - ReservedSecurityPreMem Reserved for Security Pre-Mem $EN_DIS.
UINT8 | PchHpetEnable
Offset 0x030A - PCH HPET Enabled Enable/disable PCH HPET. More...
UINT8 | PchHpetBdfValid
Offset 0x030B - PCH HPET BDF valid Whether the BDF value is valid. More...
UINT32 | PchHpetBase
Offset 0x030C - The HPET Base Address The HPET base address. More...
UINT8 | PchHpetBusNumber
Offset 0x0310 - PCH HPET Bus Number Bus Number HPETn used as Requestor / Completer ID. More...
UINT8 | PchHpetDeviceNumber
Offset 0x0311 - PCH HPET Device Number Device Number HPETn used as Requestor / Completer ID. More...
UINT8 | PchHpetFunctionNumber
Offset 0x0312 - PCH HPET Function Number Function Number HPETn used as Requestor / Completer ID. More...
UINT8 | PchPcieHsioRxSetCtleEnable [24]
Offset 0x0313 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value.
UINT8 | PchPcieHsioRxSetCtle [24]
Offset 0x032B - PCH HSIO PCIE Rx Set Ctle Value PCH PCIe Gen 3 Set CTLE Value.
UINT8 | PchPcieHsioTxGen1DownscaleAmpEnable [24]
Offset 0x0343 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen1DownscaleAmp [24]
Offset 0x035B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
UINT8 | PchPcieHsioTxGen2DownscaleAmpEnable [24]
Offset 0x0373 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen2DownscaleAmp [24]
Offset 0x038B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
UINT8 | PchPcieHsioTxGen3DownscaleAmpEnable [24]
Offset 0x03A3 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen3DownscaleAmp [24]
Offset 0x03BB - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
UINT8 | PchPcieHsioTxGen1DeEmphEnable [24]
Offset 0x03D3 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen1DeEmph [24]
Offset 0x03EB - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
UINT8 | PchPcieHsioTxGen2DeEmph3p5Enable [24]
Offset 0x0403 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen2DeEmph3p5 [24]
Offset 0x041B - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
UINT8 | PchPcieHsioTxGen2DeEmph6p0Enable [24]
Offset 0x0433 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen2DeEmph6p0 [24]
Offset 0x044B - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
UINT8 | PchSataHsioRxGen1EqBoostMagEnable [8]
Offset 0x0463 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioRxGen1EqBoostMag [8]
Offset 0x046B - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 | PchSataHsioRxGen2EqBoostMagEnable [8]
Offset 0x0473 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioRxGen2EqBoostMag [8]
Offset 0x047B - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 | PchSataHsioRxGen3EqBoostMagEnable [8]
Offset 0x0483 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioRxGen3EqBoostMag [8]
Offset 0x048B - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 | PchSataHsioTxGen1DownscaleAmpEnable [8]
Offset 0x0493 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen1DownscaleAmp [8]
Offset 0x049B - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 | PchSataHsioTxGen2DownscaleAmpEnable [8]
Offset 0x04A3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen2DownscaleAmp [8]
Offset 0x04AB - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 | PchSataHsioTxGen3DownscaleAmpEnable [8]
Offset 0x04B3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen3DownscaleAmp [8]
Offset 0x04BB - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 | PchSataHsioTxGen1DeEmphEnable [8]
Offset 0x04C3 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen1DeEmph [8]
Offset 0x04CB - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT8 | PchSataHsioTxGen2DeEmphEnable [8]
Offset 0x04D3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen2DeEmph [8]
Offset 0x04DB - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT8 | PchSataHsioTxGen3DeEmphEnable [8]
Offset 0x04E3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen3DeEmph [8]
Offset 0x04EB - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT8 | PchLpcEnhancePort8xhDecoding
Offset 0x04F3 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h. More...
UINT16 | PchAcpiBase
Offset 0x04F4 - PCH Acpi Base Power management I/O base address. More...
UINT8 | PchPort80Route
Offset 0x04F6 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. More...
UINT8 | SmbusArpEnable
Offset 0x04F7 - Enable SMBus ARP support Enable SMBus ARP support. More...
UINT16 | PchSmbusIoBase
Offset 0x04F8 - SMBUS Base Address SMBUS Base Address (IO space).
UINT8 | PchNumRsvdSmbusAddresses
Offset 0x04FA - Number of RsvdSmbusAddressTable. More...
UINT8 | UnusedUpdSpace8
Offset 0x04FB.
UINT32 | RsvdSmbusAddressTablePtr
Offset 0x04FC - Point of RsvdSmbusAddressTable Array of addresses reserved for non-ARP-capable SMBus devices.
UINT32 | TraceHubMemReg0Size
Offset 0x0500 - Trace Hub Memory Region 0 Trace Hub Memory Region 0.
UINT32 | TraceHubMemReg1Size
Offset 0x0504 - Trace Hub Memory Region 1 Trace Hub Memory Region 1.
UINT32 | PcieRpEnableMask
Offset 0x0508 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. More...
UINT8 | PcdDebugInterfaceFlags
Offset 0x050C - Debug Interfaces Debug Interfaces. More...
UINT8 | PcdSerialIoUartNumber
Offset 0x050D - SerialIo Uart Number Selection Select SerialIo Uart Controller for debug. More...
UINT8 | PcdIsaSerialUartBase
Offset 0x050E - ISA Serial Base selection Select ISA Serial Base address. More...
UINT8 | PchPmPciePllSsc
Offset 0x050F - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. More...
UINT8 | PeciC10Reset
Offset 0x0510 - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command; 0: Disable; 1: Enable. More...
UINT8 | PeciSxReset
Offset 0x0511 - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. More...
UINT8 | PcdSerialDebugBaudRate
Offset 0x0512 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. More...
UINT8 | PcdSerialDebugLevel
Offset 0x0513 - PcdSerialDebugLevel Serial Debug Message Level. More...
UINT8 | EvLoader
Offset 0x0514 - Enable or Disable EV Loader Enable or Disable EV Loader; 0: Disable; 1: Enable. More...
UINT8 | GtPllVoltageOffset
Offset 0x0515 - GT PLL voltage offset Core PLL voltage offset. More...
UINT8 | RingPllVoltageOffset
Offset 0x0516 - Ring PLL voltage offset Core PLL voltage offset. More...
UINT8 | SaPllVoltageOffset
Offset 0x0517 - System Agent PLL voltage offset Core PLL voltage offset. More...
UINT8 | McPllVoltageOffset
Offset 0x0518 - Memory Controller PLL voltage offset Core PLL voltage offset. More...
UINT8 | RealtimeMemoryTiming
Offset 0x0519 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled. More...
UINT8 | Avx3RatioOffset
Offset 0x051A - AVX3 Ratio Offset 0(Default)= No Offset. More...
UINT8 | CleanMemory
Offset 0x051B - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. More...
UINT8 | TjMaxOffset
Offset 0x051C - TjMax Offset TjMax offset. More...
UINT8 | ReservedFspmUpd [3]
Offset 0x051D.

Detailed Description

Fsp M Configuration.

Definition at line 57 of file FspmUpd.h.

Member Data Documentation

UINT8 FSP_M_CONFIG::ActiveCoreCount

Offset 0x02D7 - Number of active cores Number of active cores(Depends on Number of cores).

0: All;1: 1 ;2: 2 ;3: 3 0:All, 1:1, 2:2, 3:3

Definition at line 797 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ApertureSize

Offset 0x00E5 - Aperture Size Select the Aperture Size.

0:128 MB, 1:256 MB, 2:512 MB

Definition at line 209 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Avx2RatioOffset

Offset 0x02DB - AVX2 Ratio Offset 0(Default)= No Offset.

Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.

Definition at line 822 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Avx3RatioOffset

Offset 0x051A - AVX3 Ratio Offset 0(Default)= No Offset.

Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.

Definition at line 1272 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BclkAdaptiveVoltage

Offset 0x02E4 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.

0: Disable; 1: Enable $EN_DIS

Definition at line 858 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BiosGuard

Offset 0x02E5 - BiosGuard Enable/Disable.

0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS

Definition at line 864 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BistOnReset

Offset 0x02CA - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 717 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BootFrequency

Offset 0x02D6 - Boot frequency Sets the boot frequency starting from reset vector.

  • 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance.
    Note
    If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode. 0:0, 1:1, 2:2

Definition at line 790 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CleanMemory

Offset 0x051B - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory.

$EN_DIS

Definition at line 1278 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CmdTriStateDis

Offset 0x0191 - Command Tristate Support Enable/Disable Command Tristate; 0: Enable; 1: Disable.

$EN_DIS

Definition at line 387 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CoreMaxOcRatio

Offset 0x02CF - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit.

0: Hardware defaults. Range: 0-255

Definition at line 747 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CorePllVoltageOffset

Offset 0x02E2 - Core PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63

Definition at line 844 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::CoreVoltageAdaptive

Offset 0x02DE - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.

Valid Range 0 to 2000

Definition at line 834 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CoreVoltageMode

Offset 0x02D0 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override.

$EN_DIS

Definition at line 753 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::CoreVoltageOverride

Offset 0x02DC - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies.

Valid Range 0 to 2000

Definition at line 828 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CpuRatio

Offset 0x02D5 - CPU ratio value CPU ratio value.

Valid Range 0 to 63

Definition at line 782 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CpuRatioOverride

Offset 0x02D4 - Enable or Disable CPU Ratio Override Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable.

Note
If disabled, BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting. $EN_DIS

Definition at line 777 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::DdrFreqLimit

Offset 0x00E8 - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz.

Options are 1067, 1333, 1600, 1867, 2133, 2400 and 0 for Auto. 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto

Definition at line 230 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiDeEmphasis

Offset 0x0243 - DeEmphasis control for DMI DeEmphasis control for DMI.

0=-6dB, 1(Default)=-3.5 dB 0: -6dB, 1: -3.5dB

Definition at line 566 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3EndPointHint[4]

Offset 0x023D - DMI Gen3 End port Hint values per lane Used for programming DMI Gen3 Hint values per lane.

Range: 0-6, 2 is default for each lane

Definition at line 555 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3EndPointPreset[4]

Offset 0x0239 - DMI Gen3 End port preset values per lane Used for programming DMI Gen3 preset values per lane.

Range: 0-9, 7 is default for each lane

Definition at line 550 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3ProgramStaticEq

Offset 0x0226 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Static Presets.

Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS

Definition at line 441 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3RootPortPreset[4]

Offset 0x0235 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane.

Range: 0-9, 4 is default for each lane

Definition at line 545 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EnableC6Dram

Offset 0x02CC - C6DRAM power gating feature This feature is not supported.

BIOS is required to disable. 0: Disable $EN_DIS

Definition at line 729 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EnableSgx

Offset 0x02E6 - EnableSgx Enable/Disable.

0: Disable, Enable/Disable SGX feature, 1: enable $EN_DIS

Definition at line 870 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EnableTraceHub

Offset 0x00A6 - Enable Trace Hub Enable/disable Trace Hub function.

$EN_DIS

Definition at line 187 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EvLoader

Offset 0x0514 - Enable or Disable EV Loader Enable or Disable EV Loader; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1235 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::FClkFrequency

Offset 0x02D8 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX).

1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved

Definition at line 804 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::FlashWearOutProtection

Offset 0x0300 - FlashWearOutProtection Enable/Disable.

0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable $EN_DIS

Definition at line 907 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::GtPllVoltageOffset

Offset 0x0515 - GT PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63 0x0:0xFF

Definition at line 1241 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::HeciTimeouts

Offset 0x01AC - HECI Timeouts Enable/Disable.

0: Disable, disable timeout check for HECI, 1: enable $EN_DIS

Definition at line 412 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::IgdDvmt50PreAlloc

Offset 0x00E3 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics.

0x00:0 MB, 0x01:32 MB, 0x02:64 MB

Definition at line 197 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::InitPcieAspmAfterOprom

Offset 0x0233 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM programming will happen in relation to the Oprom.

Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume 0:Before, 1:After

Definition at line 533 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::InternalGfx

Offset 0x00E4 - Internal Graphics Enable/disable internal graphics.

$EN_DIS

Definition at line 203 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::JtagC10PowerGateDisable

Offset 0x02D9 - Power JTAG in C10 and deeper power states Power JTAG in C10 and deeper power states; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 810 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::McPllVoltageOffset

Offset 0x0518 - Memory Controller PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63 0x0:0xFF

Definition at line 1259 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::MmioSize

Offset 0x00A0 - MMIO Size Size of MMIO space reserved for devices.

0(Default)=Auto, non-Zero=size in MB

Definition at line 164 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::OcLock

Offset 0x02CE - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 741 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdDebugInterfaceFlags

Offset 0x050C - Debug Interfaces Debug Interfaces.

BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used.

Definition at line 1184 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdIsaSerialUartBase

Offset 0x050E - ISA Serial Base selection Select ISA Serial Base address.

Default is 0x3F8. 0:0x3F8, 1:0x2F8

Definition at line 1196 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdSerialDebugBaudRate

Offset 0x0512 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages.

3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200

Definition at line 1220 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdSerialDebugLevel

Offset 0x0513 - PcdSerialDebugLevel Serial Debug Message Level.

0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info and Verbose

Definition at line 1229 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdSerialIoUartNumber

Offset 0x050D - SerialIo Uart Number Selection Select SerialIo Uart Controller for debug.

0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2

Definition at line 1190 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::PchAcpiBase

Offset 0x04F4 - PCH Acpi Base Power management I/O base address.

Default is 0x1800.

Definition at line 1131 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::PchHpetBase

Offset 0x030C - The HPET Base Address The HPET base address.

Default is 0xFED00000.

Definition at line 945 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchHpetBdfValid

Offset 0x030B - PCH HPET BDF valid Whether the BDF value is valid.

0: Disable; 1: Enable. $EN_DIS

Definition at line 940 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchHpetBusNumber

Offset 0x0310 - PCH HPET Bus Number Bus Number HPETn used as Requestor / Completer ID.

Default is 0xF0.

Definition at line 950 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchHpetDeviceNumber

Offset 0x0311 - PCH HPET Device Number Device Number HPETn used as Requestor / Completer ID.

Default is 0x1F.

Definition at line 955 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchHpetEnable

Offset 0x030A - PCH HPET Enabled Enable/disable PCH HPET.

$EN_DIS

Definition at line 934 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchHpetFunctionNumber

Offset 0x0312 - PCH HPET Function Number Function Number HPETn used as Requestor / Completer ID.

Default is 0x00.

Definition at line 960 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchLpcEnhancePort8xhDecoding

Offset 0x04F3 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h.

$EN_DIS

Definition at line 1126 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchNumRsvdSmbusAddresses

Offset 0x04FA - Number of RsvdSmbusAddressTable.

The number of elements in the RsvdSmbusAddressTable.

Definition at line 1153 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchPmPciePllSsc

Offset 0x050F - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage.

The default is 0xFF: AUTO - No BIOS override.

Definition at line 1202 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchPort80Route

Offset 0x04F6 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.

$EN_DIS

Definition at line 1137 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::PcieRpEnableMask

Offset 0x0508 - Enable PCIE RP Mask Enable/disable PCIE Root Ports.

0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.

Definition at line 1178 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PeciC10Reset

Offset 0x0510 - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1208 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PeciSxReset

Offset 0x0511 - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1214 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::PegDataPtr

Offset 0x024C - Memory data pointer for saved preset search results The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots.

Range: 0-0xFFFFFFFF, default is 0

Definition at line 578 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PegDisableSpreadSpectrumClocking

Offset 0x0234 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking.

Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing 0:Normal Operation, 1:Disable SSC

Definition at line 540 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::PrmrrSize

Offset 0x02E8 - PrmrrSize Enable/Disable.

0: Disable, define default value of PrmrrSize , 1: enable

Definition at line 881 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ProbelessTrace

Offset 0x00A2 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable.

Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. $EN_DIS

Definition at line 171 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Ratio

Offset 0x017B - Memory Ratio Automatic or the frequency will equal ratio times reference clock.

Set to Auto to recalculate memory timings listed below. 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15

Definition at line 293 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RealtimeMemoryTiming

Offset 0x0519 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled.

When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE. 0: Disabled, 1: Enabled

Definition at line 1266 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RefClk

Offset 0x017A - Memory Reference Clock Automatic, 100MHz, 133MHz.

0:Auto, 1:133MHz, 2:100MHz

Definition at line 286 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingDownBin

Offset 0x02E3 - Ring Downbin Ring Downbin enable/disable.

When enabled, CPU will ensure the ring ratio is always lower than the core ratio. 0: Disable; 1: Enable. $EN_DIS

Definition at line 851 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingMaxOcRatio

Offset 0x02D2 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit.

0: Hardware defaults. Range: 0-255

Definition at line 764 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingMinOcRatio

Offset 0x02D1 - Minimum clr turbo ratio override Minimum clr turbo ratio override.

0: Hardware defaults. Range: 0-255

Definition at line 758 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingPllVoltageOffset

Offset 0x0516 - Ring PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63 0x0:0xFF

Definition at line 1247 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RMT

Offset 0x00E7 - Rank Margin Tool Enable/disable Rank Margin Tool.

$EN_DIS

Definition at line 223 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SaGv

Offset 0x00E6 - SA GV System Agent dynamic frequency support and when enabled memory will be training at two different frequencies.

Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled. 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled

Definition at line 217 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SaPllVoltageOffset

Offset 0x0517 - System Agent PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63 0x0:0xFF

Definition at line 1253 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::SinitMemorySize

Offset 0x02EC - SinitMemorySize Enable/Disable.

0: Disable, define default value of SinitMemorySize , 1: enable

Definition at line 886 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SmbusArpEnable

Offset 0x04F7 - Enable SMBus ARP support Enable SMBus ARP support.

$EN_DIS

Definition at line 1143 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SmbusEnable

Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller.

$EN_DIS

Definition at line 181 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SpdProfileSelected

Offset 0x0177 - SPD Profile Selected Select DIMM timing profile.

Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2

Definition at line 272 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TjMaxOffset

Offset 0x051C - TjMax Offset TjMax offset.

Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Valid Range 0 - 63

Definition at line 1284 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::tRTP

Offset 0x0189 - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15.

DDR4 legal values: 5, 6, 7, 8, 9, 10, 12

Definition at line 345 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::TsegSize

Offset 0x009C - Tseg Size Size of SMRAM memory reserved.

0x400000 for Release build and 0x1000000 for Debug build 0x0400000:4MB, 0x01000000:16MB

Definition at line 159 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TvbRatioClipping

Offset 0x0301 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled.

This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature 0: Disabled, 1: Enabled

Definition at line 915 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TvbVoltageOptimization

Offset 0x0302 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default).

This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature. 0: Disabled, 1: Enabled

Definition at line 922 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Txt

Offset 0x02E7 - Txt Enable/Disable.

0: Disable, Enable/Disable Txt feature, 1: enable $EN_DIS

Definition at line 876 of file FspmUpd.h.

UINT64 FSP_M_CONFIG::TxtDprMemoryBase

Offset 0x02F0 - TxtDprMemoryBase Enable/Disable.

0: Disable, define default value of TxtDprMemoryBase , 1: enable

Definition at line 891 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::TxtDprMemorySize

Offset 0x02F8 - TxtDprMemorySize Enable/Disable.

0: Disable, define default value of TxtDprMemorySize , 1: enable

Definition at line 896 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::TxtHeapMemorySize

Offset 0x02FC - TxtHeapMemorySize Enable/Disable.

0: Disable, define default value of TxtHeapMemorySize , 1: enable

Definition at line 901 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TxtImplemented

Offset 0x02B5 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first.

Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization $EN_DIS

Definition at line 643 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::VddVoltage

Offset 0x0178 - Memory Voltage Memory Voltage Override (Vddq).

Default = no override 0:Default, 1100:1.10 Volts, 1150:1.15 Volts, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts

Definition at line 280 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::VmxEnable

Offset 0x02DA - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 816 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_M_CONFIG Member List

This is the complete list of members for FSP_M_CONFIG, including all inherited members.

ActiveCoreCount | FSP_M_CONFIG
ApertureSize | FSP_M_CONFIG
Avx2RatioOffset | FSP_M_CONFIG
Avx3RatioOffset | FSP_M_CONFIG
BclkAdaptiveVoltage | FSP_M_CONFIG
BiosGuard | FSP_M_CONFIG
BistOnReset | FSP_M_CONFIG
BootFrequency | FSP_M_CONFIG
CaVrefConfig | FSP_M_CONFIG
CleanMemory | FSP_M_CONFIG
CmdTriStateDis | FSP_M_CONFIG
CoreMaxOcRatio | FSP_M_CONFIG
CorePllVoltageOffset | FSP_M_CONFIG
CoreVoltageAdaptive | FSP_M_CONFIG
CoreVoltageMode | FSP_M_CONFIG
CoreVoltageOffset | FSP_M_CONFIG
CoreVoltageOverride | FSP_M_CONFIG
CpuRatio | FSP_M_CONFIG
CpuRatioOverride | FSP_M_CONFIG
DdrFreqLimit | FSP_M_CONFIG
DllBwEn0 | FSP_M_CONFIG
DllBwEn1 | FSP_M_CONFIG
DllBwEn2 | FSP_M_CONFIG
DllBwEn3 | FSP_M_CONFIG
DmiDeEmphasis | FSP_M_CONFIG
DmiGen3EndPointHint | FSP_M_CONFIG
DmiGen3EndPointPreset | FSP_M_CONFIG
DmiGen3ProgramStaticEq | FSP_M_CONFIG
DmiGen3RootPortPreset | FSP_M_CONFIG
DmiGen3RxCtlePeaking | FSP_M_CONFIG
DqByteMapCh0 | FSP_M_CONFIG
DqByteMapCh1 | FSP_M_CONFIG
DqPinsInterleaved | FSP_M_CONFIG
DqsMapCpu2DramCh0 | FSP_M_CONFIG
DqsMapCpu2DramCh1 | FSP_M_CONFIG
EdramRatio | FSP_M_CONFIG
EnableC6Dram | FSP_M_CONFIG
EnableSgx | FSP_M_CONFIG
EnableTraceHub | FSP_M_CONFIG
EvLoader | FSP_M_CONFIG
FClkFrequency | FSP_M_CONFIG
FlashWearOutProtection | FSP_M_CONFIG
GtPllVoltageOffset | FSP_M_CONFIG
GtsExtraTurboVoltage | FSP_M_CONFIG
GtsMaxOcRatio | FSP_M_CONFIG
GtsVoltageMode | FSP_M_CONFIG
GtsVoltageOffset | FSP_M_CONFIG
GtsVoltageOverride | FSP_M_CONFIG
GttMmAdr | FSP_M_CONFIG
GttSize | FSP_M_CONFIG
GtusExtraTurboVoltage | FSP_M_CONFIG
GtusMaxOcRatio | FSP_M_CONFIG
GtusVoltageMode | FSP_M_CONFIG
GtusVoltageOffset | FSP_M_CONFIG
GtusVoltageOverride | FSP_M_CONFIG
Heci1BarAddress | FSP_M_CONFIG
Heci2BarAddress | FSP_M_CONFIG
Heci3BarAddress | FSP_M_CONFIG
HeciTimeouts | FSP_M_CONFIG
HyperThreading | FSP_M_CONFIG
IedSize | FSP_M_CONFIG
IgdDvmt50PreAlloc | FSP_M_CONFIG
InitPcieAspmAfterOprom | FSP_M_CONFIG
InternalGfx | FSP_M_CONFIG
JtagC10PowerGateDisable | FSP_M_CONFIG
McPllVoltageOffset | FSP_M_CONFIG
MemorySpdDataLen | FSP_M_CONFIG
MemorySpdPtr00 | FSP_M_CONFIG
MemorySpdPtr01 | FSP_M_CONFIG
MemorySpdPtr10 | FSP_M_CONFIG
MemorySpdPtr11 | FSP_M_CONFIG
MmaTestConfigPtr | FSP_M_CONFIG
MmaTestConfigSize | FSP_M_CONFIG
MmaTestContentPtr | FSP_M_CONFIG
MmaTestContentSize | FSP_M_CONFIG
MmioSize | FSP_M_CONFIG
MmioSizeAdjustment | FSP_M_CONFIG
MrcFastBoot | FSP_M_CONFIG
NModeSupport | FSP_M_CONFIG
OcLock | FSP_M_CONFIG
OcSupport | FSP_M_CONFIG
OddRatioMode | FSP_M_CONFIG
PcdDebugInterfaceFlags | FSP_M_CONFIG
PcdIsaSerialUartBase | FSP_M_CONFIG
PcdSerialDebugBaudRate | FSP_M_CONFIG
PcdSerialDebugLevel | FSP_M_CONFIG
PcdSerialIoUartNumber | FSP_M_CONFIG
PchAcpiBase | FSP_M_CONFIG
PchHpetBase | FSP_M_CONFIG
PchHpetBdfValid | FSP_M_CONFIG
PchHpetBusNumber | FSP_M_CONFIG
PchHpetDeviceNumber | FSP_M_CONFIG
PchHpetEnable | FSP_M_CONFIG
PchHpetFunctionNumber | FSP_M_CONFIG
PchLpcEnhancePort8xhDecoding | FSP_M_CONFIG
PchNumRsvdSmbusAddresses | FSP_M_CONFIG
PchPcieHsioRxSetCtle | FSP_M_CONFIG
PchPcieHsioRxSetCtleEnable | FSP_M_CONFIG
PchPcieHsioTxGen1DeEmph | FSP_M_CONFIG
PchPcieHsioTxGen1DeEmphEnable | FSP_M_CONFIG
PchPcieHsioTxGen1DownscaleAmp | FSP_M_CONFIG
PchPcieHsioTxGen1DownscaleAmpEnable | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph3p5 | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph3p5Enable | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph6p0 | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph6p0Enable | FSP_M_CONFIG
PchPcieHsioTxGen2DownscaleAmp | FSP_M_CONFIG
PchPcieHsioTxGen2DownscaleAmpEnable | FSP_M_CONFIG
PchPcieHsioTxGen3DownscaleAmp | FSP_M_CONFIG
PchPcieHsioTxGen3DownscaleAmpEnable | FSP_M_CONFIG
PchPmPciePllSsc | FSP_M_CONFIG
PchPort80Route | FSP_M_CONFIG
PchSataHsioRxGen1EqBoostMag | FSP_M_CONFIG
PchSataHsioRxGen1EqBoostMagEnable | FSP_M_CONFIG
PchSataHsioRxGen2EqBoostMag | FSP_M_CONFIG
PchSataHsioRxGen2EqBoostMagEnable | FSP_M_CONFIG
PchSataHsioRxGen3EqBoostMag | FSP_M_CONFIG
PchSataHsioRxGen3EqBoostMagEnable | FSP_M_CONFIG
PchSataHsioTxGen1DeEmph | FSP_M_CONFIG
PchSataHsioTxGen1DeEmphEnable | FSP_M_CONFIG
PchSataHsioTxGen1DownscaleAmp | FSP_M_CONFIG
PchSataHsioTxGen1DownscaleAmpEnable | FSP_M_CONFIG
PchSataHsioTxGen2DeEmph | FSP_M_CONFIG
PchSataHsioTxGen2DeEmphEnable | FSP_M_CONFIG
PchSataHsioTxGen2DownscaleAmp | FSP_M_CONFIG
PchSataHsioTxGen2DownscaleAmpEnable | FSP_M_CONFIG
PchSataHsioTxGen3DeEmph | FSP_M_CONFIG
PchSataHsioTxGen3DeEmphEnable | FSP_M_CONFIG
PchSataHsioTxGen3DownscaleAmp | FSP_M_CONFIG
PchSataHsioTxGen3DownscaleAmpEnable | FSP_M_CONFIG
PchSmbusIoBase | FSP_M_CONFIG
PcieRpEnableMask | FSP_M_CONFIG
PeciC10Reset | FSP_M_CONFIG
PeciSxReset | FSP_M_CONFIG
Peg0Enable | FSP_M_CONFIG
Peg0MaxLinkSpeed | FSP_M_CONFIG
Peg0MaxLinkWidth | FSP_M_CONFIG
Peg0PowerDownUnusedLanes | FSP_M_CONFIG
Peg1Enable | FSP_M_CONFIG
Peg1MaxLinkSpeed | FSP_M_CONFIG
Peg1MaxLinkWidth | FSP_M_CONFIG
Peg1PowerDownUnusedLanes | FSP_M_CONFIG
Peg2Enable | FSP_M_CONFIG
Peg2MaxLinkSpeed | FSP_M_CONFIG
Peg2MaxLinkWidth | FSP_M_CONFIG
Peg2PowerDownUnusedLanes | FSP_M_CONFIG
PegDataPtr | FSP_M_CONFIG
PegDisableSpreadSpectrumClocking | FSP_M_CONFIG
PegGen3RxCtlePeaking | FSP_M_CONFIG
PegGpioData | FSP_M_CONFIG
PegRootPortHPE | FSP_M_CONFIG
PlatformMemorySize | FSP_M_CONFIG
PrimaryDisplay | FSP_M_CONFIG
PrmrrSize | FSP_M_CONFIG
ProbelessTrace | FSP_M_CONFIG
Ratio | FSP_M_CONFIG
RcompResistor | FSP_M_CONFIG
RcompTarget | FSP_M_CONFIG
RealtimeMemoryTiming | FSP_M_CONFIG
RefClk | FSP_M_CONFIG
ReservedFspmUpd | FSP_M_CONFIG
ReservedSecurityPreMem | FSP_M_CONFIG
RingDownBin | FSP_M_CONFIG
RingMaxOcRatio | FSP_M_CONFIG
RingMinOcRatio | FSP_M_CONFIG
RingPllVoltageOffset | FSP_M_CONFIG
RMT | FSP_M_CONFIG
RootPortDev | FSP_M_CONFIG
RootPortFun | FSP_M_CONFIG
RsvdSmbusAddressTablePtr | FSP_M_CONFIG
SaGv | FSP_M_CONFIG
SaOcSupport | FSP_M_CONFIG
SaPllVoltageOffset | FSP_M_CONFIG
SaRtd3Pcie0Gpio | FSP_M_CONFIG
SaRtd3Pcie1Gpio | FSP_M_CONFIG
SaRtd3Pcie2Gpio | FSP_M_CONFIG
SaVoltageOffset | FSP_M_CONFIG
SgDelayAfterHoldReset | FSP_M_CONFIG
SgDelayAfterPwrEn | FSP_M_CONFIG
SinitMemorySize | FSP_M_CONFIG
SkipStopPbet | FSP_M_CONFIG
SmbusArpEnable | FSP_M_CONFIG
SmbusEnable | FSP_M_CONFIG
SmramMask | FSP_M_CONFIG
SpdProfileSelected | FSP_M_CONFIG
tCL | FSP_M_CONFIG
tCWL | FSP_M_CONFIG
tFAW | FSP_M_CONFIG
TjMaxOffset | FSP_M_CONFIG
TraceHubMemReg0Size | FSP_M_CONFIG
TraceHubMemReg1Size | FSP_M_CONFIG
tRAS | FSP_M_CONFIG
tRCDtRP | FSP_M_CONFIG
tREFI | FSP_M_CONFIG
tRFC | FSP_M_CONFIG
tRRD | FSP_M_CONFIG
tRTP | FSP_M_CONFIG
TsegSize | FSP_M_CONFIG
TvbRatioClipping | FSP_M_CONFIG
TvbVoltageOptimization | FSP_M_CONFIG
tWR | FSP_M_CONFIG
tWTR | FSP_M_CONFIG
Txt | FSP_M_CONFIG
TxtDprMemoryBase | FSP_M_CONFIG
TxtDprMemorySize | FSP_M_CONFIG
TxtHeapMemorySize | FSP_M_CONFIG
TxtImplemented | FSP_M_CONFIG
UnusedUpdSpace0 | FSP_M_CONFIG
UnusedUpdSpace1 | FSP_M_CONFIG
UnusedUpdSpace2 | FSP_M_CONFIG
UnusedUpdSpace3 | FSP_M_CONFIG
UnusedUpdSpace4 | FSP_M_CONFIG
UnusedUpdSpace5 | FSP_M_CONFIG
UnusedUpdSpace6 | FSP_M_CONFIG
UnusedUpdSpace7 | FSP_M_CONFIG
UnusedUpdSpace8 | FSP_M_CONFIG
UserBd | FSP_M_CONFIG
VddVoltage | FSP_M_CONFIG
VmxEnable | FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_M_TEST_CONFIG Struct Reference

Public Attributes | List of all members
FSP_M_TEST_CONFIG Struct Reference

Fsp M Test Configuration. More...

#include <FspmUpd.h>

Public Attributes

UINT32 | Signature
Offset 0x0520.
UINT8 | SkipExtGfxScan
Offset 0x0524 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS.
UINT8 | BdatEnable
Offset 0x0525 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. More...
UINT8 | ScanExtGfxForLegacyOpRom
Offset 0x0526 - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). More...
UINT8 | LockPTMregs
Offset 0x0527 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. More...
UINT8 | DmiVc1
Offset 0x0528 - Enable/Disable DmiVc1 Enable/Disable DmiVc1. More...
UINT8 | DmiVcm
Offset 0x0529 - Enable/Disable DmiVcm Enable/Disable DmiVcm. More...
UINT8 | DmiMaxLinkSpeed
Offset 0x052A - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | DmiGen3EqPh2Enable
Offset 0x052B - DMI Equalization Phase 2 DMI Equalization Phase 2. More...
UINT8 | DmiGen3EqPh3Method
Offset 0x052C - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3. More...
UINT8 | Peg0Gen3EqPh2Enable
Offset 0x052D - Phase2 EQ enable on the PEG 0:1:0. More...
UINT8 | Peg1Gen3EqPh2Enable
Offset 0x052E - Phase2 EQ enable on the PEG 0:1:1. More...
UINT8 | Peg2Gen3EqPh2Enable
Offset 0x052F - Phase2 EQ enable on the PEG 0:1:2. More...
UINT8 | Peg0Gen3EqPh3Method
Offset 0x0530 - Phase3 EQ method on the PEG 0:1:0. More...
UINT8 | Peg1Gen3EqPh3Method
Offset 0x0531 - Phase3 EQ method on the PEG 0:1:1. More...
UINT8 | Peg2Gen3EqPh3Method
Offset 0x0532 - Phase3 EQ method on the PEG 0:1:2. More...
UINT8 | PegGen3ProgramStaticEq
Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets. More...
UINT8 | Gen3SwEqAlwaysAttempt
Offset 0x0534 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot. More...
UINT8 | Gen3SwEqNumberOfPresets
Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq. More...
UINT8 | Gen3SwEqEnableVocTest
Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. More...
UINT8 | PegRxCemTestingMode
Offset 0x0537 - PPCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing $EN_DIS.
UINT8 | PegRxCemLoopbackLane
Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback. More...
UINT8 | PegGenerateBdatMarginTable
Offset 0x0539 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. More...
UINT8 | UnusedUpdSpace9 [6]
Offset 0x053A.
UINT8 | PegRxCemNonProtocolAwareness
Offset 0x0540 - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. More...
UINT8 | PegGen3RxCtleOverride
Offset 0x0541 - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified $EN_DIS.
UINT8 | PegGen3Rsvd
Offset 0x0542 - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified $EN_DIS.
UINT8 | PanelPowerEnable
Offset 0x0543 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). More...
UINT8 | PegGen3RootPortPreset [16]
Offset 0x0544 - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane. More...
UINT8 | PegGen3EndPointPreset [16]
Offset 0x0554 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane. More...
UINT8 | PegGen3EndPointHint [16]
Offset 0x0564 - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane. More...
UINT16 | Gen3SwEqJitterDwellTime
Offset 0x0574 - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. More...
UINT16 | Gen3SwEqJitterErrorTarget
Offset 0x0576 - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1. More...
UINT16 | Gen3SwEqVocDwellTime
Offset 0x0578 - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000. More...
UINT16 | Gen3SwEqVocErrorTarget
Offset 0x057A - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2. More...
UINT8 | SaPreMemTestRsvd [4]
Offset 0x057C - SaPreMemTestRsvd Reserved for SA Pre-Mem Test $EN_DIS.
UINT64 | BiosAcmBase
Offset 0x0580 - BiosAcmBase Enable/Disable. More...
UINT32 | BiosAcmSize
Offset 0x0588 - BiosAcmSize Enable/Disable. More...
UINT32 | TgaSize
Offset 0x058C - TgaSize Enable/Disable. More...
UINT64 | TxtLcpPdBase
Offset 0x0590 - TxtLcpPdBase Enable/Disable. More...
UINT64 | TxtLcpPdSize
Offset 0x0598 - TxtLcpPdSize Enable/Disable. More...
UINT16 | TotalFlashSize
Offset 0x05A0 - TotalFlashSize Enable/Disable. More...
UINT16 | BiosSize
Offset 0x05A2 - BiosSize Enable/Disable. More...
UINT8 | PchDciEn
Offset 0x05A4 - PCH Dci Enable Enable/disable PCH Dci. More...
UINT8 | PchDciAutoDetect
Offset 0x05A5 - PCH Dci Auto Detect Deprecated $EN_DIS.
UINT8 | SmbusDynamicPowerGating
Offset 0x05A6 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. More...
UINT8 | WdtDisableAndLock
Offset 0x05A7 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. More...
UINT8 | SmbusSpdWriteDisable
Offset 0x05A8 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. More...
UINT8 | ChipsetInitMessage
Offset 0x05A9 - ChipsetInit HECI message Enable/Disable. More...
UINT8 | BypassPhySyncReset
Offset 0x05AA - Bypass ChipsetInit sync reset. More...
UINT8 | DidInitStat
Offset 0x05AB - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4: Memory not preserved across reset, Set ME DID init stat value $EN_DIS.
UINT8 | DisableCpuReplacedPolling
Offset 0x05AC - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS.
UINT8 | SendDidMsg
Offset 0x05AD - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent) $EN_DIS.
UINT8 | DisableHeciRetry
Offset 0x05AE - Retry mechanism for HECI APIs Test, 0: disable, 1: enable, Enable/Disable HECI retry. More...
UINT8 | DisableMessageCheck
Offset 0x05AF - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. More...
UINT8 | SkipMbpHob
Offset 0x05B0 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. More...
UINT8 | HeciCommunication2
Offset 0x05B1 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. More...
UINT8 | KtDeviceEnable
Offset 0x05B2 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device. More...
UINT8 | IderDeviceEnable
Offset 0x05B3 - Enable IDEr Test, 0: disable, 1: enable, Enable or Disable IDEr. More...
UINT8 | ReservedFspmTestUpd [12]
Offset 0x05B4.

Detailed Description

Fsp M Test Configuration.

Definition at line 1293 of file FspmUpd.h.

Member Data Documentation

UINT8 FSP_M_TEST_CONFIG::BdatEnable

Offset 0x0525 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data.

Disable (Default): Do not generate it $EN_DIS

Definition at line 1310 of file FspmUpd.h.

UINT64 FSP_M_TEST_CONFIG::BiosAcmBase

Offset 0x0580 - BiosAcmBase Enable/Disable.

0: Disable, define default value of BiosAcmBase , 1: enable

Definition at line 1546 of file FspmUpd.h.

UINT32 FSP_M_TEST_CONFIG::BiosAcmSize

Offset 0x0588 - BiosAcmSize Enable/Disable.

0: Disable, define default value of BiosAcmSize , 1: enable

Definition at line 1551 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::BiosSize

Offset 0x05A2 - BiosSize Enable/Disable.

0: Disable, define default value of BiosSize , 1: enable

Definition at line 1576 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::BypassPhySyncReset

Offset 0x05AA - Bypass ChipsetInit sync reset.

0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message. $EN_DIS

Definition at line 1620 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::ChipsetInitMessage

Offset 0x05A9 - ChipsetInit HECI message Enable/Disable.

0: Disable, 1: enable, Enable or disable ChipsetInit HECI message. If disabled, it prevents from sending ChipsetInit HECI message. $EN_DIS

Definition at line 1614 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DisableHeciRetry

Offset 0x05AE - Retry mechanism for HECI APIs Test, 0: disable, 1: enable, Enable/Disable HECI retry.

$EN_DIS

Definition at line 1646 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DisableMessageCheck

Offset 0x05AF - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check.

$EN_DIS

Definition at line 1652 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DmiGen3EqPh2Enable

Offset 0x052B - DMI Equalization Phase 2 DMI Equalization Phase 2.

(0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method 0:Disable phase2, 1:Enable phase2, 2:Auto

Definition at line 1349 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DmiGen3EqPh3Method

Offset 0x052C - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3.

Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 1359 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DmiVc1

Offset 0x0528 - Enable/Disable DmiVc1 Enable/Disable DmiVc1.

Enable = 1, Disable (Default) = 0 $EN_DIS

Definition at line 1329 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DmiVcm

Offset 0x0529 - Enable/Disable DmiVcm Enable/Disable DmiVcm.

Enable (Default) = 1, Disable = 0 $EN_DIS

Definition at line 1335 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Gen3SwEqAlwaysAttempt

Offset 0x0534 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot.

Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended 0:Disable, 1:Enable

Definition at line 1425 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Gen3SwEqEnableVocTest

Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm.

Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default 0:Disable, 1:Enable, 2:Auto

Definition at line 1443 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqJitterDwellTime

Offset 0x0574 - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000.

Warning
Do not change from the default

Definition at line 1520 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqJitterErrorTarget

Offset 0x0576 - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1.

Warning
Do not change from the default

Definition at line 1525 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Gen3SwEqNumberOfPresets

Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq.

P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings 0:P7 P3 P5, 1:P0 to P9, 2:Auto

Definition at line 1435 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqVocDwellTime

Offset 0x0578 - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000.

Warning
Do not change from the default

Definition at line 1530 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqVocErrorTarget

Offset 0x057A - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2.

Warning
Do not change from the default

Definition at line 1535 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::HeciCommunication2

Offset 0x05B1 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.

$EN_DIS

Definition at line 1664 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::IderDeviceEnable

Offset 0x05B3 - Enable IDEr Test, 0: disable, 1: enable, Enable or Disable IDEr.

$EN_DIS

Definition at line 1676 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::KtDeviceEnable

Offset 0x05B2 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device.

$EN_DIS

Definition at line 1670 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::LockPTMregs

Offset 0x0527 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers.

Enable(Default)=1, Disable=0 $EN_DIS

Definition at line 1323 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PanelPowerEnable

Offset 0x0543 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel).

0=Disable, 1(Default)=Enable $EN_DIS

Definition at line 1500 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PchDciEn

Offset 0x05A4 - PCH Dci Enable Enable/disable PCH Dci.

$EN_DIS

Definition at line 1582 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg0Gen3EqPh2Enable

Offset 0x052D - Phase2 EQ enable on the PEG 0:1:0.

Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto

Definition at line 1366 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg0Gen3EqPh3Method

Offset 0x0530 - Phase3 EQ method on the PEG 0:1:0.

PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 1390 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg1Gen3EqPh2Enable

Offset 0x052E - Phase2 EQ enable on the PEG 0:1:1.

Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto

Definition at line 1373 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg1Gen3EqPh3Method

Offset 0x0531 - Phase3 EQ method on the PEG 0:1:1.

PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 1400 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg2Gen3EqPh2Enable

Offset 0x052F - Phase2 EQ enable on the PEG 0:1:2.

Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto

Definition at line 1380 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg2Gen3EqPh3Method

Offset 0x0532 - Phase3 EQ method on the PEG 0:1:2.

PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 1410 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3EndPointHint[16]

Offset 0x0564 - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane.

Range: 0-6, 2 is default for each lane

Definition at line 1515 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3EndPointPreset[16]

Offset 0x0554 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane.

Range: 0-9, 7 is default for each lane

Definition at line 1510 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3ProgramStaticEq

Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets.

Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS

Definition at line 1417 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3RootPortPreset[16]

Offset 0x0544 - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane.

Range: 0-9, 8 is default for each lane

Definition at line 1505 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGenerateBdatMarginTable

Offset 0x0539 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table.

Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data $EN_DIS

Definition at line 1464 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegRxCemLoopbackLane

Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback.

Default is Lane 0

Definition at line 1456 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegRxCemNonProtocolAwareness

Offset 0x0540 - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table.

Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing $EN_DIS

Definition at line 1477 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::ScanExtGfxForLegacyOpRom

Offset 0x0526 - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable).

Enable(Default)=1, Disable=0 $EN_DIS

Definition at line 1317 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::SkipMbpHob

Offset 0x05B0 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB.

$EN_DIS

Definition at line 1658 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::SmbusDynamicPowerGating

Offset 0x05A6 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating.

$EN_DIS

Definition at line 1594 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::SmbusSpdWriteDisable

Offset 0x05A8 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable.

0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS

Definition at line 1607 of file FspmUpd.h.

UINT32 FSP_M_TEST_CONFIG::TgaSize

Offset 0x058C - TgaSize Enable/Disable.

0: Disable, define default value of TgaSize , 1: enable

Definition at line 1556 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::TotalFlashSize

Offset 0x05A0 - TotalFlashSize Enable/Disable.

0: Disable, define default value of TotalFlashSize , 1: enable

Definition at line 1571 of file FspmUpd.h.

UINT64 FSP_M_TEST_CONFIG::TxtLcpPdBase

Offset 0x0590 - TxtLcpPdBase Enable/Disable.

0: Disable, define default value of TxtLcpPdBase , 1: enable

Definition at line 1561 of file FspmUpd.h.

UINT64 FSP_M_TEST_CONFIG::TxtLcpPdSize

Offset 0x0598 - TxtLcpPdSize Enable/Disable.

0: Disable, define default value of TxtLcpPdSize , 1: enable

Definition at line 1566 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::WdtDisableAndLock

Offset 0x05A7 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers.

$EN_DIS

Definition at line 1600 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_M_TEST_CONFIG Member List

This is the complete list of members for FSP_M_TEST_CONFIG, including all inherited members.

BdatEnable | FSP_M_TEST_CONFIG
BiosAcmBase | FSP_M_TEST_CONFIG
BiosAcmSize | FSP_M_TEST_CONFIG
BiosSize | FSP_M_TEST_CONFIG
BypassPhySyncReset | FSP_M_TEST_CONFIG
ChipsetInitMessage | FSP_M_TEST_CONFIG
DidInitStat | FSP_M_TEST_CONFIG
DisableCpuReplacedPolling | FSP_M_TEST_CONFIG
DisableHeciRetry | FSP_M_TEST_CONFIG
DisableMessageCheck | FSP_M_TEST_CONFIG
DmiGen3EqPh2Enable | FSP_M_TEST_CONFIG
DmiGen3EqPh3Method | FSP_M_TEST_CONFIG
DmiMaxLinkSpeed | FSP_M_TEST_CONFIG
DmiVc1 | FSP_M_TEST_CONFIG
DmiVcm | FSP_M_TEST_CONFIG
Gen3SwEqAlwaysAttempt | FSP_M_TEST_CONFIG
Gen3SwEqEnableVocTest | FSP_M_TEST_CONFIG
Gen3SwEqJitterDwellTime | FSP_M_TEST_CONFIG
Gen3SwEqJitterErrorTarget | FSP_M_TEST_CONFIG
Gen3SwEqNumberOfPresets | FSP_M_TEST_CONFIG
Gen3SwEqVocDwellTime | FSP_M_TEST_CONFIG
Gen3SwEqVocErrorTarget | FSP_M_TEST_CONFIG
HeciCommunication2 | FSP_M_TEST_CONFIG
IderDeviceEnable | FSP_M_TEST_CONFIG
KtDeviceEnable | FSP_M_TEST_CONFIG
LockPTMregs | FSP_M_TEST_CONFIG
PanelPowerEnable | FSP_M_TEST_CONFIG
PchDciAutoDetect | FSP_M_TEST_CONFIG
PchDciEn | FSP_M_TEST_CONFIG
Peg0Gen3EqPh2Enable | FSP_M_TEST_CONFIG
Peg0Gen3EqPh3Method | FSP_M_TEST_CONFIG
Peg1Gen3EqPh2Enable | FSP_M_TEST_CONFIG
Peg1Gen3EqPh3Method | FSP_M_TEST_CONFIG
Peg2Gen3EqPh2Enable | FSP_M_TEST_CONFIG
Peg2Gen3EqPh3Method | FSP_M_TEST_CONFIG
PegGen3EndPointHint | FSP_M_TEST_CONFIG
PegGen3EndPointPreset | FSP_M_TEST_CONFIG
PegGen3ProgramStaticEq | FSP_M_TEST_CONFIG
PegGen3RootPortPreset | FSP_M_TEST_CONFIG
PegGen3Rsvd | FSP_M_TEST_CONFIG
PegGen3RxCtleOverride | FSP_M_TEST_CONFIG
PegGenerateBdatMarginTable | FSP_M_TEST_CONFIG
PegRxCemLoopbackLane | FSP_M_TEST_CONFIG
PegRxCemNonProtocolAwareness | FSP_M_TEST_CONFIG
PegRxCemTestingMode | FSP_M_TEST_CONFIG
ReservedFspmTestUpd | FSP_M_TEST_CONFIG
SaPreMemTestRsvd | FSP_M_TEST_CONFIG
ScanExtGfxForLegacyOpRom | FSP_M_TEST_CONFIG
SendDidMsg | FSP_M_TEST_CONFIG
Signature | FSP_M_TEST_CONFIG
SkipExtGfxScan | FSP_M_TEST_CONFIG
SkipMbpHob | FSP_M_TEST_CONFIG
SmbusDynamicPowerGating | FSP_M_TEST_CONFIG
SmbusSpdWriteDisable | FSP_M_TEST_CONFIG
TgaSize | FSP_M_TEST_CONFIG
TotalFlashSize | FSP_M_TEST_CONFIG
TxtLcpPdBase | FSP_M_TEST_CONFIG
TxtLcpPdSize | FSP_M_TEST_CONFIG
UnusedUpdSpace9 | FSP_M_TEST_CONFIG
WdtDisableAndLock | FSP_M_TEST_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_S_CONFIG Struct Reference

Public Attributes | List of all members
FSP_S_CONFIG Struct Reference

Fsp S Configuration. More...

#include <FspsUpd.h>

Public Attributes

UINT32 | LogoPtr
Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
UINT32 | LogoSize
Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
UINT32 | GraphicsConfigPtr
Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
UINT8 | Device4Enable
Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
UINT8 | PchHdaEnable
Offset 0x002D - Enable Intel HD Audio (Azalia) Enable/disable Azalia controller. More...
UINT8 | PchHdaDspEnable
Offset 0x002E - Enable HD Audio DSP Enable/disable HD Audio DSP feature. More...
UINT8 | PchHdaIoBufferOwnership
Offset 0x002F - Select HDAudio IoBuffer Ownership Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. More...
UINT8 | PchCio2Enable
Offset 0x0030 - Enable CIO2 Controller Enable/disable SKYCAM CIO2 Controller. More...
UINT8 | ScsEmmcEnabled
Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller. More...
UINT8 | ScsEmmcHs400Enabled
Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. More...
UINT8 | ScsSdCardEnabled
Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller. More...
UINT8 | PchIshEnable
Offset 0x0034 - Enable PCH ISH Controller Enable/disable ISH Controller. More...
UINT8 | ShowSpiController
Offset 0x0035 - Show SPI controller Enable/disable to show SPI controller. More...
UINT8 | SpiFlashCfgLockDown
Offset 0x0036 - Flash Configuration Lock Down Enable/disable flash lock down. More...
UINT8 | UnusedUpdSpace0
Offset 0x0037.
UINT32 | MicrocodeRegionBase
Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
UINT32 | MicrocodeRegionSize
Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
UINT8 | TurboMode
Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode. More...
UINT8 | SataSalpSupport
Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. More...
UINT8 | SataPortsEnable [8]
Offset 0x0042 - Enable SATA ports Enable/disable SATA ports. More...
UINT8 | SataPortsDevSlp [8]
Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. More...
UINT8 | PortUsb20Enable [16]
Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports. More...
UINT8 | PortUsb30Enable [10]
Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports. More...
UINT8 | XdciEnable
Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller. More...
UINT8 | SsicPortEnable
Offset 0x006D - Enable XHCI SSIC Enable Enable/disable XHCI SSIC port. More...
UINT8 | UnusedUpdSpace1
Offset 0x006E.
UINT8 | NumOfDevIntConfig
Offset 0x006F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. More...
UINT32 | DevIntConfigPtr
Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. More...
UINT8 | SerialIoDevMode [11]
Offset 0x0074 - Enable SerialIo Device Mode 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. More...
UINT8 | PxRcConfig [8]
Offset 0x007F - PIRQx to IRQx Map Config PIRQx to IRQx mapping. More...
UINT8 | GpioIrqRoute
Offset 0x0087 - Select GPIO IRQ Route GPIO IRQ Select. More...
UINT8 | SciIrqSelect
Offset 0x0088 - Select SciIrqSelect SCI IRQ Select. More...
UINT8 | TcoIrqSelect
Offset 0x0089 - Select TcoIrqSelect TCO IRQ Select. More...
UINT8 | TcoIrqEnable
Offset 0x008A - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
UINT8 | PchHdaVerbTableEntryNum
Offset 0x008B - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
UINT32 | PchHdaVerbTablePtr
Offset 0x008C - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
UINT8 | UnusedUpdSpace2
Offset 0x0090.
UINT8 | SataEnable
Offset 0x0091 - Enable SATA Enable/disable SATA controller. More...
UINT8 | SataMode
Offset 0x0092 - SATA Mode Select SATA controller working mode. More...
UINT8 | Usb2AfePetxiset [16]
Offset 0x0093 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. More...
UINT8 | Usb2AfeTxiset [16]
Offset 0x00A3 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. More...
UINT8 | Usb2AfePredeemp [16]
Offset 0x00B3 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. More...
UINT8 | Usb2AfePehalfbit [16]
Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. More...
UINT8 | Usb3HsioTxDeEmphEnable [10]
Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. More...
UINT8 | Usb3HsioTxDeEmph [10]
Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). More...
UINT8 | Usb3HsioTxDownscaleAmpEnable [10]
Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. More...
UINT8 | Usb3HsioTxDownscaleAmp [10]
Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. More...
UINT8 | PchLanEnable
Offset 0x00FB - Enable LAN Enable/disable LAN controller. More...
UINT8 | DelayUsbPdoProgramming
Offset 0x00FC - Delay USB PDO Programming Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. More...
UINT8 | UnusedUpdSpace3 [23]
Offset 0x00FD.
UINT8 | PcieRpClkReqSupport [24]
Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. More...
UINT8 | PcieRpClkReqNumber [24]
Offset 0x012C - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported. More...
UINT8 | UnusedUpdSpace4 [5]
Offset 0x0144.
UINT8 | Heci3Enabled
Offset 0x0149 - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. More...
UINT8 | UnusedUpdSpace5 [9]
Offset 0x014A.
UINT8 | AmtEnabled
Offset 0x0153 - AMT Switch Enable/Disable. More...
UINT8 | WatchDog
Offset 0x0154 - WatchDog Timer Switch Enable/Disable. More...
UINT8 | AsfEnabled
Offset 0x0155 - ASF Switch Enable/Disable. More...
UINT8 | ManageabilityMode
Offset 0x0156 - Manageability Mode set by Mebx Enable/Disable. More...
UINT8 | FwProgress
Offset 0x0157 - PET Progress Enable/Disable. More...
UINT16 | WatchDogTimerOs
Offset 0x0158 - OS Timer 16 bits Value, Set OS watchdog timer. More...
UINT16 | WatchDogTimerBios
Offset 0x015A - BIOS Timer 16 bits Value, Set BIOS watchdog timer. More...
UINT8 | AmtSolEnabled
Offset 0x015C - SOL Switch Enable/Disable. More...
UINT8 | PcieRpClkSrcNumber [24]
Offset 0x015D - Configure CLKSRC Number Configure Root Port CLKSRC Number. More...
UINT8 | UnusedUpdSpace6 [139]
Offset 0x0175.
UINT16 | DefaultSvid
Offset 0x0200 - Subsystem Vendor ID for SA devices Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086.
UINT16 | DefaultSid
Offset 0x0202 - Subsystem Device ID for SA devices Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015.
UINT8 | CridEnable
Offset 0x0204 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS.
UINT8 | DmiAspm
Offset 0x0205 - DMI ASPM 0=Disable, 2(Default)=L1 0:Disable, 2:L1.
UINT16 | PegPhysicalSlotNumber [3]
Offset 0x0206 - PCIe Physical Slot Number per root port Physical Slot Number per root port.
UINT8 | PegDeEmphasis [3]
Offset 0x020C - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB 0:-6dB, 1:-3.5dB.
UINT8 | PegSlotPowerLimitValue [3]
Offset 0x020F - PCIe Slot Power Limit value per root port Slot power limit value per root port.
UINT8 | PegSlotPowerLimitScale [3]
Offset 0x0212 - PCIe Slot Power Limit scale per root port Slot power limit scale per root port 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x.
UINT8 | PavpEnable
Offset 0x0215 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS.
UINT8 | CdClock
Offset 0x0216 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz.
UINT8 | PeiGraphicsPeimInit
Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
UINT8 | SaImguEnable
Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM) Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM) $EN_DIS.
UINT8 | GmmEnable
Offset 0x0219 - Enable or disable GMM device 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | X2ApicOptOut
Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS.
UINT8 | UnusedUpdSpace7 [1]
Offset 0x021B.
UINT32 | VtdBaseAddress [2]
Offset 0x021C - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine.
UINT8 | UnusedUpdSpace8 [19]
Offset 0x0224.
UINT8 | SaPostMemProductionRsvd [16]
Offset 0x0237 - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS.
UINT8 | UnusedUpdSpace9 [7]
Offset 0x0247.
UINT8 | Psi3Enable [5]
Offset 0x024E - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. More...
UINT8 | Psi4Enable [5]
Offset 0x0253 - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | ImonSlope [5]
Offset 0x0258 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. More...
UINT8 | ImonOffset [5]
Offset 0x025D - Imon offset correction PCODE MMIO Mailbox: Imon offset correction. More...
UINT8 | VrConfigEnable [5]
Offset 0x0262 - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | TdcEnable [5]
Offset 0x0267 - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | TdcTimeWindow [5]
Offset 0x026C - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window. More...
UINT8 | TdcLock [5]
Offset 0x0271 - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | PsysSlope
Offset 0x0276 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. More...
UINT8 | PsysOffset
Offset 0x0277 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. More...
UINT8 | AcousticNoiseMitigation
Offset 0x0278 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. More...
UINT8 | FastPkgCRampDisableIa
Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SlowSlewRateForIa
Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SlowSlewRateForGt
Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SlowSlewRateForSa
Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | UnusedUpdSpace10 [9]
Offset 0x027D.
UINT16 | TdcPowerLimit [5]
Offset 0x0286 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. More...
UINT32 | VrPowerDeliveryDesign
Offset 0x0290 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. More...
UINT8 | UnusedUpdSpace11 [4]
Offset 0x0294.
UINT16 | AcLoadline [5]
Offset 0x0298 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. More...
UINT16 | DcLoadline [5]
Offset 0x02A2 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. More...
UINT16 | Psi1Threshold [5]
Offset 0x02AC - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. More...
UINT16 | Psi2Threshold [5]
Offset 0x02B6 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. More...
UINT16 | Psi3Threshold [5]
Offset 0x02C0 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. More...
UINT16 | IccMax [5]
Offset 0x02CA - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. More...
UINT16 | VrVoltageLimit [5]
Offset 0x02D4 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit. More...
UINT8 | UnusedUpdSpace12
Offset 0x02DE.
UINT8 | FastPkgCRampDisableGt
Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | FastPkgCRampDisableSa
Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | UnusedUpdSpace13
Offset 0x02E1.
UINT8 | SendVrMbxCmd
Offset 0x02E2 - Enable VR specific mailbox command VR specific mailbox commands. More...
UINT8 | SendVrMbxCmd1
Offset 0x02E3 - Select VR specific mailbox command to send VR specific mailbox commands. More...
UINT32 | CpuS3ResumeMtrrData
Offset 0x02E4 - CpuS3ResumeMtrrData Pointer to CPU S3 Resume MTRR Data.
CPU_CONFIG_FSP_DATA | CpuConfig
Offset 0x02E8 - Cpu Configuration Cpu Configuration data.
UINT64 | MicrocodePatchAddress
Offset 0x02F0 - MicrocodePatchAddress Pointer to microcode patch that is suitable for this processor. More...
UINT16 | CpuS3ResumeMtrrDataSize
Offset 0x02F8 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data.
UINT8 | UnusedUpdSpace14
Offset 0x02FA.
UINT8 | PchSkyCamPortATermOvrEnable
Offset 0x02FB - Enable SkyCam PortA Termination override Enable/disable PortA Termination override. More...
UINT8 | PchSkyCamPortBTermOvrEnable
Offset 0x02FC - Enable SkyCam PortB Termination override Enable/disable PortB Termination override. More...
UINT8 | PchSkyCamPortCTermOvrEnable
Offset 0x02FD - Enable SkyCam PortC Termination override Enable/disable PortC Termination override. More...
UINT8 | PchSkyCamPortDTermOvrEnable
Offset 0x02FE - Enable SkyCam PortD Termination override Enable/disable PortD Termination override. More...
UINT8 | PchSkyCamPortATrimEnable
Offset 0x02FF - Enable SkyCam PortA Clk Trim Enable/disable PortA Clk Trim. More...
UINT8 | PchSkyCamPortBTrimEnable
Offset 0x0300 - Enable SkyCam PortB Clk Trim Enable/disable PortB Clk Trim. More...
UINT8 | PchSkyCamPortCTrimEnable
Offset 0x0301 - Enable SkyCam PortC Clk Trim Enable/disable PortC Clk Trim. More...
UINT8 | PchSkyCamPortDTrimEnable
Offset 0x0302 - Enable SkyCam PortD Clk Trim Enable/disable PortD Clk Trim. More...
UINT8 | PchSkyCamPortACtleEnable
Offset 0x0303 - Enable SkyCam PortA Ctle Enable/disable PortA Ctle. More...
UINT8 | PchSkyCamPortBCtleEnable
Offset 0x0304 - Enable SkyCam PortB Ctle Enable/disable PortB Ctle. More...
UINT8 | PchSkyCamPortCDCtleEnable
Offset 0x0305 - Enable SkyCam PortCD Ctle Enable/disable PortCD Ctle. More...
UINT8 | PchSkyCamPortACtleCapValue
Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value Enable/disable PortA Ctle Cap Value.
UINT8 | PchSkyCamPortBCtleCapValue
Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value Enable/disable PortB Ctle Cap Value.
UINT8 | PchSkyCamPortCDCtleCapValue
Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value Enable/disable PortCD Ctle Cap Value.
UINT8 | PchSkyCamPortACtleResValue
Offset 0x0309 - Enable SkyCam PortA Ctle Res Value Enable/disable PortA Ctle Res Value.
UINT8 | PchSkyCamPortBCtleResValue
Offset 0x030A - Enable SkyCam PortB Ctle Res Value Enable/disable PortB Ctle Res Value.
UINT8 | PchSkyCamPortCDCtleResValue
Offset 0x030B - Enable SkyCam PortCD Ctle Res Value Enable/disable PortCD Ctle Res Value.
UINT8 | PchSkyCamPortAClkTrimValue
Offset 0x030C - Enable SkyCam PortA Clk Trim Value Enable/disable PortA Clk Trim Value.
UINT8 | PchSkyCamPortBClkTrimValue
Offset 0x030D - Enable SkyCam PortB Clk Trim Value Enable/disable PortB Clk Trim Value.
UINT8 | PchSkyCamPortCClkTrimValue
Offset 0x030E - Enable SkyCam PortC Clk Trim Value Enable/disable PortC Clk Trim Value.
UINT8 | PchSkyCamPortDClkTrimValue
Offset 0x030F - Enable SkyCam PortD Clk Trim Value Enable/disable PortD Clk Trim Value.
UINT16 | PchSkyCamPortADataTrimValue
Offset 0x0310 - Enable SkyCam Port A Data Trim Value Enable/disable Port A Data Trim Value.
UINT16 | PchSkyCamPortBDataTrimValue
Offset 0x0312 - Enable SkyCam Port B Data Trim Value Enable/disable Port B Data Trim Value.
UINT16 | PchSkyCamPortCDDataTrimValue
Offset 0x0314 - Enable SkyCam C/D Data Trim Value Enable/disable C/D Data Trim Value.
UINT8 | PchDmiAspm
Offset 0x0316 - Enable DMI ASPM ASPM on PCH side of the DMI Link. More...
UINT8 | PchPwrOptEnable
Offset 0x0317 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. More...
UINT8 | PchWriteProtectionEnable [5]
Offset 0x0318 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware.
UINT8 | PchReadProtectionEnable [5]
Offset 0x031D - PCH Flash Protection Ranges Read Enble Read is blocked by hardware.
UINT16 | PchProtectedRangeLimit [5]
Offset 0x0322 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison.
UINT16 | PchProtectedRangeBase [5]
Offset 0x032C - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
UINT8 | PchHdaPme
Offset 0x0336 - Enable Pme Enable Azalia wake-on-ring. More...
UINT8 | PchHdaIoBufferVoltage
Offset 0x0337 - IO Buffer Voltage I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V.
UINT8 | PchHdaVcType
Offset 0x0338 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1.
UINT8 | PchHdaLinkFrequency
Offset 0x0339 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz.
UINT8 | PchHdaIDispLinkFrequency
Offset 0x033A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
UINT8 | PchHdaIDispLinkTmode
Offset 0x033B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
UINT8 | PchHdaDspUaaCompliance
Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). More...
UINT8 | PchHdaIDispCodecDisconnect
Offset 0x033D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. More...
UINT8 | PchHdaDspEndpointDmic
Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum) 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array.
UINT8 | PchHdaDspEndpointBluetooth
Offset 0x033F - DSP Bluetooth enablement 0: Disable; 1: Enable. More...
UINT32 | PchHdaDspFeatureMask
Offset 0x0340 - Bitmask of supported DSP features [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6]. More...
UINT32 | PchHdaDspPpModuleMask
Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules Deprecated: Specific pre/post-processing module bit position must be coherent with the ACPI implementation: _SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support.
UINT8 | PchHdaDspEndpointI2s
Offset 0x0348 - DSP I2S enablement 0: Disable; 1: Enable. More...
UINT8 | PchIoApicBdfValid
Offset 0x0349 - Enable PCH Io Apic Set to 1 if BDF value is valid. More...
UINT8 | PchIoApicBusNumber
Offset 0x034A - PCH Io Apic Bus Number Bus/Device/Function used as Requestor / Completer ID. More...
UINT8 | PchIoApicDeviceNumber
Offset 0x034B - PCH Io Apic Device Number Bus/Device/Function used as Requestor / Completer ID. More...
UINT8 | PchIoApicFunctionNumber
Offset 0x034C - PCH Io Apic Function Number Bus/Device/Function used as Requestor / Completer ID. More...
UINT8 | PchIoApicEntry24_119
Offset 0x034D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. More...
UINT8 | PchIoApicId
Offset 0x034E - PCH Io Apic ID This member determines IOAPIC ID. More...
UINT8 | PchIoApicRangeSelect
Offset 0x034F - PCH Io Apic Range Select Define address bits 19:12 for the IOxAPIC range. More...
UINT8 | PchIshSpiGpioAssign
Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshUart0GpioAssign
Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshUart1GpioAssign
Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshI2c0GpioAssign
Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshI2c1GpioAssign
Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshI2c2GpioAssign
Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp0GpioAssign
Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp1GpioAssign
Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp2GpioAssign
Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp3GpioAssign
Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp4GpioAssign
Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp5GpioAssign
Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp6GpioAssign
Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp7GpioAssign
Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshPdtUnlock
Offset 0x035E - PCH ISH PDT Unlock Msg 0: False; 1: True. More...
UINT8 | PchLanLtrEnable
Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. More...
UINT8 | PchLanK1OffEnable
Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management 0: Disable; 1: Enable. More...
UINT8 | PchLanClkReqSupported
Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported 0: Disable; 1: Enable. More...
UINT8 | PchLanClkReqNumber
Offset 0x0362 - CLKREQ# used by GbE Valid if ClkReqSupported is TRUE.
UINT8 | PchLockDownBiosLock
Offset 0x0363 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. More...
UINT8 | PchLockDownSpiEiss
Offset 0x0364 - Enable LOCKDOWN SPI Eiss Enable InSMM.STS (EISS) in SPI. More...
UINT8 | PchCrid
Offset 0x0365 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. More...
UINT16 | PchSubSystemVendorId
Offset 0x0366 - PCH Sub system vendor ID Default Subsystem Vendor ID of the PCH devices. More...
UINT16 | PchSubSystemId
Offset 0x0368 - PCH Sub system ID Default Subsystem ID of the PCH devices. More...
UINT8 | PchLegacyIoLowLatency
Offset 0x036A - PCH Legacy IO Low Latency Enable todo $EN_DIS.
UINT8 | UnusedUpdSpace15 [5]
Offset 0x036B.
UINT8 | PcieRpHotPlug [24]
Offset 0x0370 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available.
UINT8 | PcieRpPmSci [24]
Offset 0x0388 - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled.
UINT8 | PcieRpExtSync [24]
Offset 0x03A0 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled.
UINT8 | PcieRpTransmitterHalfSwing [24]
Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled.
UINT8 | PcieRpClkReqDetect [24]
Offset 0x03D0 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management.
UINT8 | PcieRpAdvancedErrorReporting [24]
Offset 0x03E8 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled.
UINT8 | PcieRpUnsupportedRequestReport [24]
Offset 0x0400 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled.
UINT8 | PcieRpFatalErrorReport [24]
Offset 0x0418 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled.
UINT8 | PcieRpNoFatalErrorReport [24]
Offset 0x0430 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled.
UINT8 | PcieRpCorrectableErrorReport [24]
Offset 0x0448 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled.
UINT8 | PcieRpSystemErrorOnFatalError [24]
Offset 0x0460 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled.
UINT8 | PcieRpSystemErrorOnNonFatalError [24]
Offset 0x0478 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled.
UINT8 | PcieRpSystemErrorOnCorrectableError [24]
Offset 0x0490 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled.
UINT8 | PcieRpMaxPayload [24]
Offset 0x04A8 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
UINT8 | PcieRpDeviceResetPadActiveHigh [24]
Offset 0x04C0 - PCIE RP Device Reset Pad Active High Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad.
UINT8 | PcieRpPcieSpeed [24]
Offset 0x04D8 - PCIE RP Pcie Speed Determines each PCIE Port speed capability. More...
UINT8 | PcieRpGen3EqPh3Method [24]
Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). More...
UINT8 | PcieRpPhysicalSlotNumber [24]
Offset 0x0508 - PCIE RP Physical Slot Number Indicates the slot number for the root port. More...
UINT8 | PcieRpCompletionTimeout [24]
Offset 0x0520 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). More...
UINT32 | PcieRpDeviceResetPad [24]
Offset 0x0538 - PCIE RP Device Reset Pad The PCH pin assigned to device PERST# signal if available, zero otherwise. More...
UINT8 | PcieRpAspm [24]
Offset 0x0598 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). More...
UINT8 | PcieRpL1Substates [24]
Offset 0x05B0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). More...
UINT8 | PcieRpLtrEnable [24]
Offset 0x05C8 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism.
UINT8 | PcieRpLtrConfigLock [24]
Offset 0x05E0 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable.
UINT8 | PcieEqPh3LaneParamCm [24]
Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. More...
UINT8 | PcieEqPh3LaneParamCp [24]
Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. More...
UINT8 | PcieSwEqCoeffListCm [5]
Offset 0x0628 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. More...
UINT8 | PcieSwEqCoeffListCp [5]
Offset 0x062D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. More...
UINT8 | PcieDisableRootPortClockGating
Offset 0x0632 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. More...
UINT8 | PcieEnablePeerMemoryWrite
Offset 0x0633 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. More...
UINT8 | PcieAllowNoLtrIccPllShutdown
Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable or leaving untouched. More...
UINT8 | PcieComplianceTestMode
Offset 0x0635 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. More...
UINT16 | PcieDetectTimeoutMs
Offset 0x0636 - PCIE Rp Detect Timeout Ms Will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.
UINT8 | PcieRpFunctionSwap
Offset 0x0638 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
UINT8 | PchPmPmeB0S5Dis
Offset 0x0639 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. More...
UINT8 | PchPmSlpS0VmEnable
Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state. More...
UINT8 | UnusedUpdSpace16 [5]
Offset 0x063B.
UINT8 | PchPmWolEnableOverride
Offset 0x0640 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. More...
UINT8 | PchPmPcieWakeFromDeepSx
Offset 0x0641 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. More...
UINT8 | PchPmWoWlanEnable
Offset 0x0642 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
UINT8 | PchPmWoWlanDeepSxEnable
Offset 0x0643 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
UINT8 | PchPmLanWakeFromDeepSx
Offset 0x0644 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. More...
UINT8 | PchPmDeepSxPol
Offset 0x0645 - PCH Pm Deep Sx Pol Deep Sx Policy. More...
UINT8 | PchPmSlpS3MinAssert
Offset 0x0646 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. More...
UINT8 | PchPmSlpS4MinAssert
Offset 0x0647 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. More...
UINT8 | PchPmSlpSusMinAssert
Offset 0x0648 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. More...
UINT8 | PchPmSlpAMinAssert
Offset 0x0649 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. More...
UINT8 | UnusedUpdSpace17 [6]
Offset 0x064A.
UINT8 | PchPmLpcClockRun
Offset 0x0650 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
UINT8 | PchPmSlpStrchSusUp
Offset 0x0651 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. More...
UINT8 | PchPmSlpLanLowDc
Offset 0x0652 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. More...
UINT8 | PchPmPwrBtnOverridePeriod
Offset 0x0653 - PCH Pm Pwr Btn Override Period PCH power button override period. More...
UINT8 | PchPmDisableDsxAcPresentPulldown
Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
UINT8 | PchPmCapsuleResetType
Offset 0x0655 - PCH Pm Capsule Reset Type Deprecated: Determines type of reset issued during UpdateCapsule(). More...
UINT8 | PchPmDisableNativePowerButton
Offset 0x0656 - PCH Pm Disable Native Power Button Power button native mode disable. More...
UINT8 | PchPmSlpS0Enable
Offset 0x0657 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. More...
UINT8 | PchPmMeWakeSts
Offset 0x0658 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. More...
UINT8 | PchPmWolOvrWkSts
Offset 0x0659 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. More...
UINT8 | PchPmPwrCycDur
Offset 0x065A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. More...
UINT8 | UnusedUpdSpace18
Offset 0x065B.
UINT8 | PchPort61hEnable
Offset 0x065C - PCH Port 61h Config Enable/Disable Used for the emulation feature for Port61h read. More...
UINT8 | SataPwrOptEnable
Offset 0x065D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. More...
UINT8 | EsataSpeedLimit
Offset 0x065E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
UINT8 | SataSpeedLimit
Offset 0x065F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
UINT8 | SataPortsHotPlug [8]
Offset 0x0660 - Enable SATA Port HotPlug Enable SATA Port HotPlug.
UINT8 | SataPortsInterlockSw [8]
Offset 0x0668 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw.
UINT8 | SataPortsExternal [8]
Offset 0x0670 - Enable SATA Port External Enable SATA Port External.
UINT8 | SataPortsSpinUp [8]
Offset 0x0678 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device.
UINT8 | SataPortsSolidStateDrive [8]
Offset 0x0680 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD.
UINT8 | SataPortsEnableDitoConfig [8]
Offset 0x0688 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
UINT8 | SataPortsDmVal [8]
Offset 0x0690 - Enable SATA Port DmVal DITO multiplier. More...
UINT16 | SataPortsDitoVal [8]
Offset 0x0698 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625.
UINT8 | SataPortsZpOdd [8]
Offset 0x06A8 - Enable SATA Port ZpOdd Support zero power ODD.
UINT8 | SataRstRaidAlternateId
Offset 0x06B0 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. More...
UINT8 | SataRstRaid0
Offset 0x06B1 - PCH Sata Rst Raid0 RAID0. More...
UINT8 | SataRstRaid1
Offset 0x06B2 - PCH Sata Rst Raid1 RAID1. More...
UINT8 | SataRstRaid10
Offset 0x06B3 - PCH Sata Rst Raid10 RAID10. More...
UINT8 | SataRstRaid5
Offset 0x06B4 - PCH Sata Rst Raid5 RAID5. More...
UINT8 | SataRstIrrt
Offset 0x06B5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology. More...
UINT8 | SataRstOromUiBanner
Offset 0x06B6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. More...
UINT8 | SataRstOromUiDelay
Offset 0x06B7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
UINT8 | SataRstHddUnlock
Offset 0x06B8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. More...
UINT8 | SataRstLedLocate
Offset 0x06B9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. More...
UINT8 | SataRstIrrtOnly
Offset 0x06BA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. More...
UINT8 | SataRstSmartStorage
Offset 0x06BB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. More...
UINT8 | SataRstPcieEnable [3]
Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping.
UINT8 | SataRstPcieStoragePort [3]
Offset 0x06BF - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
UINT8 | SataRstPcieDeviceResetDelay [3]
Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. More...
UINT8 | PchScsEmmcHs400TuningRequired
Offset 0x06C5 - Enable eMMC HS400 Training Determine if HS400 Training is required. More...
UINT8 | PchScsEmmcHs400DllDataValid
Offset 0x06C6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. More...
UINT8 | PchScsEmmcHs400RxStrobeDll1
Offset 0x06C7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
UINT8 | PchScsEmmcHs400TxDataDll
Offset 0x06C8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
UINT8 | PchScsEmmcHs400DriverStrength
Offset 0x06C9 - I/O Driver Strength I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm.
UINT8 | SerialIoGpio
Offset 0x06CA - Enable Pch Serial IO GPIO Determines if enable Serial IO GPIO. More...
UINT8 | SerialIoI2cVoltage [6]
Offset 0x06CB - IO voltage for I2C controllers Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V.
UINT8 | SerialIoSpiCsPolarity [2]
Offset 0x06D1 - SPI ChipSelect signal polarity Selects SPI ChipSelect signal polarity.
UINT8 | SerialIoUartHwFlowCtrl [3]
Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS linesh.
UINT8 | SerialIoDebugUartNumber
Offset 0x06D6 - UART Number For Debug Purpose UART number for debug purpose. More...
UINT8 | SerialIoEnableDebugUartAfterPost
Offset 0x06D7 - Enable Debug UART Controller Enable debug UART controller after post.
UINT8 | PchSirqEnable
Offset 0x06D8 - Enable Serial IRQ Determines if enable Serial IRQ. More...
UINT8 | PchSirqMode
Offset 0x06D9 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. More...
UINT8 | PchStartFramePulse
Offset 0x06DA - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
UINT8 | PchThermalDeviceEnable
Offset 0x06DB - Enable Thermal Device Enable Thermal Device. More...
UINT16 | PchT0Level
Offset 0x06DC - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
UINT16 | PchT1Level
Offset 0x06DE - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
UINT16 | PchT2Level
Offset 0x06E0 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
UINT8 | PchTsmicLock
Offset 0x06E2 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. More...
UINT8 | PchTTEnable
Offset 0x06E3 - Enable The Thermal Throttle Enable the thermal throttle function. More...
UINT8 | PchTTState13Enable
Offset 0x06E4 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
UINT8 | PchTTLock
Offset 0x06E5 - Thermal Throttle Lock Thermal Throttle Lock. More...
UINT8 | TTSuggestedSetting
Offset 0x06E6 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. More...
UINT8 | TTCrossThrottling
Offset 0x06E7 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
UINT8 | PchDmiTsawEn
Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. More...
UINT8 | DmiSuggestedSetting
Offset 0x06E9 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. More...
UINT8 | DmiTS0TW
Offset 0x06EA - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width.
UINT8 | DmiTS1TW
Offset 0x06EB - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width.
UINT8 | DmiTS2TW
Offset 0x06EC - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width.
UINT8 | DmiTS3TW
Offset 0x06ED - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width.
UINT8 | SataP0T1M
Offset 0x06EE - Port 0 T1 Multipler Port 0 T1 Multipler.
UINT8 | SataP0T2M
Offset 0x06EF - Port 0 T2 Multipler Port 0 T2 Multipler.
UINT8 | SataP0T3M
Offset 0x06F0 - Port 0 T3 Multipler Port 0 T3 Multipler.
UINT8 | SataP0TDisp
Offset 0x06F1 - Port 0 Tdispatch Port 0 Tdispatch.
UINT8 | SataP1T1M
Offset 0x06F2 - Port 1 T1 Multipler Port 1 T1 Multipler.
UINT8 | SataP1T2M
Offset 0x06F3 - Port 1 T2 Multipler Port 1 T2 Multipler.
UINT8 | SataP1T3M
Offset 0x06F4 - Port 1 T3 Multipler Port 1 T3 Multipler.
UINT8 | SataP1TDisp
Offset 0x06F5 - Port 1 Tdispatch Port 1 Tdispatch.
UINT8 | SataP0Tinact
Offset 0x06F6 - Port 0 Tinactive Port 0 Tinactive.
UINT8 | SataP0TDispFinit
Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. More...
UINT8 | SataP1Tinact
Offset 0x06F8 - Port 1 Tinactive Port 1 Tinactive.
UINT8 | SataP1TDispFinit
Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. More...
UINT8 | SataThermalSuggestedSetting
Offset 0x06FA - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. More...
UINT8 | PchMemoryThrottlingEnable
Offset 0x06FB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. More...
UINT8 | PchMemoryPmsyncEnable [2]
Offset 0x06FC - Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT8 | PchMemoryC0TransmitEnable [2]
Offset 0x06FE - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT8 | PchMemoryPinSelection [2]
Offset 0x0700 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT16 | PchTemperatureHotLevel
Offset 0x0702 - Thermal Device Temperature Decides the temperature.
UINT8 | PchDisableComplianceMode
Offset 0x0704 - Disable XHCI Compliance Mode This policy will disable XHCI compliance mode on all ports. More...
UINT8 | Usb2OverCurrentPin [16]
Offset 0x0705 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N.
UINT8 | Usb3OverCurrentPin [10]
Offset 0x0715 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N.
UINT8 | Early8254ClockGatingEnable
Offset 0x071F - Enable 8254 Static Clock Gating in early POST time Set 8254CGE=1 is required for C11 support. More...
UINT8 | SataRstOptaneMemory
Offset 0x0720 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
UINT8 | SataRstCpuAttachedStorage
Offset 0x0721 - PCH SATA RST CPU attached storage RST CPU attached storage $EN_DIS.
UINT8 | UnusedUpdSpace19 [2]
Offset 0x0722.
UINT32 | PchPcieDeviceOverrideTablePtr
Offset 0x0724 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. More...
UINT8 | EnableTcoTimer
Offset 0x0728 - Enable TCO timer. More...
UINT8 | EcCmdProvisionEav
Offset 0x0729 - EcCmdProvisionEav Ephemeral Authorization Value default values. More...
UINT8 | EcCmdLock
Offset 0x072A - EcCmdLock EcCmdLock default values. More...
UINT8 | UnusedUpdSpace20 [5]
Offset 0x072B.
UINT64 | SendEcCmd
Offset 0x0730 - SendEcCmd SendEcCmd function pointer. More...
UINT64 | BgpdtHash [4]
Offset 0x0738 - BgpdtHash[4] BgpdtHash values.
UINT64 | BiosGuardModulePtr
Offset 0x0758 - BiosGuardModulePtr BiosGuardModulePtr default values.
UINT32 | BiosGuardAttr
Offset 0x0760 - BiosGuardAttr BiosGuardAttr default values.
UINT8 | SgxSinitNvsData
Offset 0x0764 - SgxSinitNvsData SgxSinitNvsData default values.
UINT8 | UnusedUpdSpace21 [3]
Offset 0x0765.
UINT64 | SgxEpoch0
Offset 0x0768 - SgxEpoch0 SgxEpoch0 default values.
UINT64 | SgxEpoch1
Offset 0x0770 - SgxEpoch1 SgxEpoch1 default values.
UINT8 | MeUnconfigOnRtcClear
Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear $EN_DIS.
UINT8 | MeUnconfigIsValid
Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. More...
UINT8 | IslVrCmd
Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues. More...
UINT8 | ReservedFspsUpd [5]
Offset 0x077B.

Detailed Description

Fsp S Configuration.

Definition at line 88 of file FspsUpd.h.

Member Data Documentation

UINT16 FSP_S_CONFIG::AcLoadline[5]

Offset 0x0298 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie.

1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU.

Definition at line 688 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AcousticNoiseMitigation

Offset 0x0278 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature.

0: Disabled; 1: Enabled $EN_DIS

Definition at line 633 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AmtEnabled

Offset 0x0153 - AMT Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS

Definition at line 410 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AmtSolEnabled

Offset 0x015C - SOL Switch Enable/Disable.

0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx $EN_DIS

Definition at line 453 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AsfEnabled

Offset 0x0155 - ASF Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable ASF functionality. $EN_DIS

Definition at line 422 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::DcLoadline[5]

Offset 0x02A2 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie.

1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU.

Definition at line 694 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DelayUsbPdoProgramming

Offset 0x00FC - Delay USB PDO Programming Enable/disable delay of PDO programming for USB from PEI phase to DXE phase.

0: disable, 1: enable $EN_DIS

Definition at line 373 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::DevIntConfigPtr

Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.

The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.

Definition at line 251 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DmiSuggestedSetting

Offset 0x06E9 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values.

$EN_DIS

Definition at line 1843 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Early8254ClockGatingEnable

Offset 0x071F - Enable 8254 Static Clock Gating in early POST time Set 8254CGE=1 is required for C11 support.

However, set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy OS boot before enabling this. $EN_DIS

Definition at line 1982 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EcCmdLock

Offset 0x072A - EcCmdLock EcCmdLock default values.

Locks Ephemeral Authorization Value sent previously

Definition at line 2024 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EcCmdProvisionEav

Offset 0x0729 - EcCmdProvisionEav Ephemeral Authorization Value default values.

Provisions an ephemeral shared secret to the EC

Definition at line 2019 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EnableTcoTimer

Offset 0x0728 - Enable TCO timer.

When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. $EN_DIS

Definition at line 2014 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EsataSpeedLimit

Offset 0x065E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.

$EN_DIS

Definition at line 1561 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableGt

Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 733 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableIa

Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 640 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableSa

Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 740 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FwProgress

Offset 0x0157 - PET Progress Enable/Disable.

0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. $EN_DIS

Definition at line 435 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::GpioIrqRoute

Offset 0x0087 - Select GPIO IRQ Route GPIO IRQ Select.

The valid value is 14 or 15.

Definition at line 270 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Heci3Enabled

Offset 0x0149 - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.

0: disable, 1: enable $EN_DIS

Definition at line 400 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::IccMax[5]

Offset 0x02CA - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit.

0-255A in 1/4 A units. 400 = 100A

Definition at line 717 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ImonOffset[5]

Offset 0x025D - Imon offset correction PCODE MMIO Mailbox: Imon offset correction.

Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto

Definition at line 591 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ImonSlope[5]

Offset 0x0258 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction.

Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes

Definition at line 585 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::IslVrCmd

Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.

Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.

Definition at line 2087 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ManageabilityMode

Offset 0x0156 - Manageability Mode set by Mebx Enable/Disable.

0: Disable, 1: enable, Enable or disable Manageability Mode. $EN_DIS

Definition at line 428 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::MeUnconfigIsValid

Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear.

$EN_DIS

Definition at line 2081 of file FspsUpd.h.

UINT64 FSP_S_CONFIG::MicrocodePatchAddress

Offset 0x02F0 - MicrocodePatchAddress Pointer to microcode patch that is suitable for this processor.

0:Disable, 1:Enable

Definition at line 775 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::NumOfDevIntConfig

Offset 0x006F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry.

If this is not zero, the DevIntConfigPtr must not be NULL.

Definition at line 246 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchCio2Enable

Offset 0x0030 - Enable CIO2 Controller Enable/disable SKYCAM CIO2 Controller.

$EN_DIS

Definition at line 137 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchCrid

Offset 0x0365 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled.

$EN_DIS

Definition at line 1192 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDisableComplianceMode

Offset 0x0704 - Disable XHCI Compliance Mode This policy will disable XHCI compliance mode on all ports.

Complicance Mode should be default enabled. $EN_DIS

Definition at line 1964 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDmiAspm

Offset 0x0316 - Enable DMI ASPM ASPM on PCH side of the DMI Link.

$EN_DIS

Definition at line 921 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDmiTsawEn

Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable.

$EN_DIS

Definition at line 1837 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspEnable

Offset 0x002E - Enable HD Audio DSP Enable/disable HD Audio DSP feature.

$EN_DIS

Definition at line 121 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspEndpointBluetooth

Offset 0x033F - DSP Bluetooth enablement 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1003 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspEndpointI2s

Offset 0x0348 - DSP I2S enablement 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1023 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PchHdaDspFeatureMask

Offset 0x0340 - Bitmask of supported DSP features [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6].

  • BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation.

Definition at line 1010 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspUaaCompliance

Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported).

$EN_DIS

Definition at line 986 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaEnable

Offset 0x002D - Enable Intel HD Audio (Azalia) Enable/disable Azalia controller.

$EN_DIS

Definition at line 115 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaIDispCodecDisconnect

Offset 0x033D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.

$EN_DIS

Definition at line 992 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaIoBufferOwnership

Offset 0x002F - Select HDAudio IoBuffer Ownership Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port.

0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers. 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports

Definition at line 131 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaPme

Offset 0x0336 - Enable Pme Enable Azalia wake-on-ring.

$EN_DIS

Definition at line 954 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicBdfValid

Offset 0x0349 - Enable PCH Io Apic Set to 1 if BDF value is valid.

$EN_DIS

Definition at line 1029 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicBusNumber

Offset 0x034A - PCH Io Apic Bus Number Bus/Device/Function used as Requestor / Completer ID.

Default is 0xF0.

Definition at line 1034 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicDeviceNumber

Offset 0x034B - PCH Io Apic Device Number Bus/Device/Function used as Requestor / Completer ID.

Default is 0x1F.

Definition at line 1039 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicEntry24_119

Offset 0x034D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1050 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicFunctionNumber

Offset 0x034C - PCH Io Apic Function Number Bus/Device/Function used as Requestor / Completer ID.

Default is 0x00.

Definition at line 1044 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicId

Offset 0x034E - PCH Io Apic ID This member determines IOAPIC ID.

Default is 0x02.

Definition at line 1055 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicRangeSelect

Offset 0x034F - PCH Io Apic Range Select Define address bits 19:12 for the IOxAPIC range.

Default is 0.

Definition at line 1060 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshEnable

Offset 0x0034 - Enable PCH ISH Controller Enable/disable ISH Controller.

$EN_DIS

Definition at line 161 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp0GpioAssign

Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1102 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp1GpioAssign

Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1108 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp2GpioAssign

Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1114 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp3GpioAssign

Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1120 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp4GpioAssign

Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1126 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp5GpioAssign

Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1132 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp6GpioAssign

Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1138 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp7GpioAssign

Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1144 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c0GpioAssign

Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1084 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c1GpioAssign

Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1090 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c2GpioAssign

Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1096 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshPdtUnlock

Offset 0x035E - PCH ISH PDT Unlock Msg 0: False; 1: True.

$EN_DIS

Definition at line 1150 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshSpiGpioAssign

Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1066 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshUart0GpioAssign

Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1072 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshUart1GpioAssign

Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1078 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanClkReqSupported

Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1168 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanEnable

Offset 0x00FB - Enable LAN Enable/disable LAN controller.

$EN_DIS

Definition at line 366 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanK1OffEnable

Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1162 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanLtrEnable

Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1156 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLockDownBiosLock

Offset 0x0363 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection.

$EN_DIS

Definition at line 1180 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLockDownSpiEiss

Offset 0x0364 - Enable LOCKDOWN SPI Eiss Enable InSMM.STS (EISS) in SPI.

$EN_DIS

Definition at line 1186 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchMemoryThrottlingEnable

Offset 0x06FB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.

$EN_DIS

Definition at line 1937 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PchPcieDeviceOverrideTablePtr

Offset 0x0724 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings.

This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0.

Definition at line 2006 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmCapsuleResetType

Offset 0x0655 - PCH Pm Capsule Reset Type Deprecated: Determines type of reset issued during UpdateCapsule().

Always Warm reset. $EN_DIS

Definition at line 1508 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDeepSxPol

Offset 0x0645 - PCH Pm Deep Sx Pol Deep Sx Policy.

$EN_DIS

Definition at line 1449 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDisableDsxAcPresentPulldown

Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.

$EN_DIS

Definition at line 1502 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDisableNativePowerButton

Offset 0x0656 - PCH Pm Disable Native Power Button Power button native mode disable.

$EN_DIS

Definition at line 1514 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmLanWakeFromDeepSx

Offset 0x0644 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx.

$EN_DIS

Definition at line 1443 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmLpcClockRun

Offset 0x0650 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled.

$EN_DIS

Definition at line 1479 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmMeWakeSts

Offset 0x0658 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.

$EN_DIS

Definition at line 1526 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPcieWakeFromDeepSx

Offset 0x0641 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx.

$EN_DIS

Definition at line 1424 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPmeB0S5Dis

Offset 0x0639 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.

$EN_DIS

Definition at line 1402 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPwrBtnOverridePeriod

Offset 0x0653 - PCH Pm Pwr Btn Override Period PCH power button override period.

000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.

Definition at line 1496 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPwrCycDur

Offset 0x065A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second.

Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ...

Definition at line 1538 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpAMinAssert

Offset 0x0649 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy.

Default is PchSlpA2s.

Definition at line 1469 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpLanLowDc

Offset 0x0652 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power.

$EN_DIS

Definition at line 1491 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0Enable

Offset 0x0657 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.

$EN_DIS

Definition at line 1520 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0VmEnable

Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state.

$EN_DIS

Definition at line 1408 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS3MinAssert

Offset 0x0646 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy.

Default is PchSlpS350ms.

Definition at line 1454 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS4MinAssert

Offset 0x0647 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy.

Default is PchSlpS44s.

Definition at line 1459 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpStrchSusUp

Offset 0x0651 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up.

$EN_DIS

Definition at line 1485 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpSusMinAssert

Offset 0x0648 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy.

Default is PchSlpSus4s.

Definition at line 1464 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWolEnableOverride

Offset 0x0640 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.

$EN_DIS

Definition at line 1418 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWolOvrWkSts

Offset 0x0659 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.

$EN_DIS

Definition at line 1532 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWoWlanDeepSxEnable

Offset 0x0643 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register.

$EN_DIS

Definition at line 1437 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWoWlanEnable

Offset 0x0642 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.

$EN_DIS

Definition at line 1430 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPort61hEnable

Offset 0x065C - PCH Port 61h Config Enable/Disable Used for the emulation feature for Port61h read.

The port is trapped and the SMI handler will toggle bit4 according to the handler's internal state. $EN_DIS

Definition at line 1549 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPwrOptEnable

Offset 0x0317 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side.

$EN_DIS

Definition at line 927 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchScsEmmcHs400DllDataValid

Offset 0x06C6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid.

$EN_DIS

Definition at line 1710 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchScsEmmcHs400TuningRequired

Offset 0x06C5 - Enable eMMC HS400 Training Determine if HS400 Training is required.

$EN_DIS

Definition at line 1704 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSirqEnable

Offset 0x06D8 - Enable Serial IRQ Determines if enable Serial IRQ.

$EN_DIS

Definition at line 1762 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSirqMode

Offset 0x06D9 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.

$EN_DIS

Definition at line 1768 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortACtleEnable

Offset 0x0303 - Enable SkyCam PortA Ctle Enable/disable PortA Ctle.

$EN_DIS

Definition at line 838 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortATermOvrEnable

Offset 0x02FB - Enable SkyCam PortA Termination override Enable/disable PortA Termination override.

$EN_DIS

Definition at line 790 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortATrimEnable

Offset 0x02FF - Enable SkyCam PortA Clk Trim Enable/disable PortA Clk Trim.

$EN_DIS

Definition at line 814 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortBCtleEnable

Offset 0x0304 - Enable SkyCam PortB Ctle Enable/disable PortB Ctle.

$EN_DIS

Definition at line 844 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortBTermOvrEnable

Offset 0x02FC - Enable SkyCam PortB Termination override Enable/disable PortB Termination override.

$EN_DIS

Definition at line 796 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortBTrimEnable

Offset 0x0300 - Enable SkyCam PortB Clk Trim Enable/disable PortB Clk Trim.

$EN_DIS

Definition at line 820 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortCDCtleEnable

Offset 0x0305 - Enable SkyCam PortCD Ctle Enable/disable PortCD Ctle.

$EN_DIS

Definition at line 850 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortCTermOvrEnable

Offset 0x02FD - Enable SkyCam PortC Termination override Enable/disable PortC Termination override.

$EN_DIS

Definition at line 802 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortCTrimEnable

Offset 0x0301 - Enable SkyCam PortC Clk Trim Enable/disable PortC Clk Trim.

$EN_DIS

Definition at line 826 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortDTermOvrEnable

Offset 0x02FE - Enable SkyCam PortD Termination override Enable/disable PortD Termination override.

$EN_DIS

Definition at line 808 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortDTrimEnable

Offset 0x0302 - Enable SkyCam PortD Clk Trim Enable/disable PortD Clk Trim.

$EN_DIS

Definition at line 832 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::PchSubSystemId

Offset 0x0368 - PCH Sub system ID Default Subsystem ID of the PCH devices.

Default is 0x7270.

Definition at line 1202 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::PchSubSystemVendorId

Offset 0x0366 - PCH Sub system vendor ID Default Subsystem Vendor ID of the PCH devices.

Default is 0x8086.

Definition at line 1197 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchThermalDeviceEnable

Offset 0x06DB - Enable Thermal Device Enable Thermal Device.

$EN_DIS

Definition at line 1779 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTsmicLock

Offset 0x06E2 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip.

$EN_DIS

Definition at line 1800 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTEnable

Offset 0x06E3 - Enable The Thermal Throttle Enable the thermal throttle function.

$EN_DIS

Definition at line 1806 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTLock

Offset 0x06E5 - Thermal Throttle Lock Thermal Throttle Lock.

$EN_DIS

Definition at line 1819 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTState13Enable

Offset 0x06E4 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.

$EN_DIS

Definition at line 1813 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieAllowNoLtrIccPllShutdown

Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable or leaving untouched.

$EN_DIS

Definition at line 1377 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieComplianceTestMode

Offset 0x0635 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board.

$EN_DIS

Definition at line 1383 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieDisableRootPortClockGating

Offset 0x0632 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules.

0: Disable; 1: Enable. $EN_DIS

Definition at line 1364 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEnablePeerMemoryWrite

Offset 0x0633 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform.

$EN_DIS

Definition at line 1370 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEqPh3LaneParamCm[24]

Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM.

Coefficient C-1.

Definition at line 1342 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEqPh3LaneParamCp[24]

Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM.

Coefficient C+1.

Definition at line 1347 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpAspm[24]

Offset 0x0598 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL).

Default is PchPcieAspmAutoConfig.

Definition at line 1321 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpClkReqNumber[24]

Offset 0x012C - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported.

Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.

Definition at line 389 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpClkReqSupport[24]

Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support.

0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.

Definition at line 383 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpClkSrcNumber[24]

Offset 0x015D - Configure CLKSRC Number Configure Root Port CLKSRC Number.

Each value in arrary can be between 0-6 for valid clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for port1, byte1 for port2, and so on.

Definition at line 460 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpCompletionTimeout[24]

Offset 0x0520 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT).

Default is PchPcieCompletionTO_Default.

Definition at line 1309 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PcieRpDeviceResetPad[24]

Offset 0x0538 - PCIE RP Device Reset Pad The PCH pin assigned to device PERST# signal if available, zero otherwise.

See also DeviceResetPadActiveHigh.

Definition at line 1315 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpFunctionSwap

Offset 0x0638 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled.

$EN_DIS

Definition at line 1396 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpGen3EqPh3Method[24]

Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD).

0: Default; 2: Software Search; 4: Fixed Coeficients.

Definition at line 1299 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpL1Substates[24]

Offset 0x05B0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).

Default is PchPcieL1SubstatesL1_1_2.

Definition at line 1327 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpPcieSpeed[24]

Offset 0x04D8 - PCIE RP Pcie Speed Determines each PCIE Port speed capability.

0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED).

Definition at line 1293 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpPhysicalSlotNumber[24]

Offset 0x0508 - PCIE RP Physical Slot Number Indicates the slot number for the root port.

Default is the value as root port index.

Definition at line 1304 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieSwEqCoeffListCm[5]

Offset 0x0628 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM.

Coefficient C-1.

Definition at line 1352 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieSwEqCoeffListCp[5]

Offset 0x062D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM.

Coefficient C+1.

Definition at line 1357 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PortUsb20Enable[16]

Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 218 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PortUsb30Enable[10]

Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 224 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi1Threshold[5]

Offset 0x02AC - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments.

Range is 0-128A. Default Value = 20A.

Definition at line 700 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi2Threshold[5]

Offset 0x02B6 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments.

Range is 0-128A. Default Value = 5A.

Definition at line 706 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Psi3Enable[5]

Offset 0x024E - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable.

For all VR Indexes

Definition at line 573 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi3Threshold[5]

Offset 0x02C0 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments.

Range is 0-128A. Default Value = 1A.

Definition at line 712 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PsysOffset

Offset 0x0277 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction.

0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset

Definition at line 627 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PsysSlope

Offset 0x0276 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction.

0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25

Definition at line 621 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PxRcConfig[8]

Offset 0x007F - PIRQx to IRQx Map Config PIRQx to IRQx mapping.

The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode.

Definition at line 265 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataEnable

Offset 0x0091 - Enable SATA Enable/disable SATA controller.

$EN_DIS

Definition at line 306 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataMode

Offset 0x0092 - SATA Mode Select SATA controller working mode.

0:AHCI, 1:RAID

Definition at line 312 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataP0TDispFinit

Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch.

$EN_DIS

Definition at line 1914 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataP1TDispFinit

Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch.

$EN_DIS

Definition at line 1925 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsDevSlp[8]

Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port.

0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 212 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsDmVal[8]

Offset 0x0690 - Enable SATA Port DmVal DITO multiplier.

Default is 15.

Definition at line 1601 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsEnable[8]

Offset 0x0042 - Enable SATA ports Enable/disable SATA ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 206 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPwrOptEnable

Offset 0x065D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side.

$EN_DIS

Definition at line 1555 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstHddUnlock

Offset 0x06B8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled.

$EN_DIS

Definition at line 1664 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstIrrt

Offset 0x06B5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology.

$EN_DIS

Definition at line 1647 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstIrrtOnly

Offset 0x06BA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports.

$EN_DIS

Definition at line 1677 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstLedLocate

Offset 0x06B9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.

$EN_DIS

Definition at line 1671 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstOromUiBanner

Offset 0x06B6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER.

$EN_DIS

Definition at line 1653 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstPcieDeviceResetDelay[3]

Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds.

Default value is 100ms

Definition at line 1698 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid0

Offset 0x06B1 - PCH Sata Rst Raid0 RAID0.

$EN_DIS

Definition at line 1623 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid1

Offset 0x06B2 - PCH Sata Rst Raid1 RAID1.

$EN_DIS

Definition at line 1629 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid10

Offset 0x06B3 - PCH Sata Rst Raid10 RAID10.

$EN_DIS

Definition at line 1635 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid5

Offset 0x06B4 - PCH Sata Rst Raid5 RAID5.

$EN_DIS

Definition at line 1641 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaidAlternateId

Offset 0x06B0 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID.

0:Client, 1:Alternate, 2:Server

Definition at line 1617 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstSmartStorage

Offset 0x06BB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit.

$EN_DIS

Definition at line 1683 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataSalpSupport

Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management.

$EN_DIS

Definition at line 200 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataThermalSuggestedSetting

Offset 0x06FA - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting.

$EN_DIS

Definition at line 1931 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SciIrqSelect

Offset 0x0088 - Select SciIrqSelect SCI IRQ Select.

The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.

Definition at line 275 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsEmmcEnabled

Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller.

$EN_DIS

Definition at line 143 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsEmmcHs400Enabled

Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode.

$EN_DIS

Definition at line 149 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsSdCardEnabled

Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller.

$EN_DIS

Definition at line 155 of file FspsUpd.h.

UINT64 FSP_S_CONFIG::SendEcCmd

Offset 0x0730 - SendEcCmd SendEcCmd function pointer.

typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData);

Definition at line 2035 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SendVrMbxCmd

Offset 0x02E2 - Enable VR specific mailbox command VR specific mailbox commands.

00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved. $EN_DIS

Definition at line 752 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SendVrMbxCmd1

Offset 0x02E3 - Select VR specific mailbox command to send VR specific mailbox commands.

000b - no VR specific command sent. 001b - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue.

Definition at line 759 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoDebugUartNumber

Offset 0x06D6 - UART Number For Debug Purpose UART number for debug purpose.

0:UART0, 1: UART1, 2:UART2.

Definition at line 1751 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoDevMode[11]

Offset 0x0074 - Enable SerialIo Device Mode 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively.

One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.

Definition at line 258 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoGpio

Offset 0x06CA - Enable Pch Serial IO GPIO Determines if enable Serial IO GPIO.

$EN_DIS

Definition at line 1731 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ShowSpiController

Offset 0x0035 - Show SPI controller Enable/disable to show SPI controller.

$EN_DIS

Definition at line 167 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForGt

Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 654 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForIa

Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 647 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForSa

Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 661 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SpiFlashCfgLockDown

Offset 0x0036 - Flash Configuration Lock Down Enable/disable flash lock down.

If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. $EN_DIS

Definition at line 174 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SsicPortEnable

Offset 0x006D - Enable XHCI SSIC Enable Enable/disable XHCI SSIC port.

$EN_DIS

Definition at line 236 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TcoIrqSelect

Offset 0x0089 - Select TcoIrqSelect TCO IRQ Select.

The valid value is 9, 10, 11, 20, 21, 22, 23.

Definition at line 280 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::TdcPowerLimit[5]

Offset 0x0286 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit.

Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes

Definition at line 671 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TdcTimeWindow[5]

Offset 0x026C - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window.

Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe

Definition at line 609 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TTSuggestedSetting

Offset 0x06E6 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting.

$EN_DIS

Definition at line 1825 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TurboMode

Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode.

0: disable, 1: enable $EN_DIS

Definition at line 194 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePehalfbit[16]

Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis.

1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port.

Definition at line 336 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePetxiset[16]

Offset 0x0093 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias.

000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.

Definition at line 318 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePredeemp[16]

Offset 0x00B3 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis.

00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.

Definition at line 330 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfeTxiset[16]

Offset 0x00A3 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias.

000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.

Definition at line 324 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDeEmph[10]

Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis).

One byte for each port.

Definition at line 348 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDeEmphEnable[10]

Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment.

Each value in arrary can be between 0-1. One byte for each port.

Definition at line 342 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDownscaleAmp[10]

Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h.

One byte for each port.

Definition at line 360 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDownscaleAmpEnable[10]

Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1.

One byte for each port.

Definition at line 354 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::VrPowerDeliveryDesign

Offset 0x0290 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board.

This value is an enum of the available power delivery segments that are defined in the Platform Design Guide.

Definition at line 678 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::VrVoltageLimit[5]

Offset 0x02D4 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit.

Range is 0-7999mV.

Definition at line 722 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::WatchDog

Offset 0x0154 - WatchDog Timer Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable WatchDog timer. $EN_DIS

Definition at line 416 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::WatchDogTimerBios

Offset 0x015A - BIOS Timer 16 bits Value, Set BIOS watchdog timer.

$EN_DIS

Definition at line 447 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::WatchDogTimerOs

Offset 0x0158 - OS Timer 16 bits Value, Set OS watchdog timer.

$EN_DIS

Definition at line 441 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::XdciEnable

Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller.

$EN_DIS

Definition at line 230 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_S_CONFIG Member List

This is the complete list of members for FSP_S_CONFIG, including all inherited members.

AcLoadline | FSP_S_CONFIG
AcousticNoiseMitigation | FSP_S_CONFIG
AmtEnabled | FSP_S_CONFIG
AmtSolEnabled | FSP_S_CONFIG
AsfEnabled | FSP_S_CONFIG
BgpdtHash | FSP_S_CONFIG
BiosGuardAttr | FSP_S_CONFIG
BiosGuardModulePtr | FSP_S_CONFIG
CdClock | FSP_S_CONFIG
CpuConfig | FSP_S_CONFIG
CpuS3ResumeMtrrData | FSP_S_CONFIG
CpuS3ResumeMtrrDataSize | FSP_S_CONFIG
CridEnable | FSP_S_CONFIG
DcLoadline | FSP_S_CONFIG
DefaultSid | FSP_S_CONFIG
DefaultSvid | FSP_S_CONFIG
DelayUsbPdoProgramming | FSP_S_CONFIG
Device4Enable | FSP_S_CONFIG
DevIntConfigPtr | FSP_S_CONFIG
DmiAspm | FSP_S_CONFIG
DmiSuggestedSetting | FSP_S_CONFIG
DmiTS0TW | FSP_S_CONFIG
DmiTS1TW | FSP_S_CONFIG
DmiTS2TW | FSP_S_CONFIG
DmiTS3TW | FSP_S_CONFIG
Early8254ClockGatingEnable | FSP_S_CONFIG
EcCmdLock | FSP_S_CONFIG
EcCmdProvisionEav | FSP_S_CONFIG
EnableTcoTimer | FSP_S_CONFIG
EsataSpeedLimit | FSP_S_CONFIG
FastPkgCRampDisableGt | FSP_S_CONFIG
FastPkgCRampDisableIa | FSP_S_CONFIG
FastPkgCRampDisableSa | FSP_S_CONFIG
FwProgress | FSP_S_CONFIG
GmmEnable | FSP_S_CONFIG
GpioIrqRoute | FSP_S_CONFIG
GraphicsConfigPtr | FSP_S_CONFIG
Heci3Enabled | FSP_S_CONFIG
IccMax | FSP_S_CONFIG
ImonOffset | FSP_S_CONFIG
ImonSlope | FSP_S_CONFIG
IslVrCmd | FSP_S_CONFIG
LogoPtr | FSP_S_CONFIG
LogoSize | FSP_S_CONFIG
ManageabilityMode | FSP_S_CONFIG
MeUnconfigIsValid | FSP_S_CONFIG
MeUnconfigOnRtcClear | FSP_S_CONFIG
MicrocodePatchAddress | FSP_S_CONFIG
MicrocodeRegionBase | FSP_S_CONFIG
MicrocodeRegionSize | FSP_S_CONFIG
NumOfDevIntConfig | FSP_S_CONFIG
PavpEnable | FSP_S_CONFIG
PchCio2Enable | FSP_S_CONFIG
PchCrid | FSP_S_CONFIG
PchDisableComplianceMode | FSP_S_CONFIG
PchDmiAspm | FSP_S_CONFIG
PchDmiTsawEn | FSP_S_CONFIG
PchHdaDspEnable | FSP_S_CONFIG
PchHdaDspEndpointBluetooth | FSP_S_CONFIG
PchHdaDspEndpointDmic | FSP_S_CONFIG
PchHdaDspEndpointI2s | FSP_S_CONFIG
PchHdaDspFeatureMask | FSP_S_CONFIG
PchHdaDspPpModuleMask | FSP_S_CONFIG
PchHdaDspUaaCompliance | FSP_S_CONFIG
PchHdaEnable | FSP_S_CONFIG
PchHdaIDispCodecDisconnect | FSP_S_CONFIG
PchHdaIDispLinkFrequency | FSP_S_CONFIG
PchHdaIDispLinkTmode | FSP_S_CONFIG
PchHdaIoBufferOwnership | FSP_S_CONFIG
PchHdaIoBufferVoltage | FSP_S_CONFIG
PchHdaLinkFrequency | FSP_S_CONFIG
PchHdaPme | FSP_S_CONFIG
PchHdaVcType | FSP_S_CONFIG
PchHdaVerbTableEntryNum | FSP_S_CONFIG
PchHdaVerbTablePtr | FSP_S_CONFIG
PchIoApicBdfValid | FSP_S_CONFIG
PchIoApicBusNumber | FSP_S_CONFIG
PchIoApicDeviceNumber | FSP_S_CONFIG
PchIoApicEntry24_119 | FSP_S_CONFIG
PchIoApicFunctionNumber | FSP_S_CONFIG
PchIoApicId | FSP_S_CONFIG
PchIoApicRangeSelect | FSP_S_CONFIG
PchIshEnable | FSP_S_CONFIG
PchIshGp0GpioAssign | FSP_S_CONFIG
PchIshGp1GpioAssign | FSP_S_CONFIG
PchIshGp2GpioAssign | FSP_S_CONFIG
PchIshGp3GpioAssign | FSP_S_CONFIG
PchIshGp4GpioAssign | FSP_S_CONFIG
PchIshGp5GpioAssign | FSP_S_CONFIG
PchIshGp6GpioAssign | FSP_S_CONFIG
PchIshGp7GpioAssign | FSP_S_CONFIG
PchIshI2c0GpioAssign | FSP_S_CONFIG
PchIshI2c1GpioAssign | FSP_S_CONFIG
PchIshI2c2GpioAssign | FSP_S_CONFIG
PchIshPdtUnlock | FSP_S_CONFIG
PchIshSpiGpioAssign | FSP_S_CONFIG
PchIshUart0GpioAssign | FSP_S_CONFIG
PchIshUart1GpioAssign | FSP_S_CONFIG
PchLanClkReqNumber | FSP_S_CONFIG
PchLanClkReqSupported | FSP_S_CONFIG
PchLanEnable | FSP_S_CONFIG
PchLanK1OffEnable | FSP_S_CONFIG
PchLanLtrEnable | FSP_S_CONFIG
PchLegacyIoLowLatency | FSP_S_CONFIG
PchLockDownBiosLock | FSP_S_CONFIG
PchLockDownSpiEiss | FSP_S_CONFIG
PchMemoryC0TransmitEnable | FSP_S_CONFIG
PchMemoryPinSelection | FSP_S_CONFIG
PchMemoryPmsyncEnable | FSP_S_CONFIG
PchMemoryThrottlingEnable | FSP_S_CONFIG
PchPcieDeviceOverrideTablePtr | FSP_S_CONFIG
PchPmCapsuleResetType | FSP_S_CONFIG
PchPmDeepSxPol | FSP_S_CONFIG
PchPmDisableDsxAcPresentPulldown | FSP_S_CONFIG
PchPmDisableNativePowerButton | FSP_S_CONFIG
PchPmLanWakeFromDeepSx | FSP_S_CONFIG
PchPmLpcClockRun | FSP_S_CONFIG
PchPmMeWakeSts | FSP_S_CONFIG
PchPmPcieWakeFromDeepSx | FSP_S_CONFIG
PchPmPmeB0S5Dis | FSP_S_CONFIG
PchPmPwrBtnOverridePeriod | FSP_S_CONFIG
PchPmPwrCycDur | FSP_S_CONFIG
PchPmSlpAMinAssert | FSP_S_CONFIG
PchPmSlpLanLowDc | FSP_S_CONFIG
PchPmSlpS0Enable | FSP_S_CONFIG
PchPmSlpS0VmEnable | FSP_S_CONFIG
PchPmSlpS3MinAssert | FSP_S_CONFIG
PchPmSlpS4MinAssert | FSP_S_CONFIG
PchPmSlpStrchSusUp | FSP_S_CONFIG
PchPmSlpSusMinAssert | FSP_S_CONFIG
PchPmWolEnableOverride | FSP_S_CONFIG
PchPmWolOvrWkSts | FSP_S_CONFIG
PchPmWoWlanDeepSxEnable | FSP_S_CONFIG
PchPmWoWlanEnable | FSP_S_CONFIG
PchPort61hEnable | FSP_S_CONFIG
PchProtectedRangeBase | FSP_S_CONFIG
PchProtectedRangeLimit | FSP_S_CONFIG
PchPwrOptEnable | FSP_S_CONFIG
PchReadProtectionEnable | FSP_S_CONFIG
PchScsEmmcHs400DllDataValid | FSP_S_CONFIG
PchScsEmmcHs400DriverStrength | FSP_S_CONFIG
PchScsEmmcHs400RxStrobeDll1 | FSP_S_CONFIG
PchScsEmmcHs400TuningRequired | FSP_S_CONFIG
PchScsEmmcHs400TxDataDll | FSP_S_CONFIG
PchSirqEnable | FSP_S_CONFIG
PchSirqMode | FSP_S_CONFIG
PchSkyCamPortAClkTrimValue | FSP_S_CONFIG
PchSkyCamPortACtleCapValue | FSP_S_CONFIG
PchSkyCamPortACtleEnable | FSP_S_CONFIG
PchSkyCamPortACtleResValue | FSP_S_CONFIG
PchSkyCamPortADataTrimValue | FSP_S_CONFIG
PchSkyCamPortATermOvrEnable | FSP_S_CONFIG
PchSkyCamPortATrimEnable | FSP_S_CONFIG
PchSkyCamPortBClkTrimValue | FSP_S_CONFIG
PchSkyCamPortBCtleCapValue | FSP_S_CONFIG
PchSkyCamPortBCtleEnable | FSP_S_CONFIG
PchSkyCamPortBCtleResValue | FSP_S_CONFIG
PchSkyCamPortBDataTrimValue | FSP_S_CONFIG
PchSkyCamPortBTermOvrEnable | FSP_S_CONFIG
PchSkyCamPortBTrimEnable | FSP_S_CONFIG
PchSkyCamPortCClkTrimValue | FSP_S_CONFIG
PchSkyCamPortCDCtleCapValue | FSP_S_CONFIG
PchSkyCamPortCDCtleEnable | FSP_S_CONFIG
PchSkyCamPortCDCtleResValue | FSP_S_CONFIG
PchSkyCamPortCDDataTrimValue | FSP_S_CONFIG
PchSkyCamPortCTermOvrEnable | FSP_S_CONFIG
PchSkyCamPortCTrimEnable | FSP_S_CONFIG
PchSkyCamPortDClkTrimValue | FSP_S_CONFIG
PchSkyCamPortDTermOvrEnable | FSP_S_CONFIG
PchSkyCamPortDTrimEnable | FSP_S_CONFIG
PchStartFramePulse | FSP_S_CONFIG
PchSubSystemId | FSP_S_CONFIG
PchSubSystemVendorId | FSP_S_CONFIG
PchT0Level | FSP_S_CONFIG
PchT1Level | FSP_S_CONFIG
PchT2Level | FSP_S_CONFIG
PchTemperatureHotLevel | FSP_S_CONFIG
PchThermalDeviceEnable | FSP_S_CONFIG
PchTsmicLock | FSP_S_CONFIG
PchTTEnable | FSP_S_CONFIG
PchTTLock | FSP_S_CONFIG
PchTTState13Enable | FSP_S_CONFIG
PchWriteProtectionEnable | FSP_S_CONFIG
PcieAllowNoLtrIccPllShutdown | FSP_S_CONFIG
PcieComplianceTestMode | FSP_S_CONFIG
PcieDetectTimeoutMs | FSP_S_CONFIG
PcieDisableRootPortClockGating | FSP_S_CONFIG
PcieEnablePeerMemoryWrite | FSP_S_CONFIG
PcieEqPh3LaneParamCm | FSP_S_CONFIG
PcieEqPh3LaneParamCp | FSP_S_CONFIG
PcieRpAdvancedErrorReporting | FSP_S_CONFIG
PcieRpAspm | FSP_S_CONFIG
PcieRpClkReqDetect | FSP_S_CONFIG
PcieRpClkReqNumber | FSP_S_CONFIG
PcieRpClkReqSupport | FSP_S_CONFIG
PcieRpClkSrcNumber | FSP_S_CONFIG
PcieRpCompletionTimeout | FSP_S_CONFIG
PcieRpCorrectableErrorReport | FSP_S_CONFIG
PcieRpDeviceResetPad | FSP_S_CONFIG
PcieRpDeviceResetPadActiveHigh | FSP_S_CONFIG
PcieRpExtSync | FSP_S_CONFIG
PcieRpFatalErrorReport | FSP_S_CONFIG
PcieRpFunctionSwap | FSP_S_CONFIG
PcieRpGen3EqPh3Method | FSP_S_CONFIG
PcieRpHotPlug | FSP_S_CONFIG
PcieRpL1Substates | FSP_S_CONFIG
PcieRpLtrConfigLock | FSP_S_CONFIG
PcieRpLtrEnable | FSP_S_CONFIG
PcieRpMaxPayload | FSP_S_CONFIG
PcieRpNoFatalErrorReport | FSP_S_CONFIG
PcieRpPcieSpeed | FSP_S_CONFIG
PcieRpPhysicalSlotNumber | FSP_S_CONFIG
PcieRpPmSci | FSP_S_CONFIG
PcieRpSystemErrorOnCorrectableError | FSP_S_CONFIG
PcieRpSystemErrorOnFatalError | FSP_S_CONFIG
PcieRpSystemErrorOnNonFatalError | FSP_S_CONFIG
PcieRpTransmitterHalfSwing | FSP_S_CONFIG
PcieRpUnsupportedRequestReport | FSP_S_CONFIG
PcieSwEqCoeffListCm | FSP_S_CONFIG
PcieSwEqCoeffListCp | FSP_S_CONFIG
PegDeEmphasis | FSP_S_CONFIG
PegPhysicalSlotNumber | FSP_S_CONFIG
PegSlotPowerLimitScale | FSP_S_CONFIG
PegSlotPowerLimitValue | FSP_S_CONFIG
PeiGraphicsPeimInit | FSP_S_CONFIG
PortUsb20Enable | FSP_S_CONFIG
PortUsb30Enable | FSP_S_CONFIG
Psi1Threshold | FSP_S_CONFIG
Psi2Threshold | FSP_S_CONFIG
Psi3Enable | FSP_S_CONFIG
Psi3Threshold | FSP_S_CONFIG
Psi4Enable | FSP_S_CONFIG
PsysOffset | FSP_S_CONFIG
PsysSlope | FSP_S_CONFIG
PxRcConfig | FSP_S_CONFIG
ReservedFspsUpd | FSP_S_CONFIG
SaImguEnable | FSP_S_CONFIG
SaPostMemProductionRsvd | FSP_S_CONFIG
SataEnable | FSP_S_CONFIG
SataMode | FSP_S_CONFIG
SataP0T1M | FSP_S_CONFIG
SataP0T2M | FSP_S_CONFIG
SataP0T3M | FSP_S_CONFIG
SataP0TDisp | FSP_S_CONFIG
SataP0TDispFinit | FSP_S_CONFIG
SataP0Tinact | FSP_S_CONFIG
SataP1T1M | FSP_S_CONFIG
SataP1T2M | FSP_S_CONFIG
SataP1T3M | FSP_S_CONFIG
SataP1TDisp | FSP_S_CONFIG
SataP1TDispFinit | FSP_S_CONFIG
SataP1Tinact | FSP_S_CONFIG
SataPortsDevSlp | FSP_S_CONFIG
SataPortsDitoVal | FSP_S_CONFIG
SataPortsDmVal | FSP_S_CONFIG
SataPortsEnable | FSP_S_CONFIG
SataPortsEnableDitoConfig | FSP_S_CONFIG
SataPortsExternal | FSP_S_CONFIG
SataPortsHotPlug | FSP_S_CONFIG
SataPortsInterlockSw | FSP_S_CONFIG
SataPortsSolidStateDrive | FSP_S_CONFIG
SataPortsSpinUp | FSP_S_CONFIG
SataPortsZpOdd | FSP_S_CONFIG
SataPwrOptEnable | FSP_S_CONFIG
SataRstCpuAttachedStorage | FSP_S_CONFIG
SataRstHddUnlock | FSP_S_CONFIG
SataRstIrrt | FSP_S_CONFIG
SataRstIrrtOnly | FSP_S_CONFIG
SataRstLedLocate | FSP_S_CONFIG
SataRstOptaneMemory | FSP_S_CONFIG
SataRstOromUiBanner | FSP_S_CONFIG
SataRstOromUiDelay | FSP_S_CONFIG
SataRstPcieDeviceResetDelay | FSP_S_CONFIG
SataRstPcieEnable | FSP_S_CONFIG
SataRstPcieStoragePort | FSP_S_CONFIG
SataRstRaid0 | FSP_S_CONFIG
SataRstRaid1 | FSP_S_CONFIG
SataRstRaid10 | FSP_S_CONFIG
SataRstRaid5 | FSP_S_CONFIG
SataRstRaidAlternateId | FSP_S_CONFIG
SataRstSmartStorage | FSP_S_CONFIG
SataSalpSupport | FSP_S_CONFIG
SataSpeedLimit | FSP_S_CONFIG
SataThermalSuggestedSetting | FSP_S_CONFIG
SciIrqSelect | FSP_S_CONFIG
ScsEmmcEnabled | FSP_S_CONFIG
ScsEmmcHs400Enabled | FSP_S_CONFIG
ScsSdCardEnabled | FSP_S_CONFIG
SendEcCmd | FSP_S_CONFIG
SendVrMbxCmd | FSP_S_CONFIG
SendVrMbxCmd1 | FSP_S_CONFIG
SerialIoDebugUartNumber | FSP_S_CONFIG
SerialIoDevMode | FSP_S_CONFIG
SerialIoEnableDebugUartAfterPost | FSP_S_CONFIG
SerialIoGpio | FSP_S_CONFIG
SerialIoI2cVoltage | FSP_S_CONFIG
SerialIoSpiCsPolarity | FSP_S_CONFIG
SerialIoUartHwFlowCtrl | FSP_S_CONFIG
SgxEpoch0 | FSP_S_CONFIG
SgxEpoch1 | FSP_S_CONFIG
SgxSinitNvsData | FSP_S_CONFIG
ShowSpiController | FSP_S_CONFIG
SlowSlewRateForGt | FSP_S_CONFIG
SlowSlewRateForIa | FSP_S_CONFIG
SlowSlewRateForSa | FSP_S_CONFIG
SpiFlashCfgLockDown | FSP_S_CONFIG
SsicPortEnable | FSP_S_CONFIG
TcoIrqEnable | FSP_S_CONFIG
TcoIrqSelect | FSP_S_CONFIG
TdcEnable | FSP_S_CONFIG
TdcLock | FSP_S_CONFIG
TdcPowerLimit | FSP_S_CONFIG
TdcTimeWindow | FSP_S_CONFIG
TTCrossThrottling | FSP_S_CONFIG
TTSuggestedSetting | FSP_S_CONFIG
TurboMode | FSP_S_CONFIG
UnusedUpdSpace0 | FSP_S_CONFIG
UnusedUpdSpace1 | FSP_S_CONFIG
UnusedUpdSpace10 | FSP_S_CONFIG
UnusedUpdSpace11 | FSP_S_CONFIG
UnusedUpdSpace12 | FSP_S_CONFIG
UnusedUpdSpace13 | FSP_S_CONFIG
UnusedUpdSpace14 | FSP_S_CONFIG
UnusedUpdSpace15 | FSP_S_CONFIG
UnusedUpdSpace16 | FSP_S_CONFIG
UnusedUpdSpace17 | FSP_S_CONFIG
UnusedUpdSpace18 | FSP_S_CONFIG
UnusedUpdSpace19 | FSP_S_CONFIG
UnusedUpdSpace2 | FSP_S_CONFIG
UnusedUpdSpace20 | FSP_S_CONFIG
UnusedUpdSpace21 | FSP_S_CONFIG
UnusedUpdSpace3 | FSP_S_CONFIG
UnusedUpdSpace4 | FSP_S_CONFIG
UnusedUpdSpace5 | FSP_S_CONFIG
UnusedUpdSpace6 | FSP_S_CONFIG
UnusedUpdSpace7 | FSP_S_CONFIG
UnusedUpdSpace8 | FSP_S_CONFIG
UnusedUpdSpace9 | FSP_S_CONFIG
Usb2AfePehalfbit | FSP_S_CONFIG
Usb2AfePetxiset | FSP_S_CONFIG
Usb2AfePredeemp | FSP_S_CONFIG
Usb2AfeTxiset | FSP_S_CONFIG
Usb2OverCurrentPin | FSP_S_CONFIG
Usb3HsioTxDeEmph | FSP_S_CONFIG
Usb3HsioTxDeEmphEnable | FSP_S_CONFIG
Usb3HsioTxDownscaleAmp | FSP_S_CONFIG
Usb3HsioTxDownscaleAmpEnable | FSP_S_CONFIG
Usb3OverCurrentPin | FSP_S_CONFIG
VrConfigEnable | FSP_S_CONFIG
VrPowerDeliveryDesign | FSP_S_CONFIG
VrVoltageLimit | FSP_S_CONFIG
VtdBaseAddress | FSP_S_CONFIG
WatchDog | FSP_S_CONFIG
WatchDogTimerBios | FSP_S_CONFIG
WatchDogTimerOs | FSP_S_CONFIG
X2ApicOptOut | FSP_S_CONFIG
XdciEnable | FSP_S_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_S_TEST_CONFIG Struct Reference

Public Attributes | List of all members
FSP_S_TEST_CONFIG Struct Reference

Fsp S Test Configuration. More...

#include <FspsUpd.h>

Public Attributes

UINT32 | Signature
Offset 0x0780.
UINT8 | ChapDeviceEnable
Offset 0x0784 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disabled $EN_DIS.
UINT8 | SkipPamLock
Offset 0x0785 - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS.
UINT8 | EdramTestMode
Offset 0x0786 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode.
UINT8 | DmiExtSync
Offset 0x0787 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS.
UINT8 | DmiIot
Offset 0x0788 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control $EN_DIS.
UINT8 | PegMaxPayload [3]
Offset 0x0789 - PEG Max Payload size per root port 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B.
UINT8 | RenderStandby
Offset 0x078C - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS.
UINT8 | PmSupport
Offset 0x078D - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS.
UINT8 | CdynmaxClampEnable
Offset 0x078E - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS.
UINT8 | VtdDisable
Offset 0x078F - Disable VT-d 0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled) $EN_DIS.
UINT8 | GtFreqMax
Offset 0x0790 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz.
UINT8 | SaPostMemTestRsvd [11]
Offset 0x0791 - SaPostMemTestRsvd Reserved for SA Post-Mem Test $EN_DIS.
UINT8 | OneCoreRatioLimit
Offset 0x079C - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | TwoCoreRatioLimit
Offset 0x079D - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | ThreeCoreRatioLimit
Offset 0x079E - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | FourCoreRatioLimit
Offset 0x079F - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | UnusedUpdSpace22
Offset 0x07A0.
UINT8 | Hwp
Offset 0x07A1 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. More...
UINT8 | HdcControl
Offset 0x07A2 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. More...
UINT8 | PowerLimit1Time
Offset 0x07A3 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. More...
UINT8 | PowerLimit2
Offset 0x07A4 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. More...
UINT8 | TurboPowerLimitLock
Offset 0x07A5 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS.
UINT8 | PowerLimit3Time
Offset 0x07A6 - Package PL3 time window Package PL3 time window range for this policy in milliseconds. More...
UINT8 | PowerLimit3DutyCycle
Offset 0x07A7 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100.
UINT8 | PowerLimit3Lock
Offset 0x07A8 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS.
UINT8 | PowerLimit4Lock
Offset 0x07A9 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS.
UINT8 | TccActivationOffset
Offset 0x07AA - TCC Activation Offset TCC Activation Offset. More...
UINT8 | TccOffsetClamp
Offset 0x07AB - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. More...
UINT8 | TccOffsetLock
Offset 0x07AC - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. More...
UINT8 | NumberOfEntries
Offset 0x07AD - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. More...
UINT8 | Custom1PowerLimit1Time
Offset 0x07AE - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. More...
UINT8 | Custom1TurboActivationRatio
Offset 0x07AF - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. More...
UINT8 | Custom1ConfigTdpControl
Offset 0x07B0 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
UINT8 | Custom2PowerLimit1Time
Offset 0x07B1 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. More...
UINT8 | Custom2TurboActivationRatio
Offset 0x07B2 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. More...
UINT8 | Custom2ConfigTdpControl
Offset 0x07B3 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
UINT8 | Custom3PowerLimit1Time
Offset 0x07B4 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. More...
UINT8 | Custom3TurboActivationRatio
Offset 0x07B5 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. More...
UINT8 | Custom3ConfigTdpControl
Offset 0x07B6 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
UINT8 | ConfigTdpLock
Offset 0x07B7 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS.
UINT8 | ConfigTdpBios
Offset 0x07B8 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. More...
UINT8 | PsysPowerLimit1
Offset 0x07B9 - PL1 Enable value PL1 Enable value to limit average platform power. More...
UINT8 | PsysPowerLimit1Time
Offset 0x07BA - PL1 timewindow PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128.
UINT8 | PsysPowerLimit2
Offset 0x07BB - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power. More...
UINT8 | UnusedUpdSpace23 [2]
Offset 0x07BC.
UINT8 | MlcStreamerPrefetcher
Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. More...
UINT8 | MlcSpatialPrefetcher
Offset 0x07BF - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS.
UINT8 | MonitorMwaitEnable
Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. More...
UINT8 | MachineCheckEnable
Offset 0x07C1 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. More...
UINT8 | DebugInterfaceEnable
Offset 0x07C2 - Enable or Disable processor debug features Enable or Disable processor debug features; 0: Disable; 1: Enable. More...
UINT8 | DebugInterfaceLockEnable
Offset 0x07C3 - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable. More...
UINT8 | ApIdleManner
Offset 0x07C4 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. More...
UINT8 | ApHandoffManner
Offset 0x07C5 - Settings for AP Handoff to OS Settings for AP Handoff to OS; 1: HALT loop; 2: MWAIT loop. More...
UINT8 | UnusedUpdSpace24 [2]
Offset 0x07C6.
UINT8 | ProcTraceOutputScheme
Offset 0x07C8 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. More...
UINT8 | ProcTraceEnable
Offset 0x07C9 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. More...
UINT8 | ProcTraceMemSize
Offset 0x07CA - Memory region allocation for Processor Trace Memory region allocation for Processor Trace, Total Memory required is up to requested value * 2 (for memory alignment) * 8 active threads, to enable Processor Trace, PcdFspReservedMemoryLength must be increased by the total memory required, and PlatformMemorySize policy must also be increased by the total memory required over 32MB, Valid Values are 0 - 4KB , 0x1 - 8KB , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB , 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE - 64MB , 0xF - 128MB , 0xFF: Disable.
UINT8 | UnusedUpdSpace25
Offset 0x07CB.
UINT8 | VoltageOptimization
Offset 0x07CC - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable $EN_DIS.
UINT8 | Eist
Offset 0x07CD - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. More...
UINT8 | EnergyEfficientPState
Offset 0x07CE - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. More...
UINT8 | EnergyEfficientTurbo
Offset 0x07CF - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. More...
UINT8 | TStates
Offset 0x07D0 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. More...
UINT8 | BiProcHot
Offset 0x07D1 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS.
UINT8 | DisableProcHotOut
Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. More...
UINT8 | ProcHotResponse
Offset 0x07D3 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. More...
UINT8 | DisableVrThermalAlert
Offset 0x07D4 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. More...
UINT8 | AutoThermalReporting
Offset 0x07D5 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. More...
UINT8 | ThermalMonitor
Offset 0x07D6 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS.
UINT8 | Cx
Offset 0x07D7 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). More...
UINT8 | PmgCstCfgCtrlLock
Offset 0x07D8 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. More...
UINT8 | C1e
Offset 0x07D9 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. More...
UINT8 | PkgCStateDemotion
Offset 0x07DA - Enable or Disable Package C-State Demotion Enable or Disable Package C-State Demotion. More...
UINT8 | PkgCStateUnDemotion
Offset 0x07DB - Enable or Disable Package C-State UnDemotion Enable or Disable Package C-State UnDemotion. More...
UINT8 | CStatePreWake
Offset 0x07DC - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. More...
UINT8 | TimedMwait
Offset 0x07DD - Enable or Disable TimedMwait Support. More...
UINT8 | CstCfgCtrIoMwaitRedirection
Offset 0x07DE - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. More...
UINT8 | PkgCStateLimit
Offset 0x07DF - Set the Max Pkg Cstate Set the Max Pkg Cstate. More...
UINT8 | CstateLatencyControl0TimeUnit
Offset 0x07E0 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl1TimeUnit
Offset 0x07E1 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl2TimeUnit
Offset 0x07E2 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl3TimeUnit
Offset 0x07E3 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl4TimeUnit
Offset 0x07E4 - TimeUnit for C-State Latency Control4 TimeUnit for C-State Latency Control4;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl5TimeUnit
Offset 0x07E5 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | PpmIrmSetting
Offset 0x07E6 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
UINT8 | ProcHotLock
Offset 0x07E7 - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS.
UINT8 | ConfigTdpLevel
Offset 0x07E8 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up; 0xFF: Deactivate 0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate.
UINT8 | RaceToHalt
Offset 0x07E9 - Race To Halt Enable/Disable Race To Halt feature. More...
UINT16 | MaxRatio
Offset 0x07EA - Max P-State Ratio Max P-State Ratio , Valid Range 0 to 0x7F.
UINT16 | StateRatio [40]
Offset 0x07EC - Maximum P-state ratio to use in the custom P-state table Maximum P-state ratio to use in the custom P-state table. More...
UINT16 | CstateLatencyControl0Irtl
Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF, Default is 0x4E, Server Platform is 0x4B.
UINT16 | CstateLatencyControl1Irtl
Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF, Default is 0x76, Server Platform is 0x6B.
UINT16 | CstateLatencyControl2Irtl
Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl3Irtl
Offset 0x0842 - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl4Irtl
Offset 0x0844 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl5Irtl
Offset 0x0846 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
UINT32 | PowerLimit1
Offset 0x0848 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. More...
UINT32 | PowerLimit2Power
Offset 0x084C - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. More...
UINT32 | PowerLimit3
Offset 0x0850 - Package PL3 power limit Package PL3 power limit. More...
UINT32 | PowerLimit4
Offset 0x0854 - Package PL4 power limit Package PL4 power limit. More...
UINT32 | TccOffsetTimeWindowForRatl
Offset 0x0858 - Tcc Offset Time Window for RATL Package PL4 power limit. More...
UINT32 | Custom1PowerLimit1
Offset 0x085C - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. More...
UINT32 | Custom1PowerLimit2
Offset 0x0860 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. More...
UINT32 | Custom2PowerLimit1
Offset 0x0864 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. More...
UINT32 | Custom2PowerLimit2
Offset 0x0868 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. More...
UINT32 | Custom3PowerLimit1
Offset 0x086C - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. More...
UINT32 | Custom3PowerLimit2
Offset 0x0870 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. More...
UINT32 | PsysPowerLimit1Power
Offset 0x0874 - Platform PL1 power Platform PL1 power. More...
UINT32 | PsysPowerLimit2Power
Offset 0x0878 - Platform PL2 power Platform PL2 power. More...
UINT16 | PsysPmax
Offset 0x087C - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. More...
UINT16 | CpuS3ResumeDataSize
Offset 0x087E - CpuS3ResumeDataSize Size of CPU S3 Resume Data.
UINT32 | CpuS3ResumeData
Offset 0x0880 - CpuS3ResumeData Pointer to CPU S3 Resume Data.
UINT8 | FiveCoreRatioLimit
Offset 0x0884 - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | SixCoreRatioLimit
Offset 0x0885 - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | SevenCoreRatioLimit
Offset 0x0886 - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | EightCoreRatioLimit
Offset 0x0887 - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. More...
UINT8 | ThreeStrikeCounterDisable
Offset 0x0888 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. More...
UINT8 | ReservedCpuPostMemTest [1]
Offset 0x0889 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS.
UINT8 | SgxSinitDataFromTpm
Offset 0x088A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values.
UINT8 | EndOfPostMessage
Offset 0x088B - End of Post message Test, Send End of Post message. More...
UINT8 | DisableD0I3SettingForHeci
Offset 0x088C - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS.
UINT8 | PchLockDownGlobalSmi
Offset 0x088D - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. More...
UINT16 | PchHdaResetWaitTimer
Offset 0x088E - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds. More...
UINT8 | PchLockDownBiosInterface
Offset 0x0890 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. More...
UINT8 | PchLockDownRtcLock
Offset 0x0891 - RTC CMOS RAM LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. More...
UINT8 | PchSbiUnlock
Offset 0x0892 - PCH Sbi lock bit This unlock the SBI lock bit to allow SBI after post time. More...
UINT8 | PchSbAccessUnlock
Offset 0x0893 - PCH Psf lock bit The PSF registers will be locked before 3rd party code execution. More...
UINT16 | PcieRpLtrMaxSnoopLatency [24]
Offset 0x0894 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency.
UINT16 | PcieRpLtrMaxNoSnoopLatency [24]
Offset 0x08C4 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency.
UINT8 | PcieRpSnoopLatencyOverrideMode [24]
Offset 0x08F4 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode.
UINT8 | PcieRpSnoopLatencyOverrideMultiplier [24]
Offset 0x090C - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier.
UINT16 | PcieRpSnoopLatencyOverrideValue [24]
Offset 0x0924 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value.
UINT8 | PcieRpNonSnoopLatencyOverrideMode [24]
Offset 0x0954 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
UINT8 | PcieRpNonSnoopLatencyOverrideMultiplier [24]
Offset 0x096C - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
UINT16 | PcieRpNonSnoopLatencyOverrideValue [24]
Offset 0x0984 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value.
UINT8 | PcieRpSlotPowerLimitScale [24]
Offset 0x09B4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. More...
UINT16 | PcieRpSlotPowerLimitValue [24]
Offset 0x09CC - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. More...
UINT8 | PcieRpUptp [24]
Offset 0x09FC - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. More...
UINT8 | PcieRpDptp [24]
Offset 0x0A14 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. More...
UINT8 | PcieEnablePort8xhDecode
Offset 0x0A2C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. More...
UINT8 | PchPciePort8xhDecodePortIndex
Offset 0x0A2D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
UINT8 | PchPmDisableEnergyReport
Offset 0x0A2E - PCH Pm Disable Energy Report Disable/Enable PCH to CPU enery report feature. More...
UINT8 | PchPmPmcReadDisable
Offset 0x0A2F - PCH Pm Pmc Read Disable Deprecated $EN_DIS.
UINT8 | SataTestMode
Offset 0x0A30 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. More...
UINT8 | ReservedFspsTestUpd [15]
Offset 0x0A31.

Detailed Description

Fsp S Test Configuration.

Definition at line 2096 of file FspsUpd.h.

Member Data Documentation

UINT8 FSP_S_TEST_CONFIG::ApHandoffManner

Offset 0x07C5 - Settings for AP Handoff to OS Settings for AP Handoff to OS; 1: HALT loop; 2: MWAIT loop.

1:HALT loop, 2:MWAIT loop

Definition at line 2424 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ApIdleManner

Offset 0x07C4 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop.

1:HALT loop, 2:MWAIT loop, 3:RUN loop

Definition at line 2418 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::AutoThermalReporting

Offset 0x07D5 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2517 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C1e

Offset 0x07D9 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states.

0: Disable; 1: Enable $EN_DIS

Definition at line 2541 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ConfigTdpBios

Offset 0x07B8 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2353 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CStatePreWake

Offset 0x07DC - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake.

0: Disable; 1: Enable $EN_DIS

Definition at line 2561 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CstCfgCtrIoMwaitRedirection

Offset 0x07DE - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2573 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1ConfigTdpControl

Offset 0x07B0 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2311 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom1PowerLimit1

Offset 0x085C - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2723 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1PowerLimit1Time

Offset 0x07AE - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1.

Valid Range 0 to 128

Definition at line 2301 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom1PowerLimit2

Offset 0x0860 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2729 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1TurboActivationRatio

Offset 0x07AF - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1.

Valid Range 0 to 255

Definition at line 2306 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2ConfigTdpControl

Offset 0x07B3 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2326 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom2PowerLimit1

Offset 0x0864 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2735 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2PowerLimit1Time

Offset 0x07B1 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2.

Valid Range 0 to 128

Definition at line 2316 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom2PowerLimit2

Offset 0x0868 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2741 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2TurboActivationRatio

Offset 0x07B2 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2.

Valid Range 0 to 255

Definition at line 2321 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3ConfigTdpControl

Offset 0x07B6 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2341 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom3PowerLimit1

Offset 0x086C - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2747 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3PowerLimit1Time

Offset 0x07B4 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3.

Valid Range 0 to 128

Definition at line 2331 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom3PowerLimit2

Offset 0x0870 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2753 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3TurboActivationRatio

Offset 0x07B5 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3.

Valid Range 0 to 255

Definition at line 2336 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Cx

Offset 0x07D7 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states).

0: Disable; 1: Enable $EN_DIS

Definition at line 2529 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DebugInterfaceEnable

Offset 0x07C2 - Enable or Disable processor debug features Enable or Disable processor debug features; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2406 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DebugInterfaceLockEnable

Offset 0x07C3 - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2412 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DisableProcHotOut

Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2499 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DisableVrThermalAlert

Offset 0x07D4 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2511 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EightCoreRatioLimit

Offset 0x0887 - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2805 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Eist

Offset 0x07CD - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology.

0: Disable; 1: Enable $EN_DIS

Definition at line 2467 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EndOfPostMessage

Offset 0x088B - End of Post message Test, Send End of Post message.

Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved

Definition at line 2830 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnergyEfficientPState

Offset 0x07CE - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode.

Disable; 1: Enable $EN_DIS

Definition at line 2474 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnergyEfficientTurbo

Offset 0x07CF - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode.

Disable; 1: Enable $EN_DIS

Definition at line 2481 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::FiveCoreRatioLimit

Offset 0x0884 - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2787 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::FourCoreRatioLimit

Offset 0x079F - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2209 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::HdcControl

Offset 0x07A2 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration.

0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS

Definition at line 2226 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Hwp

Offset 0x07A1 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support.

0: Disable; 1: Enable; 2-3:Reserved $EN_DIS

Definition at line 2220 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MachineCheckEnable

Offset 0x07C1 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2400 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MlcStreamerPrefetcher

Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2382 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MonitorMwaitEnable

Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2394 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::NumberOfEntries

Offset 0x07AD - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states.

At least 2 states must be present

Definition at line 2296 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::OneCoreRatioLimit

Offset 0x079C - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255

Definition at line 2191 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PchHdaResetWaitTimer

Offset 0x088E - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds.

Default is 600.

Definition at line 2848 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchLockDownBiosInterface

Offset 0x0890 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.

$EN_DIS

Definition at line 2854 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchLockDownGlobalSmi

Offset 0x088D - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.

$EN_DIS

Definition at line 2843 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchLockDownRtcLock

Offset 0x0891 - RTC CMOS RAM LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM.

$EN_DIS

Definition at line 2861 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchPmDisableEnergyReport

Offset 0x0A2E - PCH Pm Disable Energy Report Disable/Enable PCH to CPU enery report feature.

$EN_DIS

Definition at line 2951 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchSbAccessUnlock

Offset 0x0893 - PCH Psf lock bit The PSF registers will be locked before 3rd party code execution.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2873 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchSbiUnlock

Offset 0x0892 - PCH Sbi lock bit This unlock the SBI lock bit to allow SBI after post time.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2867 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieEnablePort8xhDecode

Offset 0x0A2C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2940 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpDptp[24]

Offset 0x0A14 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization.

Used for all lanes. Default is 7.

Definition at line 2933 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpSlotPowerLimitScale[24]

Offset 0x09B4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value.

Leave as 0 to set to default.

Definition at line 2918 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PcieRpSlotPowerLimitValue[24]

Offset 0x09CC - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot.

Leave as 0 to set to default.

Definition at line 2923 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpUptp[24]

Offset 0x09FC - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization.

Used for all lanes. Default is 5.

Definition at line 2928 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateDemotion

Offset 0x07DA - Enable or Disable Package C-State Demotion Enable or Disable Package C-State Demotion.

0: Disable; 1: Enable; 2: Auto (Auto: Enabled for Skylake; Disabled for Kabylake) 0:Disable, 1:Enable, 2:Auto

Definition at line 2548 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateLimit

Offset 0x07DF - Set the Max Pkg Cstate Set the Max Pkg Cstate.

Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto

Definition at line 2580 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateUnDemotion

Offset 0x07DB - Enable or Disable Package C-State UnDemotion Enable or Disable Package C-State UnDemotion.

0: Disable; 1: Enable; 2: Auto (Auto: Enabled for Skylake; Disabled for Kabylake) 0:Disable, 1:Enable, 2:Auto

Definition at line 2555 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PmgCstCfgCtrlLock

Offset 0x07D8 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2535 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit1

Offset 0x0848 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125

Definition at line 2693 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PowerLimit1Time

Offset 0x07A3 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds.

Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128

Definition at line 2232 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PowerLimit2

Offset 0x07A4 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode.

0 : Disable; 1: Enable $EN_DIS

Definition at line 2238 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit2Power

Offset 0x084C - Package Short duration turbo mode power limit Package Short duration turbo mode power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2699 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit3

Offset 0x0850 - Package PL3 power limit Package PL3 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2705 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PowerLimit3Time

Offset 0x07A6 - Package PL3 time window Package PL3 time window range for this policy in milliseconds.

Valid values are 0, 3 to 8, 10, 12, 14, 16, 20 , 24, 28, 32, 40, 48, 55, 56, 64

Definition at line 2250 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit4

Offset 0x0854 - Package PL4 power limit Package PL4 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2711 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcHotResponse

Offset 0x07D3 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2505 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcTraceEnable

Offset 0x07C9 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2440 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcTraceOutputScheme

Offset 0x07C8 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.

0:Single Range Output, 1:ToPA Output

Definition at line 2434 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PsysPmax

Offset 0x087C - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax.

0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W

Definition at line 2771 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit1

Offset 0x07B9 - PL1 Enable value PL1 Enable value to limit average platform power.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2359 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PsysPowerLimit1Power

Offset 0x0874 - Platform PL1 power Platform PL1 power.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2759 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit2

Offset 0x07BB - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2372 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PsysPowerLimit2Power

Offset 0x0878 - Platform PL2 power Platform PL2 power.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2765 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::RaceToHalt

Offset 0x07E9 - Race To Halt Enable/Disable Race To Halt feature.

RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable $EN_DIS

Definition at line 2643 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SataTestMode

Offset 0x0A30 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes.

$EN_DIS

Definition at line 2963 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SevenCoreRatioLimit

Offset 0x0886 - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2799 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SixCoreRatioLimit

Offset 0x0885 - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2793 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::StateRatio[40]

Offset 0x07EC - Maximum P-state ratio to use in the custom P-state table Maximum P-state ratio to use in the custom P-state table.

NumOfCustomPStates has valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates) , StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F

Definition at line 2655 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccActivationOffset

Offset 0x07AA - TCC Activation Offset TCC Activation Offset.

Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is 10, For all other SKUs the recommended default are 0

Definition at line 2275 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccOffsetClamp

Offset 0x07AB - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled.

$EN_DIS

Definition at line 2283 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccOffsetLock

Offset 0x07AC - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled.

$EN_DIS

Definition at line 2290 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::TccOffsetTimeWindowForRatl

Offset 0x0858 - Tcc Offset Time Window for RATL Package PL4 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2717 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ThreeCoreRatioLimit

Offset 0x079E - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2203 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ThreeStrikeCounterDisable

Offset 0x0888 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True.

0: False, 1: True

Definition at line 2812 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TimedMwait

Offset 0x07DD - Enable or Disable TimedMwait Support.

Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS

Definition at line 2567 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TStates

Offset 0x07D0 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2487 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TwoCoreRatioLimit

Offset 0x079D - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255.

This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2197 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_S_TEST_CONFIG Member List

This is the complete list of members for FSP_S_TEST_CONFIG, including all inherited members.

ApHandoffManner | FSP_S_TEST_CONFIG
ApIdleManner | FSP_S_TEST_CONFIG
AutoThermalReporting | FSP_S_TEST_CONFIG
BiProcHot | FSP_S_TEST_CONFIG
C1e | FSP_S_TEST_CONFIG
CdynmaxClampEnable | FSP_S_TEST_CONFIG
ChapDeviceEnable | FSP_S_TEST_CONFIG
ConfigTdpBios | FSP_S_TEST_CONFIG
ConfigTdpLevel | FSP_S_TEST_CONFIG
ConfigTdpLock | FSP_S_TEST_CONFIG
CpuS3ResumeData | FSP_S_TEST_CONFIG
CpuS3ResumeDataSize | FSP_S_TEST_CONFIG
CstateLatencyControl0Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl0TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl1Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl1TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl2Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl2TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl3Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl3TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl4Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl4TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl5Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl5TimeUnit | FSP_S_TEST_CONFIG
CStatePreWake | FSP_S_TEST_CONFIG
CstCfgCtrIoMwaitRedirection | FSP_S_TEST_CONFIG
Custom1ConfigTdpControl | FSP_S_TEST_CONFIG
Custom1PowerLimit1 | FSP_S_TEST_CONFIG
Custom1PowerLimit1Time | FSP_S_TEST_CONFIG
Custom1PowerLimit2 | FSP_S_TEST_CONFIG
Custom1TurboActivationRatio | FSP_S_TEST_CONFIG
Custom2ConfigTdpControl | FSP_S_TEST_CONFIG
Custom2PowerLimit1 | FSP_S_TEST_CONFIG
Custom2PowerLimit1Time | FSP_S_TEST_CONFIG
Custom2PowerLimit2 | FSP_S_TEST_CONFIG
Custom2TurboActivationRatio | FSP_S_TEST_CONFIG
Custom3ConfigTdpControl | FSP_S_TEST_CONFIG
Custom3PowerLimit1 | FSP_S_TEST_CONFIG
Custom3PowerLimit1Time | FSP_S_TEST_CONFIG
Custom3PowerLimit2 | FSP_S_TEST_CONFIG
Custom3TurboActivationRatio | FSP_S_TEST_CONFIG
Cx | FSP_S_TEST_CONFIG
DebugInterfaceEnable | FSP_S_TEST_CONFIG
DebugInterfaceLockEnable | FSP_S_TEST_CONFIG
DisableD0I3SettingForHeci | FSP_S_TEST_CONFIG
DisableProcHotOut | FSP_S_TEST_CONFIG
DisableVrThermalAlert | FSP_S_TEST_CONFIG
DmiExtSync | FSP_S_TEST_CONFIG
DmiIot | FSP_S_TEST_CONFIG
EdramTestMode | FSP_S_TEST_CONFIG
EightCoreRatioLimit | FSP_S_TEST_CONFIG
Eist | FSP_S_TEST_CONFIG
EndOfPostMessage | FSP_S_TEST_CONFIG
EnergyEfficientPState | FSP_S_TEST_CONFIG
EnergyEfficientTurbo | FSP_S_TEST_CONFIG
FiveCoreRatioLimit | FSP_S_TEST_CONFIG
FourCoreRatioLimit | FSP_S_TEST_CONFIG
GtFreqMax | FSP_S_TEST_CONFIG
HdcControl | FSP_S_TEST_CONFIG
Hwp | FSP_S_TEST_CONFIG
MachineCheckEnable | FSP_S_TEST_CONFIG
MaxRatio | FSP_S_TEST_CONFIG
MlcSpatialPrefetcher | FSP_S_TEST_CONFIG
MlcStreamerPrefetcher | FSP_S_TEST_CONFIG
MonitorMwaitEnable | FSP_S_TEST_CONFIG
NumberOfEntries | FSP_S_TEST_CONFIG
OneCoreRatioLimit | FSP_S_TEST_CONFIG
PchHdaResetWaitTimer | FSP_S_TEST_CONFIG
PchLockDownBiosInterface | FSP_S_TEST_CONFIG
PchLockDownGlobalSmi | FSP_S_TEST_CONFIG
PchLockDownRtcLock | FSP_S_TEST_CONFIG
PchPciePort8xhDecodePortIndex | FSP_S_TEST_CONFIG
PchPmDisableEnergyReport | FSP_S_TEST_CONFIG
PchPmPmcReadDisable | FSP_S_TEST_CONFIG
PchSbAccessUnlock | FSP_S_TEST_CONFIG
PchSbiUnlock | FSP_S_TEST_CONFIG
PcieEnablePort8xhDecode | FSP_S_TEST_CONFIG
PcieRpDptp | FSP_S_TEST_CONFIG
PcieRpLtrMaxNoSnoopLatency | FSP_S_TEST_CONFIG
PcieRpLtrMaxSnoopLatency | FSP_S_TEST_CONFIG
PcieRpNonSnoopLatencyOverrideMode | FSP_S_TEST_CONFIG
PcieRpNonSnoopLatencyOverrideMultiplier | FSP_S_TEST_CONFIG
PcieRpNonSnoopLatencyOverrideValue | FSP_S_TEST_CONFIG
PcieRpSlotPowerLimitScale | FSP_S_TEST_CONFIG
PcieRpSlotPowerLimitValue | FSP_S_TEST_CONFIG
PcieRpSnoopLatencyOverrideMode | FSP_S_TEST_CONFIG
PcieRpSnoopLatencyOverrideMultiplier | FSP_S_TEST_CONFIG
PcieRpSnoopLatencyOverrideValue | FSP_S_TEST_CONFIG
PcieRpUptp | FSP_S_TEST_CONFIG
PegMaxPayload | FSP_S_TEST_CONFIG
PkgCStateDemotion | FSP_S_TEST_CONFIG
PkgCStateLimit | FSP_S_TEST_CONFIG
PkgCStateUnDemotion | FSP_S_TEST_CONFIG
PmgCstCfgCtrlLock | FSP_S_TEST_CONFIG
PmSupport | FSP_S_TEST_CONFIG
PowerLimit1 | FSP_S_TEST_CONFIG
PowerLimit1Time | FSP_S_TEST_CONFIG
PowerLimit2 | FSP_S_TEST_CONFIG
PowerLimit2Power | FSP_S_TEST_CONFIG
PowerLimit3 | FSP_S_TEST_CONFIG
PowerLimit3DutyCycle | FSP_S_TEST_CONFIG
PowerLimit3Lock | FSP_S_TEST_CONFIG
PowerLimit3Time | FSP_S_TEST_CONFIG
PowerLimit4 | FSP_S_TEST_CONFIG
PowerLimit4Lock | FSP_S_TEST_CONFIG
PpmIrmSetting | FSP_S_TEST_CONFIG
ProcHotLock | FSP_S_TEST_CONFIG
ProcHotResponse | FSP_S_TEST_CONFIG
ProcTraceEnable | FSP_S_TEST_CONFIG
ProcTraceMemSize | FSP_S_TEST_CONFIG
ProcTraceOutputScheme | FSP_S_TEST_CONFIG
PsysPmax | FSP_S_TEST_CONFIG
PsysPowerLimit1 | FSP_S_TEST_CONFIG
PsysPowerLimit1Power | FSP_S_TEST_CONFIG
PsysPowerLimit1Time | FSP_S_TEST_CONFIG
PsysPowerLimit2 | FSP_S_TEST_CONFIG
PsysPowerLimit2Power | FSP_S_TEST_CONFIG
RaceToHalt | FSP_S_TEST_CONFIG
RenderStandby | FSP_S_TEST_CONFIG
ReservedCpuPostMemTest | FSP_S_TEST_CONFIG
ReservedFspsTestUpd | FSP_S_TEST_CONFIG
SaPostMemTestRsvd | FSP_S_TEST_CONFIG
SataTestMode | FSP_S_TEST_CONFIG
SevenCoreRatioLimit | FSP_S_TEST_CONFIG
SgxSinitDataFromTpm | FSP_S_TEST_CONFIG
Signature | FSP_S_TEST_CONFIG
SixCoreRatioLimit | FSP_S_TEST_CONFIG
SkipPamLock | FSP_S_TEST_CONFIG
StateRatio | FSP_S_TEST_CONFIG
TccActivationOffset | FSP_S_TEST_CONFIG
TccOffsetClamp | FSP_S_TEST_CONFIG
TccOffsetLock | FSP_S_TEST_CONFIG
TccOffsetTimeWindowForRatl | FSP_S_TEST_CONFIG
ThermalMonitor | FSP_S_TEST_CONFIG
ThreeCoreRatioLimit | FSP_S_TEST_CONFIG
ThreeStrikeCounterDisable | FSP_S_TEST_CONFIG
TimedMwait | FSP_S_TEST_CONFIG
TStates | FSP_S_TEST_CONFIG
TurboPowerLimitLock | FSP_S_TEST_CONFIG
TwoCoreRatioLimit | FSP_S_TEST_CONFIG
UnusedUpdSpace22 | FSP_S_TEST_CONFIG
UnusedUpdSpace23 | FSP_S_TEST_CONFIG
UnusedUpdSpace24 | FSP_S_TEST_CONFIG
UnusedUpdSpace25 | FSP_S_TEST_CONFIG
VoltageOptimization | FSP_S_TEST_CONFIG
VtdDisable | FSP_S_TEST_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_T_CONFIG Struct Reference

Public Attributes | List of all members
FSP_T_CONFIG Struct Reference

Fsp T Configuration. More...

#include <FsptUpd.h>

Public Attributes

UINT8 | PcdSerialIoUartDebugEnable
Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. More...
UINT8 | PcdSerialIoUartNumber
Offset 0x0041 - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug. More...
UINT8 | UnusedUpdSpace0 [2]
Offset 0x0042.
UINT32 | PcdSerialIoUartInputClock
Offset 0x0044.
UINT64 | PcdPciExpressBaseAddress
Offset 0x0048 - Pci Express Base Address Base address to be programmed for Pci Express.
UINT32 | PcdPciExpressRegionLength
Offset 0x0050 - Pci Express Region Length Region Length to be programmed for Pci Express.
UINT8 | ReservedFsptUpd1 [12]
Offset 0x0054.

Detailed Description

Fsp T Configuration.

Definition at line 69 of file FsptUpd.h.

Member Data Documentation

UINT8 FSP_T_CONFIG::PcdSerialIoUartDebugEnable

Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.

0:Disable, 1:Enable and Initialize, 2:Enable without Initializing

Definition at line 75 of file FsptUpd.h.

UINT8 FSP_T_CONFIG::PcdSerialIoUartNumber

Offset 0x0041 - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug.

0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2

Definition at line 81 of file FsptUpd.h.

The documentation for this struct was generated from the following file:
  • FsptUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_T_CONFIG Member List

This is the complete list of members for FSP_T_CONFIG, including all inherited members.

PcdPciExpressBaseAddress | FSP_T_CONFIG
PcdPciExpressRegionLength | FSP_T_CONFIG
PcdSerialIoUartDebugEnable | FSP_T_CONFIG
PcdSerialIoUartInputClock | FSP_T_CONFIG
PcdSerialIoUartNumber | FSP_T_CONFIG
ReservedFsptUpd1 | FSP_T_CONFIG
UnusedUpdSpace0 | FSP_T_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPM_UPD Struct Reference

Public Attributes | List of all members
FSPM_UPD Struct Reference

Fsp M UPD Configuration. More...

#include <FspmUpd.h>

Collaboration diagram for FSPM_UPD:
[legend]

Public Attributes

FSP_UPD_HEADER | FspUpdHeader
Offset 0x0000.
FSPM_ARCH_UPD | FspmArchUpd
Offset 0x0020.
FSP_M_CONFIG FspmConfig
Offset 0x0040.
FSP_M_TEST_CONFIG FspmTestConfig
Offset 0x0520.
UINT8 | UnusedUpdSpace10 [134]
Offset 0x05C0.
UINT16 | UpdTerminator
Offset 0x0646.

Detailed Description

Fsp M UPD Configuration.

Definition at line 1685 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPM_UPD Member List

This is the complete list of members for FSPM_UPD, including all inherited members.

FspmArchUpd | FSPM_UPD
FspmConfig | FSPM_UPD
FspmTestConfig | FSPM_UPD
FspUpdHeader | FSPM_UPD
UnusedUpdSpace10 | FSPM_UPD
UpdTerminator | FSPM_UPD


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPS_UPD Struct Reference

Public Attributes | List of all members
FSPS_UPD Struct Reference

Fsp S UPD Configuration. More...

#include <FspsUpd.h>

Collaboration diagram for FSPS_UPD:
[legend]

Public Attributes

FSP_UPD_HEADER | FspUpdHeader
Offset 0x0000.
FSP_S_CONFIG FspsConfig
Offset 0x0020.
FSP_S_TEST_CONFIG FspsTestConfig
Offset 0x0780.
UINT8 | UnusedUpdSpace26 [470]
Offset 0x0A40.
UINT16 | UpdTerminator
Offset 0x0C16.

Detailed Description

Fsp S UPD Configuration.

Definition at line 2972 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPS_UPD Member List

This is the complete list of members for FSPS_UPD, including all inherited members.

FspsConfig | FSPS_UPD
FspsTestConfig | FSPS_UPD
FspUpdHeader | FSPS_UPD
UnusedUpdSpace26 | FSPS_UPD
UpdTerminator | FSPS_UPD


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPT_CORE_UPD Struct Reference

Public Attributes | List of all members
FSPT_CORE_UPD Struct Reference

Fsp T Core UPD. More...

#include <FsptUpd.h>

Public Attributes

UINT32 | MicrocodeRegionBase
Offset 0x0020.
UINT32 | MicrocodeRegionSize
Offset 0x0024.
UINT32 | CodeRegionBase
Offset 0x0028.
UINT32 | CodeRegionSize
Offset 0x002C.
UINT8 | Reserved [16]
Offset 0x0030.

Detailed Description

Fsp T Core UPD.

Definition at line 44 of file FsptUpd.h.

The documentation for this struct was generated from the following file:
  • FsptUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPT_CORE_UPD Member List

This is the complete list of members for FSPT_CORE_UPD, including all inherited members.

CodeRegionBase | FSPT_CORE_UPD
CodeRegionSize | FSPT_CORE_UPD
MicrocodeRegionBase | FSPT_CORE_UPD
MicrocodeRegionSize | FSPT_CORE_UPD
Reserved | FSPT_CORE_UPD


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPT_UPD Struct Reference

Public Attributes | List of all members
FSPT_UPD Struct Reference

Fsp T UPD Configuration. More...

#include <FsptUpd.h>

Collaboration diagram for FSPT_UPD:
[legend]

Public Attributes

FSP_UPD_HEADER | FspUpdHeader
Offset 0x0000.
FSPT_CORE_UPD FsptCoreUpd
Offset 0x0020.
FSP_T_CONFIG FsptConfig
Offset 0x0040.
UINT8 | UnusedUpdSpace1 [6]
Offset 0x0060.
UINT16 | UpdTerminator
Offset 0x0066.

Detailed Description

Fsp T UPD Configuration.

Definition at line 108 of file FsptUpd.h.

The documentation for this struct was generated from the following file:
  • FsptUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPT_UPD Member List

This is the complete list of members for FSPT_UPD, including all inherited members.

FsptConfig | FSPT_UPD
FsptCoreUpd | FSPT_UPD
FspUpdHeader | FSPT_UPD
UnusedUpdSpace1 | FSPT_UPD
UpdTerminator | FSPT_UPD


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: GPIO_CONFIG Struct Reference

Public Attributes | List of all members
GPIO_CONFIG Struct Reference

GPIO configuration structure used for pin programming. More...

#include <GpioConfig.h>

Public Attributes

UINT32 | PadMode: 5
Pad Mode Pad can be set as GPIO or one of its native functions. More...
UINT32 | HostSoftPadOwn: 2
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode. More...
UINT32 | Direction: 6
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. More...
UINT32 | OutputState: 2
Output State Set Pad output value. More...
UINT32 | InterruptConfig: 9
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). More...
UINT32 | PowerConfig: 8
GPIO Power Configuration. More...
UINT32 | ElectricalConfig: 9
GPIO Electrical Configuration This setting controls pads termination and voltage tolerance. More...
UINT32 | LockConfig: 4
GPIO Lock Configuration This setting controls pads lock. More...
UINT32 | OtherSettings: 2
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
UINT32 | RsvdBits: 17
Reserved bits for future extension.

Detailed Description

GPIO configuration structure used for pin programming.

Structure contains fields that can be used to configure pad.

Definition at line 55 of file GpioConfig.h.

Member Data Documentation

UINT32 GPIO_CONFIG::Direction

GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.

Refer to definition of GPIO_DIRECTION for supported settings.

Definition at line 76 of file GpioConfig.h.

UINT32 GPIO_CONFIG::ElectricalConfig

GPIO Electrical Configuration This setting controls pads termination and voltage tolerance.

Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.

Definition at line 102 of file GpioConfig.h.

UINT32 GPIO_CONFIG::HostSoftPadOwn

Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.

Refer to definition of GPIO_HOSTSW_OWN.

Definition at line 70 of file GpioConfig.h.

UINT32 GPIO_CONFIG::InterruptConfig

GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).

This setting is applicable only if GPIO is in GpioMode with input enabled. Refer to definition of GPIO_INT_CONFIG for supported settings.

Definition at line 90 of file GpioConfig.h.

UINT32 GPIO_CONFIG::LockConfig

GPIO Lock Configuration This setting controls pads lock.

Refer to definition of GPIO_LOCK_CONFIG for supported settings.

Definition at line 108 of file GpioConfig.h.

UINT32 GPIO_CONFIG::OutputState

Output State Set Pad output value.

Refer to definition of GPIO_OUTPUT_STATE for supported settings. This setting takes place when output is enabled.

Definition at line 83 of file GpioConfig.h.

UINT32 GPIO_CONFIG::PadMode

Pad Mode Pad can be set as GPIO or one of its native functions.

When in native mode setting Direction (except Inversion), OutputState, InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. Refer to definition of GPIO_PAD_MODE. Refer to EDS for each native mode according to the pad.

Definition at line 64 of file GpioConfig.h.

UINT32 GPIO_CONFIG::PowerConfig

GPIO Power Configuration.

This setting controls Pad Reset Configuration. Refer to definition of GPIO_RESET_CONFIG for supported settings.

Definition at line 96 of file GpioConfig.h.

The documentation for this struct was generated from the following file:
  • GpioConfig.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

GPIO_CONFIG Member List

This is the complete list of members for GPIO_CONFIG, including all inherited members.

Direction | GPIO_CONFIG
ElectricalConfig | GPIO_CONFIG
HostSoftPadOwn | GPIO_CONFIG
InterruptConfig | GPIO_CONFIG
LockConfig | GPIO_CONFIG
OtherSettings | GPIO_CONFIG
OutputState | GPIO_CONFIG
PadMode | GPIO_CONFIG
PowerConfig | GPIO_CONFIG
RsvdBits | GPIO_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: MEMORY_PLATFORM_DATA Struct Reference

List of all members
MEMORY_PLATFORM_DATA Struct Reference

Memory Platform Data Hob. More...

#include <MemInfoHob.h>

Detailed Description

Memory Platform Data Hob.

Revision 1:

  • Initial version. Revision 2:
  • Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields

Definition at line 259 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

MEMORY_PLATFORM_DATA Member List

This is the complete list of members for MEMORY_PLATFORM_DATA, including all inherited members.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: SI_CHIPSET_INIT_INFO Struct Reference

List of all members
SI_CHIPSET_INIT_INFO Struct Reference

The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. More...

#include <FspmUpd.h>

Detailed Description

The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.

Definition at line 47 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SI_CHIPSET_INIT_INFO Member List

This is the complete list of members for SI_CHIPSET_INIT_INFO, including all inherited members.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: SI_PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

Public Attributes | List of all members
SI_PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...

#include <FspsUpd.h>

Public Attributes

UINT8 | Device
Device number.
UINT8 | Function
Device function.
UINT8 | IntX
Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
UINT8 | Irq
IRQ to be set for device.

Detailed Description

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.

Definition at line 76 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SI_PCH_DEVICE_INTERRUPT_CONFIG Member List

This is the complete list of members for SI_PCH_DEVICE_INTERRUPT_CONFIG, including all inherited members.

Device | SI_PCH_DEVICE_INTERRUPT_CONFIG
Function | SI_PCH_DEVICE_INTERRUPT_CONFIG
IntX | SI_PCH_DEVICE_INTERRUPT_CONFIG
Irq | SI_PCH_DEVICE_INTERRUPT_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: SMBIOS_CACHE_INFO Struct Reference

Public Attributes | List of all members
SMBIOS_CACHE_INFO Struct Reference

SMBIOS Cache Info HOB Structure. More...

#include <SmbiosCacheInfoHob.h>

Public Attributes

UINT16 | NumberOfCacheLevels
Based on Number of Cache Types L1/L2/L3.
UINT8 | SocketDesignationStrIndex
String Index in the string Buffer. Example "L1-CACHE".
UINT16 | CacheConfiguration
Format defined in SMBIOS Spec v3.0 Section7.8 Table36.
UINT16 | MaxCacheSize
Format defined in SMBIOS Spec v3.0 Section7.8.1.
UINT16 | InstalledSize
Format defined in SMBIOS Spec v3.0 Section7.8.1.
UINT16 | SupportedSramType
Format defined in SMBIOS Spec v3.0 Section7.8.2.
UINT16 | CurrentSramType
Format defined in SMBIOS Spec v3.0 Section7.8.2.
UINT8 | CacheSpeed
Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 | ErrorCorrectionType
ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3.
UINT8 | SystemCacheType
ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4.
UINT8 | Associativity
ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5.

Detailed Description

SMBIOS Cache Info HOB Structure.

Definition at line 32 of file SmbiosCacheInfoHob.h.

The documentation for this struct was generated from the following file:
  • SmbiosCacheInfoHob.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SMBIOS_CACHE_INFO Member List

This is the complete list of members for SMBIOS_CACHE_INFO, including all inherited members.

Associativity | SMBIOS_CACHE_INFO
CacheConfiguration | SMBIOS_CACHE_INFO
CacheSpeed | SMBIOS_CACHE_INFO
CurrentSramType | SMBIOS_CACHE_INFO
ErrorCorrectionType | SMBIOS_CACHE_INFO
InstalledSize | SMBIOS_CACHE_INFO
MaxCacheSize | SMBIOS_CACHE_INFO
NumberOfCacheLevels | SMBIOS_CACHE_INFO
SocketDesignationStrIndex | SMBIOS_CACHE_INFO
SupportedSramType | SMBIOS_CACHE_INFO
SystemCacheType | SMBIOS_CACHE_INFO


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: SMBIOS_PROCESSOR_INFO Struct Reference

Public Attributes | List of all members
SMBIOS_PROCESSOR_INFO Struct Reference

SMBIOS Processor Info HOB Structure. More...

#include <SmbiosProcessorInfoHob.h>

Public Attributes

UINT8 | ProcessorType
ENUM defined in SMBIOS Spec v3.0 Section 7.5.1.
UINT16 | ProcessorFamily
This info is used for both ProcessorFamily and ProcessorFamily2 fields See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2.
UINT8 | ProcessorManufacturerStrIndex
Index of the String in the String Buffer.
UINT64 | ProcessorId
ENUM defined in SMBIOS Spec v3.0 Section 7.5.3.
UINT8 | ProcessorVersionStrIndex
Index of the String in the String Buffer.
UINT8 | Voltage
Format defined in SMBIOS Spec v3.0 Section 7.5.4.
UINT16 | ExternalClockInMHz
External Clock Frequency. Set to 0 if unknown.
UINT16 | CurrentSpeedInMHz
Snapshot of current processor speed during boot.
UINT8 | Status
Format defined in the SMBIOS Spec v3.0 Table 21.
UINT8 | ProcessorUpgrade
ENUM defined in SMBIOS Spec v3.0 Section 7.5.5.
UINT16 | CoreCount
This info is used for both CoreCount & CoreCount2 fields See detailed description in SMBIOS Spec v3.0 Section 7.5.6.
UINT16 | EnabledCoreCount
This info is used for both CoreEnabled & CoreEnabled2 fields See detailed description in SMBIOS Spec v3.0 Section 7.5.7.
UINT16 | ThreadCount
This info is used for both ThreadCount & ThreadCount2 fields See detailed description in SMBIOS Spec v3.0 Section 7.5.8.
UINT16 | ProcessorCharacteristics
Format defined in SMBIOS Spec v3.0 Section 7.5.9.

Detailed Description

SMBIOS Processor Info HOB Structure.

Definition at line 32 of file SmbiosProcessorInfoHob.h.

The documentation for this struct was generated from the following file:
  • SmbiosProcessorInfoHob.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SMBIOS_PROCESSOR_INFO Member List

This is the complete list of members for SMBIOS_PROCESSOR_INFO, including all inherited members.

CoreCount | SMBIOS_PROCESSOR_INFO
CurrentSpeedInMHz | SMBIOS_PROCESSOR_INFO
EnabledCoreCount | SMBIOS_PROCESSOR_INFO
ExternalClockInMHz | SMBIOS_PROCESSOR_INFO
ProcessorCharacteristics | SMBIOS_PROCESSOR_INFO
ProcessorFamily | SMBIOS_PROCESSOR_INFO
ProcessorId | SMBIOS_PROCESSOR_INFO
ProcessorManufacturerStrIndex | SMBIOS_PROCESSOR_INFO
ProcessorType | SMBIOS_PROCESSOR_INFO
ProcessorUpgrade | SMBIOS_PROCESSOR_INFO
ProcessorVersionStrIndex | SMBIOS_PROCESSOR_INFO
Status | SMBIOS_PROCESSOR_INFO
ThreadCount | SMBIOS_PROCESSOR_INFO
Voltage | SMBIOS_PROCESSOR_INFO


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Index

Class Index
A | D | F | G | M | S
A
F
FSP_T_CONFIG
M
SI_PCH_DEVICE_INTERRUPT_CONFIG
FSPM_UPD SMBIOS_CACHE_INFO
AUDIO_AZALIA_VERB_TABLE FSP_M_CONFIG FSPS_UPD MEMORY_PLATFORM_DATA SMBIOS_PROCESSOR_INFO
AZALIA_HEADER FSP_M_TEST_CONFIG FSPT_CORE_UPD
S
D
FSP_S_CONFIG FSPT_UPD
FSP_S_TEST_CONFIG
G
SI_CHIPSET_INIT_INFO
DIMM_INFO
GPIO_CONFIG
A | D | F | G | M | S


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • AcLoadline : FSP_S_CONFIG
  • AcousticNoiseMitigation : FSP_S_CONFIG
  • ActiveCoreCount : FSP_M_CONFIG
  • AmtEnabled : FSP_S_CONFIG
  • AmtSolEnabled : FSP_S_CONFIG
  • ApertureSize : FSP_M_CONFIG
  • ApHandoffManner : FSP_S_TEST_CONFIG
  • ApIdleManner : FSP_S_TEST_CONFIG
  • AsfEnabled : FSP_S_CONFIG
  • Associativity : SMBIOS_CACHE_INFO
  • AutoThermalReporting : FSP_S_TEST_CONFIG
  • Avx2RatioOffset : FSP_M_CONFIG
  • Avx3RatioOffset : FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- b -

  • BclkAdaptiveVoltage : FSP_M_CONFIG
  • BdatEnable : FSP_M_TEST_CONFIG
  • BgpdtHash : FSP_S_CONFIG
  • BiosAcmBase : FSP_M_TEST_CONFIG
  • BiosAcmSize : FSP_M_TEST_CONFIG
  • BiosGuard : FSP_M_CONFIG
  • BiosGuardAttr : FSP_S_CONFIG
  • BiosGuardModulePtr : FSP_S_CONFIG
  • BiosSize : FSP_M_TEST_CONFIG
  • BiProcHot : FSP_S_TEST_CONFIG
  • BistOnReset : FSP_M_CONFIG
  • BootFrequency : FSP_M_CONFIG
  • BypassPhySyncReset : FSP_M_TEST_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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  • Variables
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Here is a list of all documented class members with links to the class documentation for each member:

- c -

  • C1e : FSP_S_TEST_CONFIG
  • CacheConfiguration : SMBIOS_CACHE_INFO
  • CacheSpeed : SMBIOS_CACHE_INFO
  • CaVrefConfig : FSP_M_CONFIG
  • CdClock : FSP_S_CONFIG
  • CdynmaxClampEnable : FSP_S_TEST_CONFIG
  • ChapDeviceEnable : FSP_S_TEST_CONFIG
  • ChipsetInitMessage : FSP_M_TEST_CONFIG
  • CleanMemory : FSP_M_CONFIG
  • CmdTriStateDis : FSP_M_CONFIG
  • CodeRegionBase : FSPT_CORE_UPD
  • CodeRegionSize : FSPT_CORE_UPD
  • ConfigTdpBios : FSP_S_TEST_CONFIG
  • ConfigTdpLevel : FSP_S_TEST_CONFIG
  • ConfigTdpLock : FSP_S_TEST_CONFIG
  • CoreCount : SMBIOS_PROCESSOR_INFO
  • CoreMaxOcRatio : FSP_M_CONFIG
  • CorePllVoltageOffset : FSP_M_CONFIG
  • CoreVoltageAdaptive : FSP_M_CONFIG
  • CoreVoltageMode : FSP_M_CONFIG
  • CoreVoltageOffset : FSP_M_CONFIG
  • CoreVoltageOverride : FSP_M_CONFIG
  • CpuConfig : FSP_S_CONFIG
  • CpuRatio : FSP_M_CONFIG
  • CpuRatioOverride : FSP_M_CONFIG
  • CpuS3ResumeData : FSP_S_TEST_CONFIG
  • CpuS3ResumeDataSize : FSP_S_TEST_CONFIG
  • CpuS3ResumeMtrrData : FSP_S_CONFIG
  • CpuS3ResumeMtrrDataSize : FSP_S_CONFIG
  • CridEnable : FSP_S_CONFIG
  • CstateLatencyControl0Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl1Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl2Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl3Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl4Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl5Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : FSP_S_TEST_CONFIG
  • CStatePreWake : FSP_S_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : FSP_S_TEST_CONFIG
  • CurrentSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • CurrentSramType : SMBIOS_CACHE_INFO
  • Custom1ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom1PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom1TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom2ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom2PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom2TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom3ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom3PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom3TurboActivationRatio : FSP_S_TEST_CONFIG
  • Cx : FSP_S_TEST_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- d -

  • Data : AUDIO_AZALIA_VERB_TABLE
  • DataDwords : AZALIA_HEADER
  • DcLoadline : FSP_S_CONFIG
  • DdrFreqLimit : FSP_M_CONFIG
  • DebugInterfaceEnable : FSP_S_TEST_CONFIG
  • DebugInterfaceLockEnable : FSP_S_TEST_CONFIG
  • DefaultSid : FSP_S_CONFIG
  • DefaultSvid : FSP_S_CONFIG
  • DelayUsbPdoProgramming : FSP_S_CONFIG
  • Device : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Device4Enable : FSP_S_CONFIG
  • DeviceId : AZALIA_HEADER
  • DevIntConfigPtr : FSP_S_CONFIG
  • DidInitStat : FSP_M_TEST_CONFIG
  • DimmCapacity : DIMM_INFO
  • Direction : GPIO_CONFIG
  • DisableCpuReplacedPolling : FSP_M_TEST_CONFIG
  • DisableD0I3SettingForHeci : FSP_S_TEST_CONFIG
  • DisableHeciRetry : FSP_M_TEST_CONFIG
  • DisableMessageCheck : FSP_M_TEST_CONFIG
  • DisableProcHotOut : FSP_S_TEST_CONFIG
  • DisableVrThermalAlert : FSP_S_TEST_CONFIG
  • DllBwEn0 : FSP_M_CONFIG
  • DllBwEn1 : FSP_M_CONFIG
  • DllBwEn2 : FSP_M_CONFIG
  • DllBwEn3 : FSP_M_CONFIG
  • DmiAspm : FSP_S_CONFIG
  • DmiDeEmphasis : FSP_M_CONFIG
  • DmiExtSync : FSP_S_TEST_CONFIG
  • DmiGen3EndPointHint : FSP_M_CONFIG
  • DmiGen3EndPointPreset : FSP_M_CONFIG
  • DmiGen3EqPh2Enable : FSP_M_TEST_CONFIG
  • DmiGen3EqPh3Method : FSP_M_TEST_CONFIG
  • DmiGen3ProgramStaticEq : FSP_M_CONFIG
  • DmiGen3RootPortPreset : FSP_M_CONFIG
  • DmiGen3RxCtlePeaking : FSP_M_CONFIG
  • DmiIot : FSP_S_TEST_CONFIG
  • DmiMaxLinkSpeed : FSP_M_TEST_CONFIG
  • DmiSuggestedSetting : FSP_S_CONFIG
  • DmiTS0TW : FSP_S_CONFIG
  • DmiTS1TW : FSP_S_CONFIG
  • DmiTS2TW : FSP_S_CONFIG
  • DmiTS3TW : FSP_S_CONFIG
  • DmiVc1 : FSP_M_TEST_CONFIG
  • DmiVcm : FSP_M_TEST_CONFIG
  • DqByteMapCh0 : FSP_M_CONFIG
  • DqByteMapCh1 : FSP_M_CONFIG
  • DqPinsInterleaved : FSP_M_CONFIG
  • DqsMapCpu2DramCh0 : FSP_M_CONFIG
  • DqsMapCpu2DramCh1 : FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- e -

  • Early8254ClockGatingEnable : FSP_S_CONFIG
  • EcCmdLock : FSP_S_CONFIG
  • EcCmdProvisionEav : FSP_S_CONFIG
  • EdramRatio : FSP_M_CONFIG
  • EdramTestMode : FSP_S_TEST_CONFIG
  • EightCoreRatioLimit : FSP_S_TEST_CONFIG
  • Eist : FSP_S_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • EnableC6Dram : FSP_M_CONFIG
  • EnabledCoreCount : SMBIOS_PROCESSOR_INFO
  • EnableSgx : FSP_M_CONFIG
  • EnableTcoTimer : FSP_S_CONFIG
  • EnableTraceHub : FSP_M_CONFIG
  • EndOfPostMessage : FSP_S_TEST_CONFIG
  • EnergyEfficientPState : FSP_S_TEST_CONFIG
  • EnergyEfficientTurbo : FSP_S_TEST_CONFIG
  • ErrorCorrectionType : SMBIOS_CACHE_INFO
  • EsataSpeedLimit : FSP_S_CONFIG
  • EvLoader : FSP_M_CONFIG
  • ExternalClockInMHz : SMBIOS_PROCESSOR_INFO


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- f -

  • FastPkgCRampDisableGt : FSP_S_CONFIG
  • FastPkgCRampDisableIa : FSP_S_CONFIG
  • FastPkgCRampDisableSa : FSP_S_CONFIG
  • FClkFrequency : FSP_M_CONFIG
  • FiveCoreRatioLimit : FSP_S_TEST_CONFIG
  • FlashWearOutProtection : FSP_M_CONFIG
  • FourCoreRatioLimit : FSP_S_TEST_CONFIG
  • FspmArchUpd : FSPM_UPD
  • FspmConfig : FSPM_UPD
  • FspmTestConfig : FSPM_UPD
  • FspsConfig : FSPS_UPD
  • FspsTestConfig : FSPS_UPD
  • FsptConfig : FSPT_UPD
  • FsptCoreUpd : FSPT_UPD
  • FspUpdHeader : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Function : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • FwProgress : FSP_S_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- g -

  • Gen3SwEqAlwaysAttempt : FSP_M_TEST_CONFIG
  • Gen3SwEqEnableVocTest : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterErrorTarget : FSP_M_TEST_CONFIG
  • Gen3SwEqNumberOfPresets : FSP_M_TEST_CONFIG
  • Gen3SwEqVocDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqVocErrorTarget : FSP_M_TEST_CONFIG
  • GmmEnable : FSP_S_CONFIG
  • GpioIrqRoute : FSP_S_CONFIG
  • GraphicsConfigPtr : FSP_S_CONFIG
  • GtFreqMax : FSP_S_TEST_CONFIG
  • GtPllVoltageOffset : FSP_M_CONFIG
  • GtsExtraTurboVoltage : FSP_M_CONFIG
  • GtsMaxOcRatio : FSP_M_CONFIG
  • GtsVoltageMode : FSP_M_CONFIG
  • GtsVoltageOffset : FSP_M_CONFIG
  • GtsVoltageOverride : FSP_M_CONFIG
  • GttMmAdr : FSP_M_CONFIG
  • GttSize : FSP_M_CONFIG
  • GtusExtraTurboVoltage : FSP_M_CONFIG
  • GtusMaxOcRatio : FSP_M_CONFIG
  • GtusVoltageMode : FSP_M_CONFIG
  • GtusVoltageOffset : FSP_M_CONFIG
  • GtusVoltageOverride : FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- h -

  • HdcControl : FSP_S_TEST_CONFIG
  • Header : AUDIO_AZALIA_VERB_TABLE
  • Heci1BarAddress : FSP_M_CONFIG
  • Heci2BarAddress : FSP_M_CONFIG
  • Heci3BarAddress : FSP_M_CONFIG
  • Heci3Enabled : FSP_S_CONFIG
  • HeciCommunication2 : FSP_M_TEST_CONFIG
  • HeciTimeouts : FSP_M_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • Hwp : FSP_S_TEST_CONFIG
  • HyperThreading : FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- i -

  • IccMax : FSP_S_CONFIG
  • IderDeviceEnable : FSP_M_TEST_CONFIG
  • IedSize : FSP_M_CONFIG
  • IgdDvmt50PreAlloc : FSP_M_CONFIG
  • ImonOffset : FSP_S_CONFIG
  • ImonSlope : FSP_S_CONFIG
  • InitPcieAspmAfterOprom : FSP_M_CONFIG
  • InstalledSize : SMBIOS_CACHE_INFO
  • InternalGfx : FSP_M_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • IntX : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Irq : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • IslVrCmd : FSP_S_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- j -

  • JtagC10PowerGateDisable : FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

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  • KtDeviceEnable : FSP_M_TEST_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- l -

  • LockConfig : GPIO_CONFIG
  • LockPTMregs : FSP_M_TEST_CONFIG
  • LogoPtr : FSP_S_CONFIG
  • LogoSize : FSP_S_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- m -

  • MachineCheckEnable : FSP_S_TEST_CONFIG
  • ManageabilityMode : FSP_S_CONFIG
  • MaxCacheSize : SMBIOS_CACHE_INFO
  • MaxRatio : FSP_S_TEST_CONFIG
  • McPllVoltageOffset : FSP_M_CONFIG
  • MemorySpdDataLen : FSP_M_CONFIG
  • MemorySpdPtr00 : FSP_M_CONFIG
  • MemorySpdPtr01 : FSP_M_CONFIG
  • MemorySpdPtr10 : FSP_M_CONFIG
  • MemorySpdPtr11 : FSP_M_CONFIG
  • MeUnconfigIsValid : FSP_S_CONFIG
  • MeUnconfigOnRtcClear : FSP_S_CONFIG
  • MicrocodePatchAddress : FSP_S_CONFIG
  • MicrocodeRegionBase : FSP_S_CONFIG , FSPT_CORE_UPD
  • MicrocodeRegionSize : FSP_S_CONFIG , FSPT_CORE_UPD
  • MlcSpatialPrefetcher : FSP_S_TEST_CONFIG
  • MlcStreamerPrefetcher : FSP_S_TEST_CONFIG
  • MmaTestConfigPtr : FSP_M_CONFIG
  • MmaTestConfigSize : FSP_M_CONFIG
  • MmaTestContentPtr : FSP_M_CONFIG
  • MmaTestContentSize : FSP_M_CONFIG
  • MmioSize : FSP_M_CONFIG
  • MmioSizeAdjustment : FSP_M_CONFIG
  • ModulePartNum : DIMM_INFO
  • MonitorMwaitEnable : FSP_S_TEST_CONFIG
  • MrcFastBoot : FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- n -

  • NModeSupport : FSP_M_CONFIG
  • NumberOfCacheLevels : SMBIOS_CACHE_INFO
  • NumberOfEntries : FSP_S_TEST_CONFIG
  • NumOfDevIntConfig : FSP_S_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- o -

  • OcLock : FSP_M_CONFIG
  • OcSupport : FSP_M_CONFIG
  • OddRatioMode : FSP_M_CONFIG
  • OneCoreRatioLimit : FSP_S_TEST_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputState : GPIO_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- p -

  • PadMode : GPIO_CONFIG
  • PanelPowerEnable : FSP_M_TEST_CONFIG
  • PavpEnable : FSP_S_CONFIG
  • PcdDebugInterfaceFlags : FSP_M_CONFIG
  • PcdIsaSerialUartBase : FSP_M_CONFIG
  • PcdPciExpressBaseAddress : FSP_T_CONFIG
  • PcdPciExpressRegionLength : FSP_T_CONFIG
  • PcdSerialDebugBaudRate : FSP_M_CONFIG
  • PcdSerialDebugLevel : FSP_M_CONFIG
  • PcdSerialIoUartDebugEnable : FSP_T_CONFIG
  • PcdSerialIoUartInputClock : FSP_T_CONFIG
  • PcdSerialIoUartNumber : FSP_M_CONFIG , FSP_T_CONFIG
  • PchAcpiBase : FSP_M_CONFIG
  • PchCio2Enable : FSP_S_CONFIG
  • PchCrid : FSP_S_CONFIG
  • PchDciAutoDetect : FSP_M_TEST_CONFIG
  • PchDciEn : FSP_M_TEST_CONFIG
  • PchDisableComplianceMode : FSP_S_CONFIG
  • PchDmiAspm : FSP_S_CONFIG
  • PchDmiTsawEn : FSP_S_CONFIG
  • PchHdaDspEnable : FSP_S_CONFIG
  • PchHdaDspEndpointBluetooth : FSP_S_CONFIG
  • PchHdaDspEndpointDmic : FSP_S_CONFIG
  • PchHdaDspEndpointI2s : FSP_S_CONFIG
  • PchHdaDspFeatureMask : FSP_S_CONFIG
  • PchHdaDspPpModuleMask : FSP_S_CONFIG
  • PchHdaDspUaaCompliance : FSP_S_CONFIG
  • PchHdaEnable : FSP_S_CONFIG
  • PchHdaIDispCodecDisconnect : FSP_S_CONFIG
  • PchHdaIDispLinkFrequency : FSP_S_CONFIG
  • PchHdaIDispLinkTmode : FSP_S_CONFIG
  • PchHdaIoBufferOwnership : FSP_S_CONFIG
  • PchHdaIoBufferVoltage : FSP_S_CONFIG
  • PchHdaLinkFrequency : FSP_S_CONFIG
  • PchHdaPme : FSP_S_CONFIG
  • PchHdaResetWaitTimer : FSP_S_TEST_CONFIG
  • PchHdaVcType : FSP_S_CONFIG
  • PchHdaVerbTableEntryNum : FSP_S_CONFIG
  • PchHdaVerbTablePtr : FSP_S_CONFIG
  • PchHpetBase : FSP_M_CONFIG
  • PchHpetBdfValid : FSP_M_CONFIG
  • PchHpetBusNumber : FSP_M_CONFIG
  • PchHpetDeviceNumber : FSP_M_CONFIG
  • PchHpetEnable : FSP_M_CONFIG
  • PchHpetFunctionNumber : FSP_M_CONFIG
  • PchIoApicBdfValid : FSP_S_CONFIG
  • PchIoApicBusNumber : FSP_S_CONFIG
  • PchIoApicDeviceNumber : FSP_S_CONFIG
  • PchIoApicEntry24_119 : FSP_S_CONFIG
  • PchIoApicFunctionNumber : FSP_S_CONFIG
  • PchIoApicId : FSP_S_CONFIG
  • PchIoApicRangeSelect : FSP_S_CONFIG
  • PchIshEnable : FSP_S_CONFIG
  • PchIshGp0GpioAssign : FSP_S_CONFIG
  • PchIshGp1GpioAssign : FSP_S_CONFIG
  • PchIshGp2GpioAssign : FSP_S_CONFIG
  • PchIshGp3GpioAssign : FSP_S_CONFIG
  • PchIshGp4GpioAssign : FSP_S_CONFIG
  • PchIshGp5GpioAssign : FSP_S_CONFIG
  • PchIshGp6GpioAssign : FSP_S_CONFIG
  • PchIshGp7GpioAssign : FSP_S_CONFIG
  • PchIshI2c0GpioAssign : FSP_S_CONFIG
  • PchIshI2c1GpioAssign : FSP_S_CONFIG
  • PchIshI2c2GpioAssign : FSP_S_CONFIG
  • PchIshPdtUnlock : FSP_S_CONFIG
  • PchIshSpiGpioAssign : FSP_S_CONFIG
  • PchIshUart0GpioAssign : FSP_S_CONFIG
  • PchIshUart1GpioAssign : FSP_S_CONFIG
  • PchLanClkReqNumber : FSP_S_CONFIG
  • PchLanClkReqSupported : FSP_S_CONFIG
  • PchLanEnable : FSP_S_CONFIG
  • PchLanK1OffEnable : FSP_S_CONFIG
  • PchLanLtrEnable : FSP_S_CONFIG
  • PchLegacyIoLowLatency : FSP_S_CONFIG
  • PchLockDownBiosInterface : FSP_S_TEST_CONFIG
  • PchLockDownBiosLock : FSP_S_CONFIG
  • PchLockDownGlobalSmi : FSP_S_TEST_CONFIG
  • PchLockDownRtcLock : FSP_S_TEST_CONFIG
  • PchLockDownSpiEiss : FSP_S_CONFIG
  • PchLpcEnhancePort8xhDecoding : FSP_M_CONFIG
  • PchMemoryC0TransmitEnable : FSP_S_CONFIG
  • PchMemoryPinSelection : FSP_S_CONFIG
  • PchMemoryPmsyncEnable : FSP_S_CONFIG
  • PchMemoryThrottlingEnable : FSP_S_CONFIG
  • PchNumRsvdSmbusAddresses : FSP_M_CONFIG
  • PchPcieDeviceOverrideTablePtr : FSP_S_CONFIG
  • PchPcieHsioRxSetCtle : FSP_M_CONFIG
  • PchPcieHsioRxSetCtleEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchPciePort8xhDecodePortIndex : FSP_S_TEST_CONFIG
  • PchPmCapsuleResetType : FSP_S_CONFIG
  • PchPmDeepSxPol : FSP_S_CONFIG
  • PchPmDisableDsxAcPresentPulldown : FSP_S_CONFIG
  • PchPmDisableEnergyReport : FSP_S_TEST_CONFIG
  • PchPmDisableNativePowerButton : FSP_S_CONFIG
  • PchPmLanWakeFromDeepSx : FSP_S_CONFIG
  • PchPmLpcClockRun : FSP_S_CONFIG
  • PchPmMeWakeSts : FSP_S_CONFIG
  • PchPmPciePllSsc : FSP_M_CONFIG
  • PchPmPcieWakeFromDeepSx : FSP_S_CONFIG
  • PchPmPmcReadDisable : FSP_S_TEST_CONFIG
  • PchPmPmeB0S5Dis : FSP_S_CONFIG
  • PchPmPwrBtnOverridePeriod : FSP_S_CONFIG
  • PchPmPwrCycDur : FSP_S_CONFIG
  • PchPmSlpAMinAssert : FSP_S_CONFIG
  • PchPmSlpLanLowDc : FSP_S_CONFIG
  • PchPmSlpS0Enable : FSP_S_CONFIG
  • PchPmSlpS0VmEnable : FSP_S_CONFIG
  • PchPmSlpS3MinAssert : FSP_S_CONFIG
  • PchPmSlpS4MinAssert : FSP_S_CONFIG
  • PchPmSlpStrchSusUp : FSP_S_CONFIG
  • PchPmSlpSusMinAssert : FSP_S_CONFIG
  • PchPmWolEnableOverride : FSP_S_CONFIG
  • PchPmWolOvrWkSts : FSP_S_CONFIG
  • PchPmWoWlanDeepSxEnable : FSP_S_CONFIG
  • PchPmWoWlanEnable : FSP_S_CONFIG
  • PchPort61hEnable : FSP_S_CONFIG
  • PchPort80Route : FSP_M_CONFIG
  • PchProtectedRangeBase : FSP_S_CONFIG
  • PchProtectedRangeLimit : FSP_S_CONFIG
  • PchPwrOptEnable : FSP_S_CONFIG
  • PchReadProtectionEnable : FSP_S_CONFIG
  • PchSataHsioRxGen1EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen1EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchSbAccessUnlock : FSP_S_TEST_CONFIG
  • PchSbiUnlock : FSP_S_TEST_CONFIG
  • PchScsEmmcHs400DllDataValid : FSP_S_CONFIG
  • PchScsEmmcHs400DriverStrength : FSP_S_CONFIG
  • PchScsEmmcHs400RxStrobeDll1 : FSP_S_CONFIG
  • PchScsEmmcHs400TuningRequired : FSP_S_CONFIG
  • PchScsEmmcHs400TxDataDll : FSP_S_CONFIG
  • PchSirqEnable : FSP_S_CONFIG
  • PchSirqMode : FSP_S_CONFIG
  • PchSkyCamPortAClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortACtleCapValue : FSP_S_CONFIG
  • PchSkyCamPortACtleEnable : FSP_S_CONFIG
  • PchSkyCamPortACtleResValue : FSP_S_CONFIG
  • PchSkyCamPortADataTrimValue : FSP_S_CONFIG
  • PchSkyCamPortATermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortATrimEnable : FSP_S_CONFIG
  • PchSkyCamPortBClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortBCtleCapValue : FSP_S_CONFIG
  • PchSkyCamPortBCtleEnable : FSP_S_CONFIG
  • PchSkyCamPortBCtleResValue : FSP_S_CONFIG
  • PchSkyCamPortBDataTrimValue : FSP_S_CONFIG
  • PchSkyCamPortBTermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortBTrimEnable : FSP_S_CONFIG
  • PchSkyCamPortCClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortCDCtleCapValue : FSP_S_CONFIG
  • PchSkyCamPortCDCtleEnable : FSP_S_CONFIG
  • PchSkyCamPortCDCtleResValue : FSP_S_CONFIG
  • PchSkyCamPortCDDataTrimValue : FSP_S_CONFIG
  • PchSkyCamPortCTermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortCTrimEnable : FSP_S_CONFIG
  • PchSkyCamPortDClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortDTermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortDTrimEnable : FSP_S_CONFIG
  • PchSmbusIoBase : FSP_M_CONFIG
  • PchStartFramePulse : FSP_S_CONFIG
  • PchSubSystemId : FSP_S_CONFIG
  • PchSubSystemVendorId : FSP_S_CONFIG
  • PchT0Level : FSP_S_CONFIG
  • PchT1Level : FSP_S_CONFIG
  • PchT2Level : FSP_S_CONFIG
  • PchTemperatureHotLevel : FSP_S_CONFIG
  • PchThermalDeviceEnable : FSP_S_CONFIG
  • PchTsmicLock : FSP_S_CONFIG
  • PchTTEnable : FSP_S_CONFIG
  • PchTTLock : FSP_S_CONFIG
  • PchTTState13Enable : FSP_S_CONFIG
  • PchWriteProtectionEnable : FSP_S_CONFIG
  • PcieAllowNoLtrIccPllShutdown : FSP_S_CONFIG
  • PcieComplianceTestMode : FSP_S_CONFIG
  • PcieDetectTimeoutMs : FSP_S_CONFIG
  • PcieDisableRootPortClockGating : FSP_S_CONFIG
  • PcieEnablePeerMemoryWrite : FSP_S_CONFIG
  • PcieEnablePort8xhDecode : FSP_S_TEST_CONFIG
  • PcieEqPh3LaneParamCm : FSP_S_CONFIG
  • PcieEqPh3LaneParamCp : FSP_S_CONFIG
  • PcieRpAdvancedErrorReporting : FSP_S_CONFIG
  • PcieRpAspm : FSP_S_CONFIG
  • PcieRpClkReqDetect : FSP_S_CONFIG
  • PcieRpClkReqNumber : FSP_S_CONFIG
  • PcieRpClkReqSupport : FSP_S_CONFIG
  • PcieRpClkSrcNumber : FSP_S_CONFIG
  • PcieRpCompletionTimeout : FSP_S_CONFIG
  • PcieRpCorrectableErrorReport : FSP_S_CONFIG
  • PcieRpDeviceResetPad : FSP_S_CONFIG
  • PcieRpDeviceResetPadActiveHigh : FSP_S_CONFIG
  • PcieRpDptp : FSP_S_TEST_CONFIG
  • PcieRpEnableMask : FSP_M_CONFIG
  • PcieRpExtSync : FSP_S_CONFIG
  • PcieRpFatalErrorReport : FSP_S_CONFIG
  • PcieRpFunctionSwap : FSP_S_CONFIG
  • PcieRpGen3EqPh3Method : FSP_S_CONFIG
  • PcieRpHotPlug : FSP_S_CONFIG
  • PcieRpL1Substates : FSP_S_CONFIG
  • PcieRpLtrConfigLock : FSP_S_CONFIG
  • PcieRpLtrEnable : FSP_S_CONFIG
  • PcieRpLtrMaxNoSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpLtrMaxSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpMaxPayload : FSP_S_CONFIG
  • PcieRpNoFatalErrorReport : FSP_S_CONFIG
  • PcieRpNonSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpPcieSpeed : FSP_S_CONFIG
  • PcieRpPhysicalSlotNumber : FSP_S_CONFIG
  • PcieRpPmSci : FSP_S_CONFIG
  • PcieRpSlotPowerLimitScale : FSP_S_TEST_CONFIG
  • PcieRpSlotPowerLimitValue : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpSystemErrorOnCorrectableError : FSP_S_CONFIG
  • PcieRpSystemErrorOnFatalError : FSP_S_CONFIG
  • PcieRpSystemErrorOnNonFatalError : FSP_S_CONFIG
  • PcieRpTransmitterHalfSwing : FSP_S_CONFIG
  • PcieRpUnsupportedRequestReport : FSP_S_CONFIG
  • PcieRpUptp : FSP_S_TEST_CONFIG
  • PcieSwEqCoeffListCm : FSP_S_CONFIG
  • PcieSwEqCoeffListCp : FSP_S_CONFIG
  • PeciC10Reset : FSP_M_CONFIG
  • PeciSxReset : FSP_M_CONFIG
  • Peg0Enable : FSP_M_CONFIG
  • Peg0Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg0Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg0MaxLinkSpeed : FSP_M_CONFIG
  • Peg0MaxLinkWidth : FSP_M_CONFIG
  • Peg0PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg1Enable : FSP_M_CONFIG
  • Peg1Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg1Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg1MaxLinkSpeed : FSP_M_CONFIG
  • Peg1MaxLinkWidth : FSP_M_CONFIG
  • Peg1PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg2Enable : FSP_M_CONFIG
  • Peg2Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg2Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg2MaxLinkSpeed : FSP_M_CONFIG
  • Peg2MaxLinkWidth : FSP_M_CONFIG
  • Peg2PowerDownUnusedLanes : FSP_M_CONFIG
  • PegDataPtr : FSP_M_CONFIG
  • PegDeEmphasis : FSP_S_CONFIG
  • PegDisableSpreadSpectrumClocking : FSP_M_CONFIG
  • PegGen3EndPointHint : FSP_M_TEST_CONFIG
  • PegGen3EndPointPreset : FSP_M_TEST_CONFIG
  • PegGen3ProgramStaticEq : FSP_M_TEST_CONFIG
  • PegGen3RootPortPreset : FSP_M_TEST_CONFIG
  • PegGen3Rsvd : FSP_M_TEST_CONFIG
  • PegGen3RxCtleOverride : FSP_M_TEST_CONFIG
  • PegGen3RxCtlePeaking : FSP_M_CONFIG
  • PegGenerateBdatMarginTable : FSP_M_TEST_CONFIG
  • PegGpioData : FSP_M_CONFIG
  • PegMaxPayload : FSP_S_TEST_CONFIG
  • PegPhysicalSlotNumber : FSP_S_CONFIG
  • PegRootPortHPE : FSP_M_CONFIG
  • PegRxCemLoopbackLane : FSP_M_TEST_CONFIG
  • PegRxCemNonProtocolAwareness : FSP_M_TEST_CONFIG
  • PegRxCemTestingMode : FSP_M_TEST_CONFIG
  • PegSlotPowerLimitScale : FSP_S_CONFIG
  • PegSlotPowerLimitValue : FSP_S_CONFIG
  • PeiGraphicsPeimInit : FSP_S_CONFIG
  • PkgCStateDemotion : FSP_S_TEST_CONFIG
  • PkgCStateLimit : FSP_S_TEST_CONFIG
  • PkgCStateUnDemotion : FSP_S_TEST_CONFIG
  • PlatformMemorySize : FSP_M_CONFIG
  • PmgCstCfgCtrlLock : FSP_S_TEST_CONFIG
  • PmSupport : FSP_S_TEST_CONFIG
  • PortUsb20Enable : FSP_S_CONFIG
  • PortUsb30Enable : FSP_S_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerLimit1 : FSP_S_TEST_CONFIG
  • PowerLimit1Time : FSP_S_TEST_CONFIG
  • PowerLimit2 : FSP_S_TEST_CONFIG
  • PowerLimit2Power : FSP_S_TEST_CONFIG
  • PowerLimit3 : FSP_S_TEST_CONFIG
  • PowerLimit3DutyCycle : FSP_S_TEST_CONFIG
  • PowerLimit3Lock : FSP_S_TEST_CONFIG
  • PowerLimit3Time : FSP_S_TEST_CONFIG
  • PowerLimit4 : FSP_S_TEST_CONFIG
  • PowerLimit4Lock : FSP_S_TEST_CONFIG
  • PpmIrmSetting : FSP_S_TEST_CONFIG
  • PrimaryDisplay : FSP_M_CONFIG
  • PrmrrSize : FSP_M_CONFIG
  • ProbelessTrace : FSP_M_CONFIG
  • ProcessorCharacteristics : SMBIOS_PROCESSOR_INFO
  • ProcessorFamily : SMBIOS_PROCESSOR_INFO
  • ProcessorId : SMBIOS_PROCESSOR_INFO
  • ProcessorManufacturerStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcessorType : SMBIOS_PROCESSOR_INFO
  • ProcessorUpgrade : SMBIOS_PROCESSOR_INFO
  • ProcessorVersionStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcHotLock : FSP_S_TEST_CONFIG
  • ProcHotResponse : FSP_S_TEST_CONFIG
  • ProcTraceEnable : FSP_S_TEST_CONFIG
  • ProcTraceMemSize : FSP_S_TEST_CONFIG
  • ProcTraceOutputScheme : FSP_S_TEST_CONFIG
  • Psi1Threshold : FSP_S_CONFIG
  • Psi2Threshold : FSP_S_CONFIG
  • Psi3Enable : FSP_S_CONFIG
  • Psi3Threshold : FSP_S_CONFIG
  • Psi4Enable : FSP_S_CONFIG
  • PsysOffset : FSP_S_CONFIG
  • PsysPmax : FSP_S_TEST_CONFIG
  • PsysPowerLimit1 : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Power : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Time : FSP_S_TEST_CONFIG
  • PsysPowerLimit2 : FSP_S_TEST_CONFIG
  • PsysPowerLimit2Power : FSP_S_TEST_CONFIG
  • PsysSlope : FSP_S_CONFIG
  • PxRcConfig : FSP_S_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
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Here is a list of all documented class members with links to the class documentation for each member:

- r -

  • RaceToHalt : FSP_S_TEST_CONFIG
  • RankInDimm : DIMM_INFO
  • Ratio : FSP_M_CONFIG
  • RcompResistor : FSP_M_CONFIG
  • RcompTarget : FSP_M_CONFIG
  • RealtimeMemoryTiming : FSP_M_CONFIG
  • RefClk : FSP_M_CONFIG
  • RenderStandby : FSP_S_TEST_CONFIG
  • Reserved : AZALIA_HEADER , FSPT_CORE_UPD
  • ReservedCpuPostMemTest : FSP_S_TEST_CONFIG
  • ReservedFspmTestUpd : FSP_M_TEST_CONFIG
  • ReservedFspmUpd : FSP_M_CONFIG
  • ReservedFspsTestUpd : FSP_S_TEST_CONFIG
  • ReservedFspsUpd : FSP_S_CONFIG
  • ReservedFsptUpd1 : FSP_T_CONFIG
  • ReservedSecurityPreMem : FSP_M_CONFIG
  • RevisionId : AZALIA_HEADER
  • RingDownBin : FSP_M_CONFIG
  • RingMaxOcRatio : FSP_M_CONFIG
  • RingMinOcRatio : FSP_M_CONFIG
  • RingPllVoltageOffset : FSP_M_CONFIG
  • RMT : FSP_M_CONFIG
  • RootPortDev : FSP_M_CONFIG
  • RootPortFun : FSP_M_CONFIG
  • RsvdBits : GPIO_CONFIG
  • RsvdSmbusAddressTablePtr : FSP_M_CONFIG


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
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Here is a list of all documented class members with links to the class documentation for each member:

- s -

  • SaGv : FSP_M_CONFIG
  • SaImguEnable : FSP_S_CONFIG
  • SaOcSupport : FSP_M_CONFIG
  • SaPllVoltageOffset : FSP_M_CONFIG
  • SaPostMemProductionRsvd : FSP_S_CONFIG
  • SaPostMemTestRsvd : FSP_S_TEST_CONFIG
  • SaPreMemTestRsvd : FSP_M_TEST_CONFIG
  • SaRtd3Pcie0Gpio : FSP_M_CONFIG
  • SaRtd3Pcie1Gpio : FSP_M_CONFIG
  • SaRtd3Pcie2Gpio : FSP_M_CONFIG
  • SataEnable : FSP_S_CONFIG
  • SataMode : FSP_S_CONFIG
  • SataP0T1M : FSP_S_CONFIG
  • SataP0T2M : FSP_S_CONFIG
  • SataP0T3M : FSP_S_CONFIG
  • SataP0TDisp : FSP_S_CONFIG
  • SataP0TDispFinit : FSP_S_CONFIG
  • SataP0Tinact : FSP_S_CONFIG
  • SataP1T1M : FSP_S_CONFIG
  • SataP1T2M : FSP_S_CONFIG
  • SataP1T3M : FSP_S_CONFIG
  • SataP1TDisp : FSP_S_CONFIG
  • SataP1TDispFinit : FSP_S_CONFIG
  • SataP1Tinact : FSP_S_CONFIG
  • SataPortsDevSlp : FSP_S_CONFIG
  • SataPortsDitoVal : FSP_S_CONFIG
  • SataPortsDmVal : FSP_S_CONFIG
  • SataPortsEnable : FSP_S_CONFIG
  • SataPortsEnableDitoConfig : FSP_S_CONFIG
  • SataPortsExternal : FSP_S_CONFIG
  • SataPortsHotPlug : FSP_S_CONFIG
  • SataPortsInterlockSw : FSP_S_CONFIG
  • SataPortsSolidStateDrive : FSP_S_CONFIG
  • SataPortsSpinUp : FSP_S_CONFIG
  • SataPortsZpOdd : FSP_S_CONFIG
  • SataPwrOptEnable : FSP_S_CONFIG
  • SataRstCpuAttachedStorage : FSP_S_CONFIG
  • SataRstHddUnlock : FSP_S_CONFIG
  • SataRstIrrt : FSP_S_CONFIG
  • SataRstIrrtOnly : FSP_S_CONFIG
  • SataRstLedLocate : FSP_S_CONFIG
  • SataRstOptaneMemory : FSP_S_CONFIG
  • SataRstOromUiBanner : FSP_S_CONFIG
  • SataRstOromUiDelay : FSP_S_CONFIG
  • SataRstPcieDeviceResetDelay : FSP_S_CONFIG
  • SataRstPcieEnable : FSP_S_CONFIG
  • SataRstPcieStoragePort : FSP_S_CONFIG
  • SataRstRaid0 : FSP_S_CONFIG
  • SataRstRaid1 : FSP_S_CONFIG
  • SataRstRaid10 : FSP_S_CONFIG
  • SataRstRaid5 : FSP_S_CONFIG
  • SataRstRaidAlternateId : FSP_S_CONFIG
  • SataRstSmartStorage : FSP_S_CONFIG
  • SataSalpSupport : FSP_S_CONFIG
  • SataSpeedLimit : FSP_S_CONFIG
  • SataTestMode : FSP_S_TEST_CONFIG
  • SataThermalSuggestedSetting : FSP_S_CONFIG
  • SaVoltageOffset : FSP_M_CONFIG
  • ScanExtGfxForLegacyOpRom : FSP_M_TEST_CONFIG
  • SciIrqSelect : FSP_S_CONFIG
  • ScsEmmcEnabled : FSP_S_CONFIG
  • ScsEmmcHs400Enabled : FSP_S_CONFIG
  • ScsSdCardEnabled : FSP_S_CONFIG
  • SdiNum : AZALIA_HEADER
  • SendDidMsg : FSP_M_TEST_CONFIG
  • SendEcCmd : FSP_S_CONFIG
  • SendVrMbxCmd : FSP_S_CONFIG
  • SendVrMbxCmd1 : FSP_S_CONFIG
  • SerialIoDebugUartNumber : FSP_S_CONFIG
  • SerialIoDevMode : FSP_S_CONFIG
  • SerialIoEnableDebugUartAfterPost : FSP_S_CONFIG
  • SerialIoGpio : FSP_S_CONFIG
  • SerialIoI2cVoltage : FSP_S_CONFIG
  • SerialIoSpiCsPolarity : FSP_S_CONFIG
  • SerialIoUartHwFlowCtrl : FSP_S_CONFIG
  • SevenCoreRatioLimit : FSP_S_TEST_CONFIG
  • SgDelayAfterHoldReset : FSP_M_CONFIG
  • SgDelayAfterPwrEn : FSP_M_CONFIG
  • SgxEpoch0 : FSP_S_CONFIG
  • SgxEpoch1 : FSP_S_CONFIG
  • SgxSinitDataFromTpm : FSP_S_TEST_CONFIG
  • SgxSinitNvsData : FSP_S_CONFIG
  • ShowSpiController : FSP_S_CONFIG
  • Signature : FSP_M_TEST_CONFIG , FSP_S_TEST_CONFIG
  • SinitMemorySize : FSP_M_CONFIG
  • SixCoreRatioLimit : FSP_S_TEST_CONFIG
  • SkipExtGfxScan : FSP_M_TEST_CONFIG
  • SkipMbpHob : FSP_M_TEST_CONFIG
  • SkipPamLock : FSP_S_TEST_CONFIG
  • SkipStopPbet : FSP_M_CONFIG
  • SlowSlewRateForGt : FSP_S_CONFIG
  • SlowSlewRateForIa : FSP_S_CONFIG
  • SlowSlewRateForSa : FSP_S_CONFIG
  • SmbusArpEnable : FSP_M_CONFIG
  • SmbusDynamicPowerGating : FSP_M_TEST_CONFIG
  • SmbusEnable : FSP_M_CONFIG
  • SmbusSpdWriteDisable : FSP_M_TEST_CONFIG
  • SmramMask : FSP_M_CONFIG
  • SocketDesignationStrIndex : SMBIOS_CACHE_INFO
  • SpdDramDeviceType : DIMM_INFO
  • SpdModuleMemoryBusWidth : DIMM_INFO
  • SpdModuleType : DIMM_INFO
  • SpdProfileSelected : FSP_M_CONFIG
  • SpdSave : DIMM_INFO
  • SpiFlashCfgLockDown : FSP_S_CONFIG
  • SsicPortEnable : FSP_S_CONFIG
  • StateRatio : FSP_S_TEST_CONFIG
  • Status : DIMM_INFO , SMBIOS_PROCESSOR_INFO
  • SupportedSramType : SMBIOS_CACHE_INFO
  • SystemCacheType : SMBIOS_CACHE_INFO
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
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Here is a list of all documented class members with links to the class documentation for each member:

- t -

  • TccActivationOffset : FSP_S_TEST_CONFIG
  • TccOffsetClamp : FSP_S_TEST_CONFIG
  • TccOffsetLock : FSP_S_TEST_CONFIG
  • TccOffsetTimeWindowForRatl : FSP_S_TEST_CONFIG
  • tCL : FSP_M_CONFIG
  • TcoIrqEnable : FSP_S_CONFIG
  • TcoIrqSelect : FSP_S_CONFIG
  • tCWL : FSP_M_CONFIG
  • TdcEnable : FSP_S_CONFIG
  • TdcLock : FSP_S_CONFIG
  • TdcPowerLimit : FSP_S_CONFIG
  • TdcTimeWindow : FSP_S_CONFIG
  • tFAW : FSP_M_CONFIG
  • TgaSize : FSP_M_TEST_CONFIG
  • ThermalMonitor : FSP_S_TEST_CONFIG
  • ThreadCount : SMBIOS_PROCESSOR_INFO
  • ThreeCoreRatioLimit : FSP_S_TEST_CONFIG
  • ThreeStrikeCounterDisable : FSP_S_TEST_CONFIG
  • TimedMwait : FSP_S_TEST_CONFIG
  • TjMaxOffset : FSP_M_CONFIG
  • TotalFlashSize : FSP_M_TEST_CONFIG
  • TraceHubMemReg0Size : FSP_M_CONFIG
  • TraceHubMemReg1Size : FSP_M_CONFIG
  • tRAS : FSP_M_CONFIG
  • tRCDtRP : FSP_M_CONFIG
  • tREFI : FSP_M_CONFIG
  • tRFC : FSP_M_CONFIG
  • tRRD : FSP_M_CONFIG
  • tRTP : FSP_M_CONFIG
  • TsegSize : FSP_M_CONFIG
  • TStates : FSP_S_TEST_CONFIG
  • TTCrossThrottling : FSP_S_CONFIG
  • TTSuggestedSetting : FSP_S_CONFIG
  • TurboMode : FSP_S_CONFIG
  • TurboPowerLimitLock : FSP_S_TEST_CONFIG
  • TvbRatioClipping : FSP_M_CONFIG
  • TvbVoltageOptimization : FSP_M_CONFIG
  • TwoCoreRatioLimit : FSP_S_TEST_CONFIG
  • tWR : FSP_M_CONFIG
  • tWTR : FSP_M_CONFIG
  • Txt : FSP_M_CONFIG
  • TxtDprMemoryBase : FSP_M_CONFIG
  • TxtDprMemorySize : FSP_M_CONFIG
  • TxtHeapMemorySize : FSP_M_CONFIG
  • TxtImplemented : FSP_M_CONFIG
  • TxtLcpPdBase : FSP_M_TEST_CONFIG
  • TxtLcpPdSize : FSP_M_TEST_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
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Here is a list of all documented class members with links to the class documentation for each member:

- u -

  • UnusedUpdSpace0 : FSP_M_CONFIG , FSP_S_CONFIG , FSP_T_CONFIG
  • UnusedUpdSpace1 : FSP_M_CONFIG , FSP_S_CONFIG , FSPT_UPD
  • UnusedUpdSpace10 : FSP_S_CONFIG , FSPM_UPD
  • UnusedUpdSpace11 : FSP_S_CONFIG
  • UnusedUpdSpace12 : FSP_S_CONFIG
  • UnusedUpdSpace13 : FSP_S_CONFIG
  • UnusedUpdSpace14 : FSP_S_CONFIG
  • UnusedUpdSpace15 : FSP_S_CONFIG
  • UnusedUpdSpace16 : FSP_S_CONFIG
  • UnusedUpdSpace17 : FSP_S_CONFIG
  • UnusedUpdSpace18 : FSP_S_CONFIG
  • UnusedUpdSpace19 : FSP_S_CONFIG
  • UnusedUpdSpace2 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace20 : FSP_S_CONFIG
  • UnusedUpdSpace21 : FSP_S_CONFIG
  • UnusedUpdSpace22 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace23 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace24 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace25 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace26 : FSPS_UPD
  • UnusedUpdSpace3 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace4 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace5 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace6 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace7 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace8 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace9 : FSP_M_TEST_CONFIG , FSP_S_CONFIG
  • UpdTerminator : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Usb2AfePehalfbit : FSP_S_CONFIG
  • Usb2AfePetxiset : FSP_S_CONFIG
  • Usb2AfePredeemp : FSP_S_CONFIG
  • Usb2AfeTxiset : FSP_S_CONFIG
  • Usb2OverCurrentPin : FSP_S_CONFIG
  • Usb3HsioTxDeEmph : FSP_S_CONFIG
  • Usb3HsioTxDeEmphEnable : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmp : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmpEnable : FSP_S_CONFIG
  • Usb3OverCurrentPin : FSP_S_CONFIG
  • UserBd : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- v -

  • VddVoltage : FSP_M_CONFIG
  • VendorId : AZALIA_HEADER
  • VmxEnable : FSP_M_CONFIG
  • Voltage : SMBIOS_PROCESSOR_INFO
  • VoltageOptimization : FSP_S_TEST_CONFIG
  • VrConfigEnable : FSP_S_CONFIG
  • VrPowerDeliveryDesign : FSP_S_CONFIG
  • VrVoltageLimit : FSP_S_CONFIG
  • VtdBaseAddress : FSP_S_CONFIG
  • VtdDisable : FSP_S_TEST_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
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Here is a list of all documented class members with links to the class documentation for each member:

- w -

  • WatchDog : FSP_S_CONFIG
  • WatchDogTimerBios : FSP_S_CONFIG
  • WatchDogTimerOs : FSP_S_CONFIG
  • WdtDisableAndLock : FSP_M_TEST_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
  • b
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  • x
Here is a list of all documented class members with links to the class documentation for each member:

- x -

  • X2ApicOptOut : FSP_S_CONFIG
  • XdciEnable : FSP_S_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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  • Variables
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- a -

  • AcLoadline : FSP_S_CONFIG
  • AcousticNoiseMitigation : FSP_S_CONFIG
  • ActiveCoreCount : FSP_M_CONFIG
  • AmtEnabled : FSP_S_CONFIG
  • AmtSolEnabled : FSP_S_CONFIG
  • ApertureSize : FSP_M_CONFIG
  • ApHandoffManner : FSP_S_TEST_CONFIG
  • ApIdleManner : FSP_S_TEST_CONFIG
  • AsfEnabled : FSP_S_CONFIG
  • Associativity : SMBIOS_CACHE_INFO
  • AutoThermalReporting : FSP_S_TEST_CONFIG
  • Avx2RatioOffset : FSP_M_CONFIG
  • Avx3RatioOffset : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

  • All
  • Variables
  • a
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- b -

  • BclkAdaptiveVoltage : FSP_M_CONFIG
  • BdatEnable : FSP_M_TEST_CONFIG
  • BgpdtHash : FSP_S_CONFIG
  • BiosAcmBase : FSP_M_TEST_CONFIG
  • BiosAcmSize : FSP_M_TEST_CONFIG
  • BiosGuard : FSP_M_CONFIG
  • BiosGuardAttr : FSP_S_CONFIG
  • BiosGuardModulePtr : FSP_S_CONFIG
  • BiosSize : FSP_M_TEST_CONFIG
  • BiProcHot : FSP_S_TEST_CONFIG
  • BistOnReset : FSP_M_CONFIG
  • BootFrequency : FSP_M_CONFIG
  • BypassPhySyncReset : FSP_M_TEST_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

  • All
  • Variables
  • a
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  • i
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- c -

  • C1e : FSP_S_TEST_CONFIG
  • CacheConfiguration : SMBIOS_CACHE_INFO
  • CacheSpeed : SMBIOS_CACHE_INFO
  • CaVrefConfig : FSP_M_CONFIG
  • CdClock : FSP_S_CONFIG
  • CdynmaxClampEnable : FSP_S_TEST_CONFIG
  • ChapDeviceEnable : FSP_S_TEST_CONFIG
  • ChipsetInitMessage : FSP_M_TEST_CONFIG
  • CleanMemory : FSP_M_CONFIG
  • CmdTriStateDis : FSP_M_CONFIG
  • CodeRegionBase : FSPT_CORE_UPD
  • CodeRegionSize : FSPT_CORE_UPD
  • ConfigTdpBios : FSP_S_TEST_CONFIG
  • ConfigTdpLevel : FSP_S_TEST_CONFIG
  • ConfigTdpLock : FSP_S_TEST_CONFIG
  • CoreCount : SMBIOS_PROCESSOR_INFO
  • CoreMaxOcRatio : FSP_M_CONFIG
  • CorePllVoltageOffset : FSP_M_CONFIG
  • CoreVoltageAdaptive : FSP_M_CONFIG
  • CoreVoltageMode : FSP_M_CONFIG
  • CoreVoltageOffset : FSP_M_CONFIG
  • CoreVoltageOverride : FSP_M_CONFIG
  • CpuConfig : FSP_S_CONFIG
  • CpuRatio : FSP_M_CONFIG
  • CpuRatioOverride : FSP_M_CONFIG
  • CpuS3ResumeData : FSP_S_TEST_CONFIG
  • CpuS3ResumeDataSize : FSP_S_TEST_CONFIG
  • CpuS3ResumeMtrrData : FSP_S_CONFIG
  • CpuS3ResumeMtrrDataSize : FSP_S_CONFIG
  • CridEnable : FSP_S_CONFIG
  • CstateLatencyControl0Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl1Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl2Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl3Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl4Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl5Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : FSP_S_TEST_CONFIG
  • CStatePreWake : FSP_S_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : FSP_S_TEST_CONFIG
  • CurrentSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • CurrentSramType : SMBIOS_CACHE_INFO
  • Custom1ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom1PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom1TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom2ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom2PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom2TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom3ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom3PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom3TurboActivationRatio : FSP_S_TEST_CONFIG
  • Cx : FSP_S_TEST_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- d -

  • Data : AUDIO_AZALIA_VERB_TABLE
  • DataDwords : AZALIA_HEADER
  • DcLoadline : FSP_S_CONFIG
  • DdrFreqLimit : FSP_M_CONFIG
  • DebugInterfaceEnable : FSP_S_TEST_CONFIG
  • DebugInterfaceLockEnable : FSP_S_TEST_CONFIG
  • DefaultSid : FSP_S_CONFIG
  • DefaultSvid : FSP_S_CONFIG
  • DelayUsbPdoProgramming : FSP_S_CONFIG
  • Device : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Device4Enable : FSP_S_CONFIG
  • DeviceId : AZALIA_HEADER
  • DevIntConfigPtr : FSP_S_CONFIG
  • DidInitStat : FSP_M_TEST_CONFIG
  • DimmCapacity : DIMM_INFO
  • Direction : GPIO_CONFIG
  • DisableCpuReplacedPolling : FSP_M_TEST_CONFIG
  • DisableD0I3SettingForHeci : FSP_S_TEST_CONFIG
  • DisableHeciRetry : FSP_M_TEST_CONFIG
  • DisableMessageCheck : FSP_M_TEST_CONFIG
  • DisableProcHotOut : FSP_S_TEST_CONFIG
  • DisableVrThermalAlert : FSP_S_TEST_CONFIG
  • DllBwEn0 : FSP_M_CONFIG
  • DllBwEn1 : FSP_M_CONFIG
  • DllBwEn2 : FSP_M_CONFIG
  • DllBwEn3 : FSP_M_CONFIG
  • DmiAspm : FSP_S_CONFIG
  • DmiDeEmphasis : FSP_M_CONFIG
  • DmiExtSync : FSP_S_TEST_CONFIG
  • DmiGen3EndPointHint : FSP_M_CONFIG
  • DmiGen3EndPointPreset : FSP_M_CONFIG
  • DmiGen3EqPh2Enable : FSP_M_TEST_CONFIG
  • DmiGen3EqPh3Method : FSP_M_TEST_CONFIG
  • DmiGen3ProgramStaticEq : FSP_M_CONFIG
  • DmiGen3RootPortPreset : FSP_M_CONFIG
  • DmiGen3RxCtlePeaking : FSP_M_CONFIG
  • DmiIot : FSP_S_TEST_CONFIG
  • DmiMaxLinkSpeed : FSP_M_TEST_CONFIG
  • DmiSuggestedSetting : FSP_S_CONFIG
  • DmiTS0TW : FSP_S_CONFIG
  • DmiTS1TW : FSP_S_CONFIG
  • DmiTS2TW : FSP_S_CONFIG
  • DmiTS3TW : FSP_S_CONFIG
  • DmiVc1 : FSP_M_TEST_CONFIG
  • DmiVcm : FSP_M_TEST_CONFIG
  • DqByteMapCh0 : FSP_M_CONFIG
  • DqByteMapCh1 : FSP_M_CONFIG
  • DqPinsInterleaved : FSP_M_CONFIG
  • DqsMapCpu2DramCh0 : FSP_M_CONFIG
  • DqsMapCpu2DramCh1 : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- e -

  • Early8254ClockGatingEnable : FSP_S_CONFIG
  • EcCmdLock : FSP_S_CONFIG
  • EcCmdProvisionEav : FSP_S_CONFIG
  • EdramRatio : FSP_M_CONFIG
  • EdramTestMode : FSP_S_TEST_CONFIG
  • EightCoreRatioLimit : FSP_S_TEST_CONFIG
  • Eist : FSP_S_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • EnableC6Dram : FSP_M_CONFIG
  • EnabledCoreCount : SMBIOS_PROCESSOR_INFO
  • EnableSgx : FSP_M_CONFIG
  • EnableTcoTimer : FSP_S_CONFIG
  • EnableTraceHub : FSP_M_CONFIG
  • EndOfPostMessage : FSP_S_TEST_CONFIG
  • EnergyEfficientPState : FSP_S_TEST_CONFIG
  • EnergyEfficientTurbo : FSP_S_TEST_CONFIG
  • ErrorCorrectionType : SMBIOS_CACHE_INFO
  • EsataSpeedLimit : FSP_S_CONFIG
  • EvLoader : FSP_M_CONFIG
  • ExternalClockInMHz : SMBIOS_PROCESSOR_INFO
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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  • FastPkgCRampDisableGt : FSP_S_CONFIG
  • FastPkgCRampDisableIa : FSP_S_CONFIG
  • FastPkgCRampDisableSa : FSP_S_CONFIG
  • FClkFrequency : FSP_M_CONFIG
  • FiveCoreRatioLimit : FSP_S_TEST_CONFIG
  • FlashWearOutProtection : FSP_M_CONFIG
  • FourCoreRatioLimit : FSP_S_TEST_CONFIG
  • FspmArchUpd : FSPM_UPD
  • FspmConfig : FSPM_UPD
  • FspmTestConfig : FSPM_UPD
  • FspsConfig : FSPS_UPD
  • FspsTestConfig : FSPS_UPD
  • FsptConfig : FSPT_UPD
  • FsptCoreUpd : FSPT_UPD
  • FspUpdHeader : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Function : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • FwProgress : FSP_S_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- g -

  • Gen3SwEqAlwaysAttempt : FSP_M_TEST_CONFIG
  • Gen3SwEqEnableVocTest : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterErrorTarget : FSP_M_TEST_CONFIG
  • Gen3SwEqNumberOfPresets : FSP_M_TEST_CONFIG
  • Gen3SwEqVocDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqVocErrorTarget : FSP_M_TEST_CONFIG
  • GmmEnable : FSP_S_CONFIG
  • GpioIrqRoute : FSP_S_CONFIG
  • GraphicsConfigPtr : FSP_S_CONFIG
  • GtFreqMax : FSP_S_TEST_CONFIG
  • GtPllVoltageOffset : FSP_M_CONFIG
  • GtsExtraTurboVoltage : FSP_M_CONFIG
  • GtsMaxOcRatio : FSP_M_CONFIG
  • GtsVoltageMode : FSP_M_CONFIG
  • GtsVoltageOffset : FSP_M_CONFIG
  • GtsVoltageOverride : FSP_M_CONFIG
  • GttMmAdr : FSP_M_CONFIG
  • GttSize : FSP_M_CONFIG
  • GtusExtraTurboVoltage : FSP_M_CONFIG
  • GtusMaxOcRatio : FSP_M_CONFIG
  • GtusVoltageMode : FSP_M_CONFIG
  • GtusVoltageOffset : FSP_M_CONFIG
  • GtusVoltageOverride : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- h -

  • HdcControl : FSP_S_TEST_CONFIG
  • Header : AUDIO_AZALIA_VERB_TABLE
  • Heci1BarAddress : FSP_M_CONFIG
  • Heci2BarAddress : FSP_M_CONFIG
  • Heci3BarAddress : FSP_M_CONFIG
  • Heci3Enabled : FSP_S_CONFIG
  • HeciCommunication2 : FSP_M_TEST_CONFIG
  • HeciTimeouts : FSP_M_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • Hwp : FSP_S_TEST_CONFIG
  • HyperThreading : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- i -

  • IccMax : FSP_S_CONFIG
  • IderDeviceEnable : FSP_M_TEST_CONFIG
  • IedSize : FSP_M_CONFIG
  • IgdDvmt50PreAlloc : FSP_M_CONFIG
  • ImonOffset : FSP_S_CONFIG
  • ImonSlope : FSP_S_CONFIG
  • InitPcieAspmAfterOprom : FSP_M_CONFIG
  • InstalledSize : SMBIOS_CACHE_INFO
  • InternalGfx : FSP_M_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • IntX : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Irq : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • IslVrCmd : FSP_S_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- j -

  • JtagC10PowerGateDisable : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- k -

  • KtDeviceEnable : FSP_M_TEST_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- l -

  • LockConfig : GPIO_CONFIG
  • LockPTMregs : FSP_M_TEST_CONFIG
  • LogoPtr : FSP_S_CONFIG
  • LogoSize : FSP_S_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- m -

  • MachineCheckEnable : FSP_S_TEST_CONFIG
  • ManageabilityMode : FSP_S_CONFIG
  • MaxCacheSize : SMBIOS_CACHE_INFO
  • MaxRatio : FSP_S_TEST_CONFIG
  • McPllVoltageOffset : FSP_M_CONFIG
  • MemorySpdDataLen : FSP_M_CONFIG
  • MemorySpdPtr00 : FSP_M_CONFIG
  • MemorySpdPtr01 : FSP_M_CONFIG
  • MemorySpdPtr10 : FSP_M_CONFIG
  • MemorySpdPtr11 : FSP_M_CONFIG
  • MeUnconfigIsValid : FSP_S_CONFIG
  • MeUnconfigOnRtcClear : FSP_S_CONFIG
  • MicrocodePatchAddress : FSP_S_CONFIG
  • MicrocodeRegionBase : FSP_S_CONFIG , FSPT_CORE_UPD
  • MicrocodeRegionSize : FSP_S_CONFIG , FSPT_CORE_UPD
  • MlcSpatialPrefetcher : FSP_S_TEST_CONFIG
  • MlcStreamerPrefetcher : FSP_S_TEST_CONFIG
  • MmaTestConfigPtr : FSP_M_CONFIG
  • MmaTestConfigSize : FSP_M_CONFIG
  • MmaTestContentPtr : FSP_M_CONFIG
  • MmaTestContentSize : FSP_M_CONFIG
  • MmioSize : FSP_M_CONFIG
  • MmioSizeAdjustment : FSP_M_CONFIG
  • ModulePartNum : DIMM_INFO
  • MonitorMwaitEnable : FSP_S_TEST_CONFIG
  • MrcFastBoot : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- n -

  • NModeSupport : FSP_M_CONFIG
  • NumberOfCacheLevels : SMBIOS_CACHE_INFO
  • NumberOfEntries : FSP_S_TEST_CONFIG
  • NumOfDevIntConfig : FSP_S_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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  • OcLock : FSP_M_CONFIG
  • OcSupport : FSP_M_CONFIG
  • OddRatioMode : FSP_M_CONFIG
  • OneCoreRatioLimit : FSP_S_TEST_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputState : GPIO_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- p -

  • PadMode : GPIO_CONFIG
  • PanelPowerEnable : FSP_M_TEST_CONFIG
  • PavpEnable : FSP_S_CONFIG
  • PcdDebugInterfaceFlags : FSP_M_CONFIG
  • PcdIsaSerialUartBase : FSP_M_CONFIG
  • PcdPciExpressBaseAddress : FSP_T_CONFIG
  • PcdPciExpressRegionLength : FSP_T_CONFIG
  • PcdSerialDebugBaudRate : FSP_M_CONFIG
  • PcdSerialDebugLevel : FSP_M_CONFIG
  • PcdSerialIoUartDebugEnable : FSP_T_CONFIG
  • PcdSerialIoUartInputClock : FSP_T_CONFIG
  • PcdSerialIoUartNumber : FSP_M_CONFIG , FSP_T_CONFIG
  • PchAcpiBase : FSP_M_CONFIG
  • PchCio2Enable : FSP_S_CONFIG
  • PchCrid : FSP_S_CONFIG
  • PchDciAutoDetect : FSP_M_TEST_CONFIG
  • PchDciEn : FSP_M_TEST_CONFIG
  • PchDisableComplianceMode : FSP_S_CONFIG
  • PchDmiAspm : FSP_S_CONFIG
  • PchDmiTsawEn : FSP_S_CONFIG
  • PchHdaDspEnable : FSP_S_CONFIG
  • PchHdaDspEndpointBluetooth : FSP_S_CONFIG
  • PchHdaDspEndpointDmic : FSP_S_CONFIG
  • PchHdaDspEndpointI2s : FSP_S_CONFIG
  • PchHdaDspFeatureMask : FSP_S_CONFIG
  • PchHdaDspPpModuleMask : FSP_S_CONFIG
  • PchHdaDspUaaCompliance : FSP_S_CONFIG
  • PchHdaEnable : FSP_S_CONFIG
  • PchHdaIDispCodecDisconnect : FSP_S_CONFIG
  • PchHdaIDispLinkFrequency : FSP_S_CONFIG
  • PchHdaIDispLinkTmode : FSP_S_CONFIG
  • PchHdaIoBufferOwnership : FSP_S_CONFIG
  • PchHdaIoBufferVoltage : FSP_S_CONFIG
  • PchHdaLinkFrequency : FSP_S_CONFIG
  • PchHdaPme : FSP_S_CONFIG
  • PchHdaResetWaitTimer : FSP_S_TEST_CONFIG
  • PchHdaVcType : FSP_S_CONFIG
  • PchHdaVerbTableEntryNum : FSP_S_CONFIG
  • PchHdaVerbTablePtr : FSP_S_CONFIG
  • PchHpetBase : FSP_M_CONFIG
  • PchHpetBdfValid : FSP_M_CONFIG
  • PchHpetBusNumber : FSP_M_CONFIG
  • PchHpetDeviceNumber : FSP_M_CONFIG
  • PchHpetEnable : FSP_M_CONFIG
  • PchHpetFunctionNumber : FSP_M_CONFIG
  • PchIoApicBdfValid : FSP_S_CONFIG
  • PchIoApicBusNumber : FSP_S_CONFIG
  • PchIoApicDeviceNumber : FSP_S_CONFIG
  • PchIoApicEntry24_119 : FSP_S_CONFIG
  • PchIoApicFunctionNumber : FSP_S_CONFIG
  • PchIoApicId : FSP_S_CONFIG
  • PchIoApicRangeSelect : FSP_S_CONFIG
  • PchIshEnable : FSP_S_CONFIG
  • PchIshGp0GpioAssign : FSP_S_CONFIG
  • PchIshGp1GpioAssign : FSP_S_CONFIG
  • PchIshGp2GpioAssign : FSP_S_CONFIG
  • PchIshGp3GpioAssign : FSP_S_CONFIG
  • PchIshGp4GpioAssign : FSP_S_CONFIG
  • PchIshGp5GpioAssign : FSP_S_CONFIG
  • PchIshGp6GpioAssign : FSP_S_CONFIG
  • PchIshGp7GpioAssign : FSP_S_CONFIG
  • PchIshI2c0GpioAssign : FSP_S_CONFIG
  • PchIshI2c1GpioAssign : FSP_S_CONFIG
  • PchIshI2c2GpioAssign : FSP_S_CONFIG
  • PchIshPdtUnlock : FSP_S_CONFIG
  • PchIshSpiGpioAssign : FSP_S_CONFIG
  • PchIshUart0GpioAssign : FSP_S_CONFIG
  • PchIshUart1GpioAssign : FSP_S_CONFIG
  • PchLanClkReqNumber : FSP_S_CONFIG
  • PchLanClkReqSupported : FSP_S_CONFIG
  • PchLanEnable : FSP_S_CONFIG
  • PchLanK1OffEnable : FSP_S_CONFIG
  • PchLanLtrEnable : FSP_S_CONFIG
  • PchLegacyIoLowLatency : FSP_S_CONFIG
  • PchLockDownBiosInterface : FSP_S_TEST_CONFIG
  • PchLockDownBiosLock : FSP_S_CONFIG
  • PchLockDownGlobalSmi : FSP_S_TEST_CONFIG
  • PchLockDownRtcLock : FSP_S_TEST_CONFIG
  • PchLockDownSpiEiss : FSP_S_CONFIG
  • PchLpcEnhancePort8xhDecoding : FSP_M_CONFIG
  • PchMemoryC0TransmitEnable : FSP_S_CONFIG
  • PchMemoryPinSelection : FSP_S_CONFIG
  • PchMemoryPmsyncEnable : FSP_S_CONFIG
  • PchMemoryThrottlingEnable : FSP_S_CONFIG
  • PchNumRsvdSmbusAddresses : FSP_M_CONFIG
  • PchPcieDeviceOverrideTablePtr : FSP_S_CONFIG
  • PchPcieHsioRxSetCtle : FSP_M_CONFIG
  • PchPcieHsioRxSetCtleEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchPciePort8xhDecodePortIndex : FSP_S_TEST_CONFIG
  • PchPmCapsuleResetType : FSP_S_CONFIG
  • PchPmDeepSxPol : FSP_S_CONFIG
  • PchPmDisableDsxAcPresentPulldown : FSP_S_CONFIG
  • PchPmDisableEnergyReport : FSP_S_TEST_CONFIG
  • PchPmDisableNativePowerButton : FSP_S_CONFIG
  • PchPmLanWakeFromDeepSx : FSP_S_CONFIG
  • PchPmLpcClockRun : FSP_S_CONFIG
  • PchPmMeWakeSts : FSP_S_CONFIG
  • PchPmPciePllSsc : FSP_M_CONFIG
  • PchPmPcieWakeFromDeepSx : FSP_S_CONFIG
  • PchPmPmcReadDisable : FSP_S_TEST_CONFIG
  • PchPmPmeB0S5Dis : FSP_S_CONFIG
  • PchPmPwrBtnOverridePeriod : FSP_S_CONFIG
  • PchPmPwrCycDur : FSP_S_CONFIG
  • PchPmSlpAMinAssert : FSP_S_CONFIG
  • PchPmSlpLanLowDc : FSP_S_CONFIG
  • PchPmSlpS0Enable : FSP_S_CONFIG
  • PchPmSlpS0VmEnable : FSP_S_CONFIG
  • PchPmSlpS3MinAssert : FSP_S_CONFIG
  • PchPmSlpS4MinAssert : FSP_S_CONFIG
  • PchPmSlpStrchSusUp : FSP_S_CONFIG
  • PchPmSlpSusMinAssert : FSP_S_CONFIG
  • PchPmWolEnableOverride : FSP_S_CONFIG
  • PchPmWolOvrWkSts : FSP_S_CONFIG
  • PchPmWoWlanDeepSxEnable : FSP_S_CONFIG
  • PchPmWoWlanEnable : FSP_S_CONFIG
  • PchPort61hEnable : FSP_S_CONFIG
  • PchPort80Route : FSP_M_CONFIG
  • PchProtectedRangeBase : FSP_S_CONFIG
  • PchProtectedRangeLimit : FSP_S_CONFIG
  • PchPwrOptEnable : FSP_S_CONFIG
  • PchReadProtectionEnable : FSP_S_CONFIG
  • PchSataHsioRxGen1EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen1EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchSbAccessUnlock : FSP_S_TEST_CONFIG
  • PchSbiUnlock : FSP_S_TEST_CONFIG
  • PchScsEmmcHs400DllDataValid : FSP_S_CONFIG
  • PchScsEmmcHs400DriverStrength : FSP_S_CONFIG
  • PchScsEmmcHs400RxStrobeDll1 : FSP_S_CONFIG
  • PchScsEmmcHs400TuningRequired : FSP_S_CONFIG
  • PchScsEmmcHs400TxDataDll : FSP_S_CONFIG
  • PchSirqEnable : FSP_S_CONFIG
  • PchSirqMode : FSP_S_CONFIG
  • PchSkyCamPortAClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortACtleCapValue : FSP_S_CONFIG
  • PchSkyCamPortACtleEnable : FSP_S_CONFIG
  • PchSkyCamPortACtleResValue : FSP_S_CONFIG
  • PchSkyCamPortADataTrimValue : FSP_S_CONFIG
  • PchSkyCamPortATermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortATrimEnable : FSP_S_CONFIG
  • PchSkyCamPortBClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortBCtleCapValue : FSP_S_CONFIG
  • PchSkyCamPortBCtleEnable : FSP_S_CONFIG
  • PchSkyCamPortBCtleResValue : FSP_S_CONFIG
  • PchSkyCamPortBDataTrimValue : FSP_S_CONFIG
  • PchSkyCamPortBTermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortBTrimEnable : FSP_S_CONFIG
  • PchSkyCamPortCClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortCDCtleCapValue : FSP_S_CONFIG
  • PchSkyCamPortCDCtleEnable : FSP_S_CONFIG
  • PchSkyCamPortCDCtleResValue : FSP_S_CONFIG
  • PchSkyCamPortCDDataTrimValue : FSP_S_CONFIG
  • PchSkyCamPortCTermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortCTrimEnable : FSP_S_CONFIG
  • PchSkyCamPortDClkTrimValue : FSP_S_CONFIG
  • PchSkyCamPortDTermOvrEnable : FSP_S_CONFIG
  • PchSkyCamPortDTrimEnable : FSP_S_CONFIG
  • PchSmbusIoBase : FSP_M_CONFIG
  • PchStartFramePulse : FSP_S_CONFIG
  • PchSubSystemId : FSP_S_CONFIG
  • PchSubSystemVendorId : FSP_S_CONFIG
  • PchT0Level : FSP_S_CONFIG
  • PchT1Level : FSP_S_CONFIG
  • PchT2Level : FSP_S_CONFIG
  • PchTemperatureHotLevel : FSP_S_CONFIG
  • PchThermalDeviceEnable : FSP_S_CONFIG
  • PchTsmicLock : FSP_S_CONFIG
  • PchTTEnable : FSP_S_CONFIG
  • PchTTLock : FSP_S_CONFIG
  • PchTTState13Enable : FSP_S_CONFIG
  • PchWriteProtectionEnable : FSP_S_CONFIG
  • PcieAllowNoLtrIccPllShutdown : FSP_S_CONFIG
  • PcieComplianceTestMode : FSP_S_CONFIG
  • PcieDetectTimeoutMs : FSP_S_CONFIG
  • PcieDisableRootPortClockGating : FSP_S_CONFIG
  • PcieEnablePeerMemoryWrite : FSP_S_CONFIG
  • PcieEnablePort8xhDecode : FSP_S_TEST_CONFIG
  • PcieEqPh3LaneParamCm : FSP_S_CONFIG
  • PcieEqPh3LaneParamCp : FSP_S_CONFIG
  • PcieRpAdvancedErrorReporting : FSP_S_CONFIG
  • PcieRpAspm : FSP_S_CONFIG
  • PcieRpClkReqDetect : FSP_S_CONFIG
  • PcieRpClkReqNumber : FSP_S_CONFIG
  • PcieRpClkReqSupport : FSP_S_CONFIG
  • PcieRpClkSrcNumber : FSP_S_CONFIG
  • PcieRpCompletionTimeout : FSP_S_CONFIG
  • PcieRpCorrectableErrorReport : FSP_S_CONFIG
  • PcieRpDeviceResetPad : FSP_S_CONFIG
  • PcieRpDeviceResetPadActiveHigh : FSP_S_CONFIG
  • PcieRpDptp : FSP_S_TEST_CONFIG
  • PcieRpEnableMask : FSP_M_CONFIG
  • PcieRpExtSync : FSP_S_CONFIG
  • PcieRpFatalErrorReport : FSP_S_CONFIG
  • PcieRpFunctionSwap : FSP_S_CONFIG
  • PcieRpGen3EqPh3Method : FSP_S_CONFIG
  • PcieRpHotPlug : FSP_S_CONFIG
  • PcieRpL1Substates : FSP_S_CONFIG
  • PcieRpLtrConfigLock : FSP_S_CONFIG
  • PcieRpLtrEnable : FSP_S_CONFIG
  • PcieRpLtrMaxNoSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpLtrMaxSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpMaxPayload : FSP_S_CONFIG
  • PcieRpNoFatalErrorReport : FSP_S_CONFIG
  • PcieRpNonSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpPcieSpeed : FSP_S_CONFIG
  • PcieRpPhysicalSlotNumber : FSP_S_CONFIG
  • PcieRpPmSci : FSP_S_CONFIG
  • PcieRpSlotPowerLimitScale : FSP_S_TEST_CONFIG
  • PcieRpSlotPowerLimitValue : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpSystemErrorOnCorrectableError : FSP_S_CONFIG
  • PcieRpSystemErrorOnFatalError : FSP_S_CONFIG
  • PcieRpSystemErrorOnNonFatalError : FSP_S_CONFIG
  • PcieRpTransmitterHalfSwing : FSP_S_CONFIG
  • PcieRpUnsupportedRequestReport : FSP_S_CONFIG
  • PcieRpUptp : FSP_S_TEST_CONFIG
  • PcieSwEqCoeffListCm : FSP_S_CONFIG
  • PcieSwEqCoeffListCp : FSP_S_CONFIG
  • PeciC10Reset : FSP_M_CONFIG
  • PeciSxReset : FSP_M_CONFIG
  • Peg0Enable : FSP_M_CONFIG
  • Peg0Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg0Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg0MaxLinkSpeed : FSP_M_CONFIG
  • Peg0MaxLinkWidth : FSP_M_CONFIG
  • Peg0PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg1Enable : FSP_M_CONFIG
  • Peg1Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg1Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg1MaxLinkSpeed : FSP_M_CONFIG
  • Peg1MaxLinkWidth : FSP_M_CONFIG
  • Peg1PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg2Enable : FSP_M_CONFIG
  • Peg2Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg2Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg2MaxLinkSpeed : FSP_M_CONFIG
  • Peg2MaxLinkWidth : FSP_M_CONFIG
  • Peg2PowerDownUnusedLanes : FSP_M_CONFIG
  • PegDataPtr : FSP_M_CONFIG
  • PegDeEmphasis : FSP_S_CONFIG
  • PegDisableSpreadSpectrumClocking : FSP_M_CONFIG
  • PegGen3EndPointHint : FSP_M_TEST_CONFIG
  • PegGen3EndPointPreset : FSP_M_TEST_CONFIG
  • PegGen3ProgramStaticEq : FSP_M_TEST_CONFIG
  • PegGen3RootPortPreset : FSP_M_TEST_CONFIG
  • PegGen3Rsvd : FSP_M_TEST_CONFIG
  • PegGen3RxCtleOverride : FSP_M_TEST_CONFIG
  • PegGen3RxCtlePeaking : FSP_M_CONFIG
  • PegGenerateBdatMarginTable : FSP_M_TEST_CONFIG
  • PegGpioData : FSP_M_CONFIG
  • PegMaxPayload : FSP_S_TEST_CONFIG
  • PegPhysicalSlotNumber : FSP_S_CONFIG
  • PegRootPortHPE : FSP_M_CONFIG
  • PegRxCemLoopbackLane : FSP_M_TEST_CONFIG
  • PegRxCemNonProtocolAwareness : FSP_M_TEST_CONFIG
  • PegRxCemTestingMode : FSP_M_TEST_CONFIG
  • PegSlotPowerLimitScale : FSP_S_CONFIG
  • PegSlotPowerLimitValue : FSP_S_CONFIG
  • PeiGraphicsPeimInit : FSP_S_CONFIG
  • PkgCStateDemotion : FSP_S_TEST_CONFIG
  • PkgCStateLimit : FSP_S_TEST_CONFIG
  • PkgCStateUnDemotion : FSP_S_TEST_CONFIG
  • PlatformMemorySize : FSP_M_CONFIG
  • PmgCstCfgCtrlLock : FSP_S_TEST_CONFIG
  • PmSupport : FSP_S_TEST_CONFIG
  • PortUsb20Enable : FSP_S_CONFIG
  • PortUsb30Enable : FSP_S_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerLimit1 : FSP_S_TEST_CONFIG
  • PowerLimit1Time : FSP_S_TEST_CONFIG
  • PowerLimit2 : FSP_S_TEST_CONFIG
  • PowerLimit2Power : FSP_S_TEST_CONFIG
  • PowerLimit3 : FSP_S_TEST_CONFIG
  • PowerLimit3DutyCycle : FSP_S_TEST_CONFIG
  • PowerLimit3Lock : FSP_S_TEST_CONFIG
  • PowerLimit3Time : FSP_S_TEST_CONFIG
  • PowerLimit4 : FSP_S_TEST_CONFIG
  • PowerLimit4Lock : FSP_S_TEST_CONFIG
  • PpmIrmSetting : FSP_S_TEST_CONFIG
  • PrimaryDisplay : FSP_M_CONFIG
  • PrmrrSize : FSP_M_CONFIG
  • ProbelessTrace : FSP_M_CONFIG
  • ProcessorCharacteristics : SMBIOS_PROCESSOR_INFO
  • ProcessorFamily : SMBIOS_PROCESSOR_INFO
  • ProcessorId : SMBIOS_PROCESSOR_INFO
  • ProcessorManufacturerStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcessorType : SMBIOS_PROCESSOR_INFO
  • ProcessorUpgrade : SMBIOS_PROCESSOR_INFO
  • ProcessorVersionStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcHotLock : FSP_S_TEST_CONFIG
  • ProcHotResponse : FSP_S_TEST_CONFIG
  • ProcTraceEnable : FSP_S_TEST_CONFIG
  • ProcTraceMemSize : FSP_S_TEST_CONFIG
  • ProcTraceOutputScheme : FSP_S_TEST_CONFIG
  • Psi1Threshold : FSP_S_CONFIG
  • Psi2Threshold : FSP_S_CONFIG
  • Psi3Enable : FSP_S_CONFIG
  • Psi3Threshold : FSP_S_CONFIG
  • Psi4Enable : FSP_S_CONFIG
  • PsysOffset : FSP_S_CONFIG
  • PsysPmax : FSP_S_TEST_CONFIG
  • PsysPowerLimit1 : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Power : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Time : FSP_S_TEST_CONFIG
  • PsysPowerLimit2 : FSP_S_TEST_CONFIG
  • PsysPowerLimit2Power : FSP_S_TEST_CONFIG
  • PsysSlope : FSP_S_CONFIG
  • PxRcConfig : FSP_S_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- r -

  • RaceToHalt : FSP_S_TEST_CONFIG
  • RankInDimm : DIMM_INFO
  • Ratio : FSP_M_CONFIG
  • RcompResistor : FSP_M_CONFIG
  • RcompTarget : FSP_M_CONFIG
  • RealtimeMemoryTiming : FSP_M_CONFIG
  • RefClk : FSP_M_CONFIG
  • RenderStandby : FSP_S_TEST_CONFIG
  • Reserved : AZALIA_HEADER , FSPT_CORE_UPD
  • ReservedCpuPostMemTest : FSP_S_TEST_CONFIG
  • ReservedFspmTestUpd : FSP_M_TEST_CONFIG
  • ReservedFspmUpd : FSP_M_CONFIG
  • ReservedFspsTestUpd : FSP_S_TEST_CONFIG
  • ReservedFspsUpd : FSP_S_CONFIG
  • ReservedFsptUpd1 : FSP_T_CONFIG
  • ReservedSecurityPreMem : FSP_M_CONFIG
  • RevisionId : AZALIA_HEADER
  • RingDownBin : FSP_M_CONFIG
  • RingMaxOcRatio : FSP_M_CONFIG
  • RingMinOcRatio : FSP_M_CONFIG
  • RingPllVoltageOffset : FSP_M_CONFIG
  • RMT : FSP_M_CONFIG
  • RootPortDev : FSP_M_CONFIG
  • RootPortFun : FSP_M_CONFIG
  • RsvdBits : GPIO_CONFIG
  • RsvdSmbusAddressTablePtr : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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  • Variables
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- s -

  • SaGv : FSP_M_CONFIG
  • SaImguEnable : FSP_S_CONFIG
  • SaOcSupport : FSP_M_CONFIG
  • SaPllVoltageOffset : FSP_M_CONFIG
  • SaPostMemProductionRsvd : FSP_S_CONFIG
  • SaPostMemTestRsvd : FSP_S_TEST_CONFIG
  • SaPreMemTestRsvd : FSP_M_TEST_CONFIG
  • SaRtd3Pcie0Gpio : FSP_M_CONFIG
  • SaRtd3Pcie1Gpio : FSP_M_CONFIG
  • SaRtd3Pcie2Gpio : FSP_M_CONFIG
  • SataEnable : FSP_S_CONFIG
  • SataMode : FSP_S_CONFIG
  • SataP0T1M : FSP_S_CONFIG
  • SataP0T2M : FSP_S_CONFIG
  • SataP0T3M : FSP_S_CONFIG
  • SataP0TDisp : FSP_S_CONFIG
  • SataP0TDispFinit : FSP_S_CONFIG
  • SataP0Tinact : FSP_S_CONFIG
  • SataP1T1M : FSP_S_CONFIG
  • SataP1T2M : FSP_S_CONFIG
  • SataP1T3M : FSP_S_CONFIG
  • SataP1TDisp : FSP_S_CONFIG
  • SataP1TDispFinit : FSP_S_CONFIG
  • SataP1Tinact : FSP_S_CONFIG
  • SataPortsDevSlp : FSP_S_CONFIG
  • SataPortsDitoVal : FSP_S_CONFIG
  • SataPortsDmVal : FSP_S_CONFIG
  • SataPortsEnable : FSP_S_CONFIG
  • SataPortsEnableDitoConfig : FSP_S_CONFIG
  • SataPortsExternal : FSP_S_CONFIG
  • SataPortsHotPlug : FSP_S_CONFIG
  • SataPortsInterlockSw : FSP_S_CONFIG
  • SataPortsSolidStateDrive : FSP_S_CONFIG
  • SataPortsSpinUp : FSP_S_CONFIG
  • SataPortsZpOdd : FSP_S_CONFIG
  • SataPwrOptEnable : FSP_S_CONFIG
  • SataRstCpuAttachedStorage : FSP_S_CONFIG
  • SataRstHddUnlock : FSP_S_CONFIG
  • SataRstIrrt : FSP_S_CONFIG
  • SataRstIrrtOnly : FSP_S_CONFIG
  • SataRstLedLocate : FSP_S_CONFIG
  • SataRstOptaneMemory : FSP_S_CONFIG
  • SataRstOromUiBanner : FSP_S_CONFIG
  • SataRstOromUiDelay : FSP_S_CONFIG
  • SataRstPcieDeviceResetDelay : FSP_S_CONFIG
  • SataRstPcieEnable : FSP_S_CONFIG
  • SataRstPcieStoragePort : FSP_S_CONFIG
  • SataRstRaid0 : FSP_S_CONFIG
  • SataRstRaid1 : FSP_S_CONFIG
  • SataRstRaid10 : FSP_S_CONFIG
  • SataRstRaid5 : FSP_S_CONFIG
  • SataRstRaidAlternateId : FSP_S_CONFIG
  • SataRstSmartStorage : FSP_S_CONFIG
  • SataSalpSupport : FSP_S_CONFIG
  • SataSpeedLimit : FSP_S_CONFIG
  • SataTestMode : FSP_S_TEST_CONFIG
  • SataThermalSuggestedSetting : FSP_S_CONFIG
  • SaVoltageOffset : FSP_M_CONFIG
  • ScanExtGfxForLegacyOpRom : FSP_M_TEST_CONFIG
  • SciIrqSelect : FSP_S_CONFIG
  • ScsEmmcEnabled : FSP_S_CONFIG
  • ScsEmmcHs400Enabled : FSP_S_CONFIG
  • ScsSdCardEnabled : FSP_S_CONFIG
  • SdiNum : AZALIA_HEADER
  • SendDidMsg : FSP_M_TEST_CONFIG
  • SendEcCmd : FSP_S_CONFIG
  • SendVrMbxCmd : FSP_S_CONFIG
  • SendVrMbxCmd1 : FSP_S_CONFIG
  • SerialIoDebugUartNumber : FSP_S_CONFIG
  • SerialIoDevMode : FSP_S_CONFIG
  • SerialIoEnableDebugUartAfterPost : FSP_S_CONFIG
  • SerialIoGpio : FSP_S_CONFIG
  • SerialIoI2cVoltage : FSP_S_CONFIG
  • SerialIoSpiCsPolarity : FSP_S_CONFIG
  • SerialIoUartHwFlowCtrl : FSP_S_CONFIG
  • SevenCoreRatioLimit : FSP_S_TEST_CONFIG
  • SgDelayAfterHoldReset : FSP_M_CONFIG
  • SgDelayAfterPwrEn : FSP_M_CONFIG
  • SgxEpoch0 : FSP_S_CONFIG
  • SgxEpoch1 : FSP_S_CONFIG
  • SgxSinitDataFromTpm : FSP_S_TEST_CONFIG
  • SgxSinitNvsData : FSP_S_CONFIG
  • ShowSpiController : FSP_S_CONFIG
  • Signature : FSP_M_TEST_CONFIG , FSP_S_TEST_CONFIG
  • SinitMemorySize : FSP_M_CONFIG
  • SixCoreRatioLimit : FSP_S_TEST_CONFIG
  • SkipExtGfxScan : FSP_M_TEST_CONFIG
  • SkipMbpHob : FSP_M_TEST_CONFIG
  • SkipPamLock : FSP_S_TEST_CONFIG
  • SkipStopPbet : FSP_M_CONFIG
  • SlowSlewRateForGt : FSP_S_CONFIG
  • SlowSlewRateForIa : FSP_S_CONFIG
  • SlowSlewRateForSa : FSP_S_CONFIG
  • SmbusArpEnable : FSP_M_CONFIG
  • SmbusDynamicPowerGating : FSP_M_TEST_CONFIG
  • SmbusEnable : FSP_M_CONFIG
  • SmbusSpdWriteDisable : FSP_M_TEST_CONFIG
  • SmramMask : FSP_M_CONFIG
  • SocketDesignationStrIndex : SMBIOS_CACHE_INFO
  • SpdDramDeviceType : DIMM_INFO
  • SpdModuleMemoryBusWidth : DIMM_INFO
  • SpdModuleType : DIMM_INFO
  • SpdProfileSelected : FSP_M_CONFIG
  • SpdSave : DIMM_INFO
  • SpiFlashCfgLockDown : FSP_S_CONFIG
  • SsicPortEnable : FSP_S_CONFIG
  • StateRatio : FSP_S_TEST_CONFIG
  • Status : DIMM_INFO , SMBIOS_PROCESSOR_INFO
  • SupportedSramType : SMBIOS_CACHE_INFO
  • SystemCacheType : SMBIOS_CACHE_INFO
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- t -

  • TccActivationOffset : FSP_S_TEST_CONFIG
  • TccOffsetClamp : FSP_S_TEST_CONFIG
  • TccOffsetLock : FSP_S_TEST_CONFIG
  • TccOffsetTimeWindowForRatl : FSP_S_TEST_CONFIG
  • tCL : FSP_M_CONFIG
  • TcoIrqEnable : FSP_S_CONFIG
  • TcoIrqSelect : FSP_S_CONFIG
  • tCWL : FSP_M_CONFIG
  • TdcEnable : FSP_S_CONFIG
  • TdcLock : FSP_S_CONFIG
  • TdcPowerLimit : FSP_S_CONFIG
  • TdcTimeWindow : FSP_S_CONFIG
  • tFAW : FSP_M_CONFIG
  • TgaSize : FSP_M_TEST_CONFIG
  • ThermalMonitor : FSP_S_TEST_CONFIG
  • ThreadCount : SMBIOS_PROCESSOR_INFO
  • ThreeCoreRatioLimit : FSP_S_TEST_CONFIG
  • ThreeStrikeCounterDisable : FSP_S_TEST_CONFIG
  • TimedMwait : FSP_S_TEST_CONFIG
  • TjMaxOffset : FSP_M_CONFIG
  • TotalFlashSize : FSP_M_TEST_CONFIG
  • TraceHubMemReg0Size : FSP_M_CONFIG
  • TraceHubMemReg1Size : FSP_M_CONFIG
  • tRAS : FSP_M_CONFIG
  • tRCDtRP : FSP_M_CONFIG
  • tREFI : FSP_M_CONFIG
  • tRFC : FSP_M_CONFIG
  • tRRD : FSP_M_CONFIG
  • tRTP : FSP_M_CONFIG
  • TsegSize : FSP_M_CONFIG
  • TStates : FSP_S_TEST_CONFIG
  • TTCrossThrottling : FSP_S_CONFIG
  • TTSuggestedSetting : FSP_S_CONFIG
  • TurboMode : FSP_S_CONFIG
  • TurboPowerLimitLock : FSP_S_TEST_CONFIG
  • TvbRatioClipping : FSP_M_CONFIG
  • TvbVoltageOptimization : FSP_M_CONFIG
  • TwoCoreRatioLimit : FSP_S_TEST_CONFIG
  • tWR : FSP_M_CONFIG
  • tWTR : FSP_M_CONFIG
  • Txt : FSP_M_CONFIG
  • TxtDprMemoryBase : FSP_M_CONFIG
  • TxtDprMemorySize : FSP_M_CONFIG
  • TxtHeapMemorySize : FSP_M_CONFIG
  • TxtImplemented : FSP_M_CONFIG
  • TxtLcpPdBase : FSP_M_TEST_CONFIG
  • TxtLcpPdSize : FSP_M_TEST_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- u -

  • UnusedUpdSpace0 : FSP_M_CONFIG , FSP_S_CONFIG , FSP_T_CONFIG
  • UnusedUpdSpace1 : FSP_M_CONFIG , FSP_S_CONFIG , FSPT_UPD
  • UnusedUpdSpace10 : FSP_S_CONFIG , FSPM_UPD
  • UnusedUpdSpace11 : FSP_S_CONFIG
  • UnusedUpdSpace12 : FSP_S_CONFIG
  • UnusedUpdSpace13 : FSP_S_CONFIG
  • UnusedUpdSpace14 : FSP_S_CONFIG
  • UnusedUpdSpace15 : FSP_S_CONFIG
  • UnusedUpdSpace16 : FSP_S_CONFIG
  • UnusedUpdSpace17 : FSP_S_CONFIG
  • UnusedUpdSpace18 : FSP_S_CONFIG
  • UnusedUpdSpace19 : FSP_S_CONFIG
  • UnusedUpdSpace2 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace20 : FSP_S_CONFIG
  • UnusedUpdSpace21 : FSP_S_CONFIG
  • UnusedUpdSpace22 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace23 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace24 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace25 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace26 : FSPS_UPD
  • UnusedUpdSpace3 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace4 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace5 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace6 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace7 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace8 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace9 : FSP_M_TEST_CONFIG , FSP_S_CONFIG
  • UpdTerminator : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Usb2AfePehalfbit : FSP_S_CONFIG
  • Usb2AfePetxiset : FSP_S_CONFIG
  • Usb2AfePredeemp : FSP_S_CONFIG
  • Usb2AfeTxiset : FSP_S_CONFIG
  • Usb2OverCurrentPin : FSP_S_CONFIG
  • Usb3HsioTxDeEmph : FSP_S_CONFIG
  • Usb3HsioTxDeEmphEnable : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmp : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmpEnable : FSP_S_CONFIG
  • Usb3OverCurrentPin : FSP_S_CONFIG
  • UserBd : FSP_M_CONFIG
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- v -

  • VddVoltage : FSP_M_CONFIG
  • VendorId : AZALIA_HEADER
  • VmxEnable : FSP_M_CONFIG
  • Voltage : SMBIOS_PROCESSOR_INFO
  • VoltageOptimization : FSP_S_TEST_CONFIG
  • VrConfigEnable : FSP_S_CONFIG
  • VrPowerDeliveryDesign : FSP_S_CONFIG
  • VrVoltageLimit : FSP_S_CONFIG
  • VtdBaseAddress : FSP_S_CONFIG
  • VtdDisable : FSP_S_TEST_CONFIG
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- w -

  • WatchDog : FSP_S_CONFIG
  • WatchDogTimerBios : FSP_S_CONFIG
  • WatchDogTimerOs : FSP_S_CONFIG
  • WdtDisableAndLock : FSP_M_TEST_CONFIG
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  • X2ApicOptOut : FSP_S_CONFIG
  • XdciEnable : FSP_S_CONFIG
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Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: File List

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File List
Here is a list of all documented files with brief descriptions:
CpuConfigFspData.h | FSP CPU Data Config Block
DoxygenFspIntegrationGuide.h | This file contains doxygen KabylakeFspIntegration Guide
FspmUpd.h |
FspsUpd.h |
FsptUpd.h |
FspUpd.h |
GpioConfig.h | Header file for GpioConfig structure used by GPIO library
GpioSampleDef.h |
MemInfoHob.h | This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs
SmbiosCacheInfoHob.h | Header file for SMBIOS Cache Info HOB
SmbiosProcessorInfoHob.h | Header file for SMBIOS Processor Info HOB
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CpuConfigFspData.h File Reference

FSP CPU Data Config Block. More...

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Detailed Description

FSP CPU Data Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuConfigFspData.h.


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1 /** @file
2 FSP CPU Data Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_CONFIG_FSP_DATA_H_
36 #define _CPU_CONFIG_FSP_DATA_H_
37
38 #pragma pack (push,1)
39 typedef union {
40 struct {
41 /**
42 Enable or Disable Advanced Encryption Standard (AES) feature.
43 For some countries, this should be disabled for legal reasons.
44 - 0: Disable
45 - <b>1: Enable</b>
46 **/
47 UINT32 AesEnable : 1;
48 /**
49 Processor Early Power On Configuration FCLK setting.
50 - <b>0: 800 MHz (ULT/ULX)</b>.
51 - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
52 - 2: 400 MHz.
53 - 3: Reserved.
54 **/
55 UINT32 FClkFrequency : 2;
56 UINT32 EnableRsr : 1; ///< Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
57 /**
58 Policies to obtain CPU temperature.
59 - <b>0: ACPI thermal management uses EC reported temperature values</b>.
60 - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.
61 - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.
62 **/
63 UINT32 EnableDts : 2;
64 UINT32 SmmbaseSwSmiNumber : 8; ///< Software SMI number for handler to save CPU information in SMRAM.
65 /**
66 Enable or Disable Virtual Machine Extensions (VMX) feature.
67 - 0: Disable
68 - <b>1: Enable</b>
69 **/
70 UINT32 VmxEnable : 1;
71 /**
72 Enable or Disable Trusted Execution Technology (TXT) feature.
73 - 0: Disable
74 - <b>1: Enable</b>
75 **/
76 UINT32 TxtEnable : 1;
77 UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
78 UINT32 RsvdBits : 15; ///< Reserved for future use
79 UINT32 Reserved;
80 } Bits;
81 UINT32 Uint32[2];
82 } CPU_CONFIG_FSP_DATA;
83
84 #pragma pack (pop)
85
86 #endif // _CPU_CONFIG_FSP_DATA_H_
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: DoxygenFspIntegrationGuide.h File Reference

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DoxygenFspIntegrationGuide.h File Reference

This file contains doxygen KabylakeFspIntegration Guide. More...

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Detailed Description

This file contains doxygen KabylakeFspIntegration Guide.

Copyright
Copyright (c) 2015 - 2018 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file DoxygenFspIntegrationGuide.h.


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1 /** @file
2 This file contains doxygen KabylakeFspIntegration Guide
3
4 @copyright
5 Copyright (c) 2015 - 2018 Intel Corporation. All rights reserved
6 This software and associated documentation (if any) is furnished
7 under a license and may only be used or copied in accordance
8 with the terms of the license. Except as permitted by such
9 license, no part of this software or documentation may be
10 reproduced, stored in a retrieval system, or transmitted in any
11 form or by any means without the express written consent of
12 Intel Corporation.
13 This file contains an 'Intel Peripheral Driver' and uniquely
14 identified as "Intel Reference Module" and is
15 licensed for Intel CPUs and chipsets under the terms of your
16 license agreement with Intel or your vendor. This file may
17 be modified by the user, subject to additional terms of the
18 license agreement
19 **/
20
21 /** @mainpage INTRODUCTION
22
23 # 1 Introduction
24
25 ## 1.1 Purpose
26 The purpose of this document is to describe the steps required to integrate the Intel&reg; Firmware
27 Support Package (FSP) into a boot loader solution. It supports Kabylake platforms with Kabylake/Skylake
28 processor and Sunrise point Platform Controller Hub (PCH).</P>
29
30 ## 1.2 Intended Audience
31 This document is targeted at all platform and system developers who need to consume FSP binaries
32 in their boot loader solutions. This includes, but is not limited to: system BIOS developers, boot
33 loader developers, system integrators, as well as end users.</P>
34
35 ## 1.3 Related Documents
36 - *Platform Initialization (PI) Specification v1.4* located at http://www.uefi.org/specifications
37 - *UEFI Specification v2.5* located at http://www.uefi.org/specifications
38 - *Intel&reg; Firmware Support Package: External Architecture Specification (EAS) v2.0* located at
39 http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf
40 - *Boot Setting File Specification (BSF) v1.0* https://firmware.intel.com/sites/default/files/BSF_1_0.pdf
41 - *Binary Configuration Tool for Intel&reg; Firmware Support Package* available at http://www.intel.com/fsp
42
43 ## 1.4 Acronyms and Terminology
44
45 Acronym | Definition
46 --------|-----------
47 BCT | Binary Configuration Tool
48 BSF | Boot Setting File
49 BSP | Boot Strap Processor
50 BWG | BIOS Writer&apos;s Guide
51 CAR | Cache As Ram
52 CRB | Customer Reference Board
53 FIT | Firmware Interface Table
54 FSP | Firmware Support Package
55 FSP API | Firmware Support Package Interface
56 FW | Firmware
57 PCH | Platform Controller Hub
58 PMC | Power Management Controller
59 SBSP | System BSP
60 SMI | System Management Interrupt
61 SMM | System Management Mode
62 SPI | Serial Peripheral Interface
63 TSEG | Memory Reserved at the Top of Memory to be used as SMRAM
64 UPD | Updatable Product Data
65
66 **/
67
68 /** @page fsp_overview FSP OVERVIEW
69 # FSP Overview
70 ## 2.1 Technical Overview
71 The *Intel&reg; Firmware Support Package (FSP)* provides chipset and processor initialization in a
72 format that can easily be incorporated into many existing boot loaders.
73
74 The FSP will perform the necessary initialization steps as documented in the BWG including
75 initialization of the CPU, memory controller, chipset and certain bus interfaces, if necessary.
76
77 FSP is not a stand-alone boot loader; therefore it needs to be integrated into a host boot loader
78 to carry out other boot loader functions, such as: initializing non-Intel components, conducting
79 bus enumeration, and discovering devices in the system and all industry standard initialization.
80
81 The FSP binary can be integrated easily into many different boot loaders, such as Coreboot, EDKII etc.
82 and also into the embedded OS directly.
83
84 Below are some required steps for the integration:
85
86 - **Customizing**
87 The static FSP configuration parameters are part of the FSP binary and can be customized by external
88 tools that will be provided by Intel.
89
90 - **Rebasing**
91 The FSP is not Position Independent Code (PIC) and the whole FSP has to be rebased if it is placed
92 at a location which is different from the preferred address during build process.
93
94 - **Placing**
95 Once the FSP binary is ready for integration, the boot loader build process needs to be modified to
96 place this FSP binary at the specific rebasing location identified above.
97
98 - **Interfacing**
99 The boot loader needs to add code to setup the operating environment for the FSP, call the FSP with
100 correct parameters and parse the FSP output to retrieve the necessary information returned by the FSP.
101
102 ## 2.2 FSP Distribution Package
103 - The FSP distribution package contains the following:
104 - FSP Binary
105 - FSP Integration Guide
106 - BSF Configuration File
107 - Data Structure Header File
108
109 - The FSP configuration utility called BCT is available as a separate package.
110 It can be downloaded from link mentioned in Section 1.3.
111
112 ### 2.2.1 Package Layout
113 - **Docs (Auto generated)**
114 - Kabylake_FSP_Integration_Guide.pdf (this doc)
115 - Kabylake_FSP_Integration_Guide.chm
116
117 - **Include**
118 - FsptUpd.h, FspmUpd.h and FspsUpd.h (FSP UPD structure and related definitions)
119 - GpioSampleDef.h (Sample enum definitions for Gpio table)
120 - KabylakeFspBinPkg.dec (EDKII declaration file for package)
121 - Fsp.bsf (BSF file for configuring the data using BCT tool)
122 - Fsp.fd (FSP Binary)
123 **/
124
125 /** @page fsp_integration FSP INTEGRATION
126 # 3 FSP Integration
127
128 ## 3.1 Assumptions Used in this Document
129 The FSP for the Kabylake platform is built with a preferred base address of 0xFFF40000 and so the
130 reference code provided in the document assumes that the FSP is placed at this base address during
131 the final boot loader build. Users may rebase the FSP binary at a different location with
132 Intel&apos;s Binary Configuration Tool (BCT) before integrating to the boot loader.
133
134 For other assumptions and conventions, please refer section 8 in the FSP External Architecture
135 Specification version 2.0.
136
137 ## 3.2 Boot Flow
138 Please refer Chapter 7 in the FSP External Architecture Specification version 2.0 for Boot flow chart.
139
140 ## 3.3 FSP INFO Header
141 The FSP has an Information Header that provides critical information that is required by the
142 bootloader to successfully interface with the FSP. The structure of the FSP Information Header
143 is documented in the FSP External Architecture Specification version 2.0 with a HeaderRevision of 3.
144
145 ## 3.4 FSP Image ID and Revision
146 FSP information header contains an Image ID field and an Image Revision field that provide the
147 identification and revision information of the FSP binary. It is important to verify these fields
148 while integrating the FSP as API parameters could change over different FSP IDs and revisions.
149 All the FSP FV segments(FSP-T, FSP-M and FSP-S) must have same FSP Image ID and revision number,
150 using FV segments with different revision numbers in a single FSP image is not valid. The FSP
151 API parameters documented in this integration guide are applicable for the Image ID and
152 Revision specified as below.
153
154 The current FSP ImageId string in the FSP information header is <strong>$KBLFSP$</strong> and the
155 ImageRevision field is **0x03060000.(3.6.0.0)**.
156
157 ## 3.5 FSP Global Data
158 FSP uses some amount of TempRam area to store FSP global data which contains some critical data like
159 pointers to FSP information headers and UPD configuration regions, FSP/Bootloader stack pointers
160 required for stack switching etc. HPET Timer register(2) 0xFED00148 is reserved to store address
161 of this global data, and hence boot loader should not use this register for any other purpose.
162 If TempRAM initialization is done by boot loader, then HPET has to be initialized to the base so
163 that access to this register will work fine.
164
165 ## 3.6 FSP APIs
166 This release of the Kabylake FSP supports the all APIs required by the FSP External
167 Architecture Specification version 2.0.
168 The FSP information header contains the address offset for these APIs. Register usage is
169 described in the FSP External Architecture Specification version 2.0. Any usage not described
170 by the specification is described in the individual sections below.
171
172 The below sections will highlight any changes that are specific to this FSP release.
173
174 ### 3.6.1 TempRamInit API
175 Please refer Chapter 8.5 in the FSP External Architecture Specification version 2.0 for complete
176 details including the prototype, parameters and return value details for this API.
177
178 TempRamInit does basic early initialization primarily setting up temporary RAM using cache. It
179 returns ECX pointing to beginning of temporary memory and EDX pointing to end of temporary memory + 1.
180 The total temporary ram currently available is from 0xFEF0_0000 to 0xFEF4_0000 out of which
181 0xFEF0_0000(ECX) to 0xFEF3_FF00(EDX) is usable area for both bootloader and FSP binary, remaining
182 0x100 bytes of space reserved by FSP for TempRamInit if temporary RAM initialization is done by FSP.
183
184 **TempRamInit** also sets up the code caching of the region passed CodeCacheBase and CodeCacheLength,
185 which are input parameters to TempRamInitApi. if 0 is passed in for CodeCacheBase, the base used will
186 be 4 GB - 1 - length to be code cached instead of starting from CodeCacheBase.
187 @note: when programming MTRR CodeCacheLength will be reduced, if SKU LLC size is smaller than the requested.
188
189 It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to
190 each microcode update. The microcode update is loaded for all logical processors before reset
191 vector. If more than microcode update for the CPU is present, the microcode update with the
192 latest revision is loaded.
193
194 **FSPT_UPD.MicrocodeRegionBase** and **FSPT_UPD.MicrocodeRegionLength** are input parameters to TempRamInit API.
195 If these values are 0, FSP will not attempt to update microcode. If a region is passed, then if a newer
196 microcode update revision is in the region, it will be loaded by the FSP.
197
198 MTRRs are programmed to the default values to have the following memory map:
199
200 Memory range | Cache Attribute
201 ---------------------------------------|-----------------
202 0xFEF00000 - 0x00040000 | Write back
203 CodeCacheBase - CodeCacheLength | Write protect
204
205 ### 3.6.2 FspMemoryInit API
206 Please refer to Chapter 8.6 in the FSP external Architecture Specification version 2.0 for the
207 prototype, parameters and return value details for this API.
208
209 The **FspmUpdPtr** is pointer to **FSPM_UPD** structure which is described in header file FspmUpd.h.
210
211 Boot Loader must pass valid CAR region for FSP stack use through **FSPM_UPD.FspmArchUpd.StackBase**
212 and **FSPM_UPD.FspmArchUpd.StackSize** UPDs.
213
214 The minimum FSP stack size required for this revision of FSP is 160KB, stack base is 0xFEF17F00 by default.
215
216 The base address of HECI device (Bus 0, Device 22, Function 0) is required to be initialized prior
217 to perform FspMemoryInit flow. The default address is programmed to 0xFED1A000.
218
219 Calculate memory map determining memory regions TSEG, IED, GTT, BDSM, ME stolen, Uncore PMRR, IOT,
220 MOT, DPR, REMAP, TOLUD, TOUUD. Programming will be done at a different time.
221
222 #### 3.6.3 TempRamExit API
223 Please refer to Chapter 8.7 in the FSP external Architecture Specification version 2.0 for the
224 prototype, parameters and return value details for this API.
225
226 If Boot Loader initializes the Temporary RAM (CAR) and skip calling **TempRamInit API**, it is expected that
227 bootloader must skip calling this API and bootloader will tear down the temporary memory area setup in the
228 cache and bring the cache to normal mode of operation.
229
230 This revision of FSP doesn't have any fields/structure to pass as parameter for this API.
231 Pass Null for *TempRamExitParamPtr*.
232
233 At the end of *TempRamExit* the original code and data caching are disabled. FSP will reconfigure all MTRRs
234 as described in the table below for performance optimization.
235
236 Memory range | Cache Attribute
237 ---------------------------------------|-----------------
238 0x00000000 - 0x0009FFFF | Write back
239 0x000C0000 - Top of Low Memory | Write back
240 0xFF800000 - 0xFFFFFFFF (Flash region) | Write protect
241 0x1000000000 - Top of High Memory | Write back
242
243 If the boot loader wish to reconfigure the MTRRs differently, it can be overridden immediately after this API call.
244
245 ### 3.6.4 FspSiliconInit API
246 Please refer to Chapter 8.8 in the FSP external Architecture Specification version 2.0 for the
247 prototype, parameters and return value details for this API.
248
249 The *FspsUpdPtr* is pointer to **FSPS_UPD** structure which is described in header file FspsUpd.h.
250
251 It is expected that boot loader will program MTRRs for SBSP as needed after **TempRamExit** but before
252 entering **FspSiliconInit**. If MTRRs are not programmed properly, the boot performance
253 might be impacted.
254
255 The region of 0x5_8000 - 0x5_8FFF is used by FspSilicionInit for starting APs. If this data
256 is important to bootloader, then bootloader needs to preserve it before calling FspSilicionInit.
257
258 It is a requirement for bootloader to have Firmware Interface Table (FIT), which contains pointers
259 to each microcode. The microcode is loaded for all cores before reset vector. If more than one
260 microcode update for the CPU is present, the latest revision is loaded.
261
262 MicrocodeRegionBase and MicrocodeRegionLength are both input parameters to TempRamInit
263 and UPD for SiliconInit API. UPD has priority and will be searched for a later revision
264 than TempRamInit. If MicrocodeRegionBase and MicrocodeRegionLength values are 0, FSP will
265 not attempt to update the microcode. If a microcode region is passed, and if a later
266 revision of microcode is present in this region, FSP will load it.
267
268 FSP initializes PCH audio including selecting HD Audio verb table and initializes Codec.
269
270 PCH required initialization is done for the following HECI, USB, HSIO, Integrated Sensor Hub,
271 Display, Sky Cam, Camera, PCI Express, Vt-d, straps (cores, hyper-threading, BIST, ..)
272
273 FSP initializes CPU features: XD, VMX, AES, IED, HDC, x(2)Apic, Intel&reg; Processor Trace,
274 Three strike counter, Machine check, Cache pre-fetchers, Core PMRR, Power management.
275
276 Initializes HECI, DMI, Internal Graphics. Publish EFI_PEI_GRAPHICS_INFO_HOB during normal boot
277 but this HOB will not be published during S3 resume as FSP will not launch the PEI Graphics PEIM
278 during S3 resume.
279
280 Programs SA Bars: MchBar, DmiBar, EpBar, GdxcBar, EDRAM (if supported). Please refer to section
281 2.8 (MemoryMap) for the corresponding Bar values. GttMmadr (0xDF000000) and GmAdr(0xC0000000)
282 are temporarily programmed and cleared after use in FSP.
283
284 On normal boot CPU S3 Resume Data HOB is produced in this phase. This CPU S3 Resume Data HOB is described
285 in section 4.4. Unless UPD SkipMpInit is enabled, on S3 resume, this data (not the entire HOB) must be passed through
286 UPD CpuS3ResumeData, and optionally final S3 boot MTRRs is passed through UPD CpuS3ResumeMtrrData. During S3
287 resume unless SkipMpInit is enabled, GDT base and length and IDT base and length on APs are programmed
288 to that of the BSP.
289
290 ### 3.6.5 NotifyPhase API
291 Please refer Chapter 8.9 in the FSP External Architecture Specification version 2.0 for the
292 prototype, parameters and return value details for this API.
293
294 #### 3.6.5.1 PostPciEnumeration Notification
295 This phase *EnumInitPhaseAfterPciEnumeration* is to be called after PCI enumeration but before
296 execution of third party code such as option ROMs. Currently, nothing is done in this phase,
297 but in the future updates, programming may be done in this phase.
298
299 #### 3.6.5.2 ReadyToBoot Notification
300 This phase *EnumInitPhaseReadyToBoot* is to be called before giving control to boot. It includes some
301 final initialization steps recommended by the BWG, including power management settings, Send ME Message
302 EOP (End of Post).
303
304 #### 3.6.5.3 EndOfFirmware Notification
305 This phase *EnumInitEndOfFirmware* is to be called before the firmware/preboot environment transfers
306 management of all system resources to the OS or next level execution environment. It includes final locking
307 of chipset registers
308
309 ## 3.7 Memory Map
310 Below diagram represents the memory map allocated by FSP including the FSP specific regions.
311 ![System Memory Map](KabylakeMemoryMap.jpg)
312
313 ## 3.8 Porting recommendation
314 Here listed some notes or recommendation when porting with FSP.
315
316 ### 3.8.1 Locking PAM register
317 FSP 2.0 introduced EndOfFirmware Notify phase callback which is a recommended place for locking PAM registers
318 so FSP by default implemented this way. If it is still too early to lock PAM registers then the PAM locking code
319 inside FSP can be disabled by UPD -> FSP_S_TEST_CONFIG -> SkipPamLock or SA policy -> _SI_PREMEM_POLICY_STRUCT
320 -> SA_MISC_PEI_CONFIG -> SkipPamLock, and platform or wrapper code should do the PAM locking right before booting
321 OS (so do it outside FSP instead) by programming one PCI config space register as below.
322
323 This PAM locking step has to been applied in all boot paths including S3 resume.To lock PAM regsiter:
324
325 ~~~
326 MmioOr32 (B0: D0: F0: Register 0x80, BIT0)
327 ~~~
328
329 ### 3.8.2 Locking SMRAM register
330 Since SMRAM locking is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation, the FSP code by default will not lock it.
331 The platform or FSP Wrapper code should lock SMRAM by below programming step before any 3rd partiy OpRom execution (and should be locked in S3 resume right before OS waking vector).
332 ~~~
333 PciOr8 (B0: D0: F0: Register 0x88, BIT4); Note: it must be programmed by CF8/CFC Standard PCI access mechanism. (MMIO access will not work)
334 ~~~
335
336 ### 3.8.3 Locking SMI register
337 Global SMI bit is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation after SMM configuration. FSP by default will not lock it.
338 Boot loader is responsible for locking below regsiters after SMM configuration.
339 Set AcpiBase + 0x30[0] to 1b to enable global SMI.
340 Set PMC PCI offset A0h[4] = 1b to lock SMI.
341
342 ### 3.8.4 Verify below settings are correct for your platforms
343
344 Settings | Values
345 ---------------------------------|------------------------
346 PCIEXBAR_BASE_ADDRESS | 0xE0000000 -> PciExBar
347 MCH_BASE_ADDRESS | 0xFED10000 -> MchBar
348 DMI_BASE_ADDRESS | 0xFED18000 -> DmiBar
349 EP_BASE_ADDRESS | 0xFED19000 -> EpBar
350 EDRAM_BASE_ADDRESS | 0xFED80000 -> EdramBar
351 DEFAULT_OPTION_ROM_TEMP_BAR | 0x80000000 -> OpRomScanTempMmioBar
352 DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT| 0xC0000000 -> OpRomScanTempMmioLimit
353 @note:\n
354 - It is recommended that you do not change these settings as it may require significant changes to the System Agent reference code.\n
355 - Those memory regions should be reserved from any memory service functions in platform code so it will not cause any conflict when other modules or drivers allocating memory resource.
356 - Boot Loader can use different value for PCIEXBAR_BASE_ADDRESS either by modifying the UPD (under FSP-T) or by overriding the PCIEXBAR (B0:D0:F0:R60h) before calling FspMemoryInit Api.
357 - Boot Loader should avoid using conflicting address when reprogramming PCIEXBAR_BASE_ADDRESS than the recommended one.
358
359 ### 3.8.5 FSP_STATUS_RESET_REQUIRED
360 As per FSP External Architecture Specification version 2.0, Any reset required in the FSP flow will
361 be reported as return status FSP_STATUS_RESET_REQUIREDx by the API.It is the bootloader responsibility to reset the system according to the reset type requested.
362
363 Below table specifies the return status returned by FSP API and the requested reset type.
364
365 FSP_STATUS_RESET_REQUIRED Code | Reset Type requested
366 -------------------------------|----------------------
367 0x40000001 | Cold Reset
368 0x40000002 | Warm Reset
369 0x40000003 | Global Reset - Puts the system to Global reset through Heci or Full Reset through PCH
370 0x40000004 | Reserved
371 0x40000005 | Reserved
372 0x40000006 | Reserved
373 0x40000007 | Reserved
374 0x40000008 | Reserved
375 **/
376 /** @page fsp_output FSP OUTPUT
377 # 4 FSP Output
378 The FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses
379 through initializing the silicon.
380 Please refer to the Platform Initialization (PI) Specification - Volume 3: Shared Architectural
381 Elements specification for PI Architectural HOBs.Please refer Chapter 9 in the FSP External Architecture
382 Specification version 2.0 for details about FSP Architectural HOBs.
383
384 Below section describe the HOBs not covered in the above two specifications.
385
386 ## 4.1 SMRAM Resource Descriptor HOB
387 The FSP will report the system SMRAM T-SEG range through a generic resource HOB if T-SEG is
388 enabled. The owner field of the HOB identifies the owner as T-SEG.
389
390 ~~~
391 #define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
392 { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }
393 ~~~
394
395 ## 4.2 SMBIOS INFO HOB
396 The FSP will report the SMBIOS through a HOB with below GUID. This information can be consumed
397 by the bootloader to produce the SMBIOS tables. These structures are included as part of MemInfoHob.h , SmbiosCacheInfoHob.h & SmbiosProcessorInfoHob.h.
398 Note: The Smbios Cache Info Hob & Smbios Processor Info Hob won't be published on S3 boot.
399 ~~~
400 #define SI_MEMORY_INFO_DATA_HOB_GUID \
401 { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } };
402
403 typedef struct {
404 MrcDimmStatus Status; ///< See MrcDimmStatus for the definition of this field.
405 UINT8 DimmId;
406 UINT32 DimmCapacity; ///< DIMM size in MBytes.
407 UINT16 MfgId;
408 UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
409 UINT8 RankInDimm; ///< The number of ranks in this DIMM.
410 UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
411 UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
412 UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
413 UINT8 SpdSave[MAX_SPD_SAVE_DATA]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
414 } DIMM_INFO;
415
416 typedef struct {
417 UINT8 Status; ///< Indicates whether this channel should be used.
418 UINT8 ChannelId;
419 UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
420 MRC_CH_TIMING Timing[MAX_PROFILE]; ///< The channel timing values.
421 DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
422 } CHANNEL_INFO;
423
424 typedef struct {
425 UINT8 Status; ///< Indicates whether this controller should be used.
426 UINT16 DeviceId; ///< The PCI device id of this memory controller.
427 UINT8 RevisionId; ///< The PCI revision id of this memory controller.
428 UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
429 CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
430 } CONTROLLER_INFO;
431
432 typedef struct {
433 EFI_HOB_GUID_TYPE EfiHobGuidType;
434 UINT8 Revision;
435 UINT16 DataWidth;
436 /// As defined in SMBIOS 3.0 spec
437 /// Section 7.18.2 and Table 75
438 UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
439 UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
440 /// As defined in SMBIOS 3.0 spec
441 /// Section 7.17.3 and Table 72
442 UINT8 ErrorCorrectionType;
443
444 SiMrcVersion Version;
445 UINT32 FreqMax;
446 BOOLEAN EccSupport;
447 UINT8 MemoryProfile;
448 UINT32 TotalPhysicalMemorySize;
449 BOOLEAN XmpProfileEnable;
450 UINT8 Ratio;
451 UINT8 RefClk;
452 UINT32 VddVoltage[MAX_PROFILE];
453 CONTROLLER_INFO Controller[MAX_NODE];
454 } MEMORY_INFO_DATA_HOB;
455
456 #define SI_MEMORY_PLATFORM_DATA_HOB \
457 { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
458
459 typedef struct {
460 UINT8 Revision;
461 UINT8 Reserved[3];
462 UINT32 BootMode;
463 UINT32 TsegSize;
464 UINT32 TsegBase;
465 UINT32 PrmrrSize;
466 UINT32 PrmrrBase;
467 UINT32 GttBase;
468 UINT32 MmioSize;
469 UINT32 PciEBaseAddress;
470 } MEMORY_PLATFORM_DATA;
471
472 typedef struct {
473 EFI_HOB_GUID_TYPE EfiHobGuidType;
474 MEMORY_PLATFORM_DATA Data;
475 UINT8 *Buffer;
476 } MEMORY_PLATFORM_DATA_HOB;
477
478 #define SMBIOS_CACHE_INFO_HOB_GUID \
479 { 0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7} }
480
481 ///
482 /// SMBIOS Cache Info HOB Structure
483 ///
484 typedef struct {
485 UINT16 ProcessorSocketNumber;
486 UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
487 UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
488 UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
489 UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
490 UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
491 UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
492 UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
493 UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
494 UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
495 UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
496 UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
497 ///String Buffer - each string terminated by NULL "0x00"
498 ///String buffer terminated by double NULL "0x0000"
499 } SMBIOS_CACHE_INFO;
500
501 #define SMBIOS_PROCESSOR_INFO_HOB_GUID \
502 { 0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71} }
503 ///
504 /// SMBIOS Processor Info HOB Structure
505 ///
506 typedef struct {
507 UINT16 TotalNumberOfSockets;
508 UINT16 CurrentSocketNumber;
509 UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
510 ///This info is used for both ProcessorFamily and ProcessorFamily2 fields
511 ///See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
512 UINT16 ProcessorFamily;
513 UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
514 UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
515 UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
516 UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
517 UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
518 UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
519 UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
520 UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
521 ///This info is used for both CoreCount & CoreCount2 fields
522 /// See detailed description in SMBIOS Spec v3.0 Section 7.5.6
523 UINT16 CoreCount;
524 ///This info is used for both CoreEnabled & CoreEnabled2 fields
525 ///See detailed description in SMBIOS Spec v3.0 Section 7.5.7
526 UINT16 EnabledCoreCount;
527 ///This info is used for both ThreadCount & ThreadCount2 fields
528 /// See detailed description in SMBIOS Spec v3.0 Section 7.5.8
529 UINT16 ThreadCount;
530 UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
531 /// String Buffer - each string terminated by NULL "0x00"
532 /// String buffer terminated by double NULL "0x0000"
533 } SMBIOS_PROCESSOR_INFO;
534 ~~~
535
536 ## 4.3 CHIPSETINIT INFO HOB
537 The FSP will report the ChipsetInit CRC through a HOB with below GUID. This information can be consumed
538 by the bootloader to check if ChipsetInit CRC is matched between BIOS and ME. These structures are included
539 as part of FspsUpd.h
540
541 ~~~
542 #define CHIPSETINIT_INFO_HOB_GUID \
543 { 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
544
545 ///
546 /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
547 ///
548 typedef struct {
549 UINT8 Revision;
550 UINT8 Rsvd[3];
551 UINT16 MeChipInitCrc;
552 UINT16 BiosChipInitCrc;
553 } CHIPSET_INIT_INFO;
554
555 ~~~
556
557 ## 4.4 CPU S3 Resume Data HOB
558 The FSP will report the CPU S3 Resume Data through a GUIDED HOB with below GUID. This data (not the entire HOB) must be passed during S3 resume passed
559 in UPD CpuS3ResumeData except if UPD SkipMpInit is enabled.
560
561 ~~~
562 #define CPU_S3_RESUME_DATA_HOB_GUID \
563 { 0x3972d4c1, 0xf206, 0x463f, { 0x80, 0xa4, 0xd9, 0x62, 0x79, 0x0a, 0xe5, 0x49 }}
564 ~~~
565
566 **/
567 /** @page fsp_postcode FSP POSTCODE
568 # 5 FSP PostCode
569 The FSP outputs 16 bit postcode to indicate which API and in which module the execution is happening.
570
571 Bit Range | Description
572 -------------------|------------
573 Bit15 - Bit12 (X) | used to indicate the phase/api under which the code is executing
574 Bit11 - Bit8 (Y) | used to indicate the module
575 Bit7 (ZZ bit 7) | reserved for error
576 Bit6 - Bit0 (ZZ) | individual codes
577
578 ## 5.1 PostCode Info
579 Below diagram represents the 16 bit PostCode usage in FSP.
580
581 @dot
582 digraph structs {
583 node [shape=record, width=3, height=1];
584 struct1 [style=bold,label="<f0> X|<f1> Y|<f2> ZZ"];
585 struct2 [label="<f0> FSP API - 4 BITS (one Digit)\n
586 F - Tempraminit /SEC \l
587 E - Reserved \l
588 D - MemoryInit /Pre-Memory \l
589 C - Reserved \l
590 B - Tempramexit \l
591 A - Reserved \l
592 9 - SiliconInit /Post Memory \l
593 8 - Reserved \l
594 7 - Reserved \l
595 6 - Notify / Post PCIE Enumeration \l
596 5 - Reserved \l
597 4 - Notify / Ready To Boot \l
598 3 - Reserved \l
599 2 - Notify / End Of Firmware \l
600 1-0 - Reserved\l"];
601 struct3 [label="<f0> Module - 4 BITS (one digit)\n
602 7 - Gfx PEIM \l
603 8 - FSP Common Code \l
604 9 - Silicon Common Code \l
605 A - System Agent \l
606 B - PCH \l
607 C - CPU \l
608 D - MRC \l
609 E - ME-BIOS \l
610 F - Reserved \l
611 "];
612 struct4 [label="<f0>Individual Codes\n
613 0x00 - API Entry \l
614 0x7F - API Exit \l
615
616 (Bit7 reserved for error)\l
617 "];
618 struct1:f0 -> struct2:f0;
619 struct1:f1 -> struct3:f0;
620 struct1:f2 -> struct4:f0;
621 }
622 @enddot
623
624
625 ### 5.1.1 TempRamInit API Status Codes (0xFxxx)
626
627 PostCode | Module | Description
628 ---------|--------|-----------------
629 0x0000 | FSP | TempRamInit API Entry (The change in upper byte is due to not enabling of the Port81 early in the boot)
630 0x007F | FSP | TempRamInit API Exit
631
632 ### 5.1.2 FspMemoryInit API Status Codes (0xDxxx)
633
634 PostCode | Module | Description
635 ---------|--------|-----------------
636 0xD800 | FSP | FspMemoryInit API Entry
637 0xD87F | FSP | FSpMemoryInit API Exit
638 0xDA00 | SA | Pre-Mem SaInit Entry
639 0xDA01 | SA | DeviceConfigurePreMem Start
640 0xDA02 | SA | OverrideDev0Did Start
641 0xDA04 | SA | OverrideDev2Did Start
642 0xDA06 | SA | Programming SA Bars
643 0xDA08 | SA | Install SA HOBs
644 0xDA0A | SA | Reporting SA PCIe code version
645 0xDA0C | SA | SaSvInit Start
646 0xDA10 | SA | Initializing DMI
647 0xDA1F | SA | Initializing DMI/OPI Max PayLoad Size
648 0xDA20 | SA | Initializing SwitchableGraphics
649 0xDA30 | SA | Initializing SA PCIe
650 0xDA3F | SA | Programming PEG credit values Start
651 0xDA40 | SA | Initializing DMI Tc/Vc mapping
652 0xDA42 | SA | CheckOffboardPcieVga
653 0xDA44 | SA | CheckAndInitializePegVga
654 0xDA50 | SA | Initializing Graphics
655 0xDA7F | SA | Pre-Mem SaInit Exit
656 0xDB00 | PCH | PCH API Entry
657 0xDC00 | CPU | Pre-Mem Entry
658 0xDC7F | CPU | Pre-Mem Exit
659
660 ### 5.1.3 TempRamExit API Status Codes (0xBxxx)
661
662 PostCode | Module | Description
663 ---------|--------|-----------------
664 0xB800 | FSP | TempRamExit API Entry
665 0xB87F | FSP | TempRamExit API Exit
666
667 ### 5.1.3 FspSiliconInit API Status Codes (0x9xxx)
668
669 PostCode | Module | Description
670 ---------|--------|-----------------
671 0x9800 | FSP | FspSiliconInit API Entry
672 0x987F | FSP | FspSiliconInit API Exit
673 0x9A00 | SA | Post-Mem SaInit Entry
674 0x9A01 | SA | DeviceConfigure Start
675 0x9A02 | SA | UpdateSaHobPostMem Start
676 0x9A03 | SA | Initializing Pei Display
677 0x9A04 | SA | PeiGraphicsNotifyCallback Entry
678 0x9A05 | SA | CallPpiAndFillFrameBuffer
679 0x9A06 | SA | GraphicsPpiInit
680 0x9A07 | SA | GraphicsPpiGetMode
681 0x9A08 | SA | FillFrameBufferAndShowLogo
682 0x9A0F | SA | PeiGraphicsNotifyCallback Exit
683 0x9A10 | SA | Initializing SA Overclocking
684 0x9A14 | SA | Initializing SA SkyCam device
685 0x9A16 | SA | Initializing SA GMM device
686 0x9A18 | SA | Internal Device and Misc Configurations
687 0x9A1A | SA | SaProgramLlcWays Start
688 0x9A20 | SA | Initializing PciExpressInitPostMem
689 0x9A30 | SA | Initializing Vtd
690 0x9A32 | SA | Initializing Pavp
691 0x9A34 | SA | PeiInstallSmmAccessPpi Start
692 0x9A36 | SA | EdramWa Start
693 0x9A4F | SA | Post-Mem SaInit Exit
694 0x9A50 | SA | SaSecurityLock Start
695 0x9A5F | SA | SaSecurityLock End
696 0x9A60 | SA | SaSResetComplete Entry
697 0x9A61 | SA | Set BIOS_RESET_CPL to indicate all configurations complete
698 0x9A62 | SA | SaSvInit2 Start
699 0x9A63 | SA | GraphicsPmInit Start
700 0x9A64 | SA | SaPeiPolicyDump Start
701 0x9A6F | SA | SaSResetComplete Exit
702 0x9A70 | SA | SaS3ResumeAtEndOfPei Callback Entry
703 0x9A7F | SA | SaS3ResumeAtEndOfPei Callback Exit
704 0x9B7F | PCH | Post-Mem ScInit Entry
705 0x9B01 | PCH | Post-Mem Program HSIO ModPHY settings
706 0x9B02 | PCH | Post-Mem SMBus configuration
707 0x9B03 | PCH | Post-Mem LPC configuration
708 0x9B04 | PCH | Post-Mem SATA initizalization
709 0x9B05 | PCH | Post-Mem PCIe initizalization
710 0x9B06 | PCH | Post-Mem xHCI initizalization
711 0x9B07 | PCH | Post-Mem xDCI initizalization
712 0x9B08 | PCH | Post-Mem HD Audio initizalization
713 0x9B09 | PCH | Post-Mem GMM configuration
714 0x9B0A | PCH | Post-Mem LPSS initizalization
715 0x9B0B | PCH | Post-Mem SCS initizalization
716 0x9B0C | PCH | Post-Mem ISH initizalization
717 0x9B0D | PCH | Post-Mem ITSS configuration
718 0x9B40 | PCH | Post-Mem OnEndOfPEI Entry
719 0x9B4F | PCH | Post-Mem OnEndOfPEI Exit
720 0x9B7F | PCH | Post-Mem ScInit Exit
721 0x9C00 | CPU | Post-Mem Entry
722 0x9C7F | CPU | Post-Mem Exit
723
724 ### 5.1.4 NotifyPhase API Status Codes (0x6xxx)
725
726 PostCode | Module | Description
727 ---------|--------|-----------------
728 0x6800 | FSP | NotifyPhase API Entry
729 0x687F | FSP | NotifyPhase API Exit
730
731 **/


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FspmUpd.h File Reference

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FspmUpd.h File Reference
#include <FspUpd.h>
#include <MemInfoHob.h>
Include dependency graph for FspmUpd.h:
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Classes

struct | SI_CHIPSET_INIT_INFO
The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. More...
struct | FSP_M_CONFIG
Fsp M Configuration. More...
struct | FSP_M_TEST_CONFIG
Fsp M Test Configuration. More...
struct | FSPM_UPD
Fsp M UPD Configuration. More...

Detailed Description

Copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FspmUpd.h.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FspmUpd.h Source File

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1 /** @file
2
3 @copyright
4 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
5
6 Redistribution and use in source and binary forms, with or without modification,
7 are permitted provided that the following conditions are met:
8
9 * Redistributions of source code must retain the above copyright notice, this
10 list of conditions and the following disclaimer.
11 * Redistributions in binary form must reproduce the above copyright notice, this
12 list of conditions and the following disclaimer in the documentation and/or
13 other materials provided with the distribution.
14 * Neither the name of Intel Corporation nor the names of its contributors may
15 be used to endorse or promote products derived from this software without
16 specific prior written permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 THE POSSIBILITY OF SUCH DAMAGE.
29
30 This file is automatically generated. Please do NOT modify !!!
31
32 **/
33
34 #ifndef __FSPMUPD_H__
35 #define __FSPMUPD_H__
36
37 #include <FspUpd.h>
38
39 #pragma pack(1)
40
41
42 #include <MemInfoHob.h>
43
44 ///
45 /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
46 ///
47 typedef struct {
48 UINT8 Revision;
49 UINT8 Rsvd[3];
50 UINT16 MeChipInitCrc;
51 UINT16 BiosChipInitCrc;
52 } SI_CHIPSET_INIT_INFO;
53
54
55 /** Fsp M Configuration
56 **/
57 typedef struct {
58
59 /** Offset 0x0040 - Platform Reserved Memory Size
60 The minimum platform memory size required to pass control into DXE
61 **/
62 UINT64 PlatformMemorySize;
63
64 /** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0
65 Pointer to SPD data in Memory
66 **/
67 UINT32 MemorySpdPtr00;
68
69 /** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1
70 Pointer to SPD data in Memory
71 **/
72 UINT32 MemorySpdPtr01;
73
74 /** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0
75 Pointer to SPD data in Memory
76 **/
77 UINT32 MemorySpdPtr10;
78
79 /** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1
80 Pointer to SPD data in Memory
81 **/
82 UINT32 MemorySpdPtr11;
83
84 /** Offset 0x0058 - SPD Data Length
85 Length of SPD Data
86 0x100:256 Bytes, 0x200:512 Bytes
87 **/
88 UINT16 MemorySpdDataLen;
89
90 /** Offset 0x005A - Dq Byte Map CH0
91 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
92 **/
93 UINT8 DqByteMapCh0[12];
94
95 /** Offset 0x0066 - Dq Byte Map CH1
96 Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
97 **/
98 UINT8 DqByteMapCh1[12];
99
100 /** Offset 0x0072 - Dqs Map CPU to DRAM CH 0
101 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
102 **/
103 UINT8 DqsMapCpu2DramCh0[8];
104
105 /** Offset 0x007A - Dqs Map CPU to DRAM CH 1
106 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
107 **/
108 UINT8 DqsMapCpu2DramCh1[8];
109
110 /** Offset 0x0082 - RcompResister settings
111 Indicates RcompReister settings: Board-dependent
112 **/
113 UINT16 RcompResistor[3];
114
115 /** Offset 0x0088 - RcompTarget settings
116 RcompTarget settings: board-dependent
117 **/
118 UINT16 RcompTarget[5];
119
120 /** Offset 0x0092 - Dqs Pins Interleaved Setting
121 Indicates DqPinsInterleaved setting: board-dependent
122 $EN_DIS
123 **/
124 UINT8 DqPinsInterleaved;
125
126 /** Offset 0x0093 - VREF_CA
127 CA Vref routing: board-dependent
128 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
129 2:VREF_CA to CH_A and VREF_DQ_B to CH_B
130 **/
131 UINT8 CaVrefConfig;
132
133 /** Offset 0x0094 - Smram Mask
134 The SMM Regions AB-SEG and/or H-SEG reserved
135 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
136 **/
137 UINT8 SmramMask;
138
139 /** Offset 0x0095 - MRC Fast Boot
140 Enables/Disable the MRC fast path thru the MRC
141 $EN_DIS
142 **/
143 UINT8 MrcFastBoot;
144
145 /** Offset 0x0096
146 **/
147 UINT8 UnusedUpdSpace0[2];
148
149 /** Offset 0x0098 - Intel Enhanced Debug
150 Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
151 0 : Disable, 0x400000 : Enable
152 **/
153 UINT32 IedSize;
154
155 /** Offset 0x009C - Tseg Size
156 Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
157 0x0400000:4MB, 0x01000000:16MB
158 **/
159 UINT32 TsegSize;
160
161 /** Offset 0x00A0 - MMIO Size
162 Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
163 **/
164 UINT16 MmioSize;
165
166 /** Offset 0x00A2 - Probeless Trace
167 Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
168 This also requires IED to be enabled.
169 $EN_DIS
170 **/
171 UINT8 ProbelessTrace;
172
173 /** Offset 0x00A3
174 **/
175 UINT8 UnusedUpdSpace1[2];
176
177 /** Offset 0x00A5 - Enable SMBus
178 Enable/disable SMBus controller.
179 $EN_DIS
180 **/
181 UINT8 SmbusEnable;
182
183 /** Offset 0x00A6 - Enable Trace Hub
184 Enable/disable Trace Hub function.
185 $EN_DIS
186 **/
187 UINT8 EnableTraceHub;
188
189 /** Offset 0x00A7
190 **/
191 UINT8 UnusedUpdSpace2[60];
192
193 /** Offset 0x00E3 - Internal Graphics Pre-allocated Memory
194 Size of memory preallocated for internal graphics.
195 0x00:0 MB, 0x01:32 MB, 0x02:64 MB
196 **/
197 UINT8 IgdDvmt50PreAlloc;
198
199 /** Offset 0x00E4 - Internal Graphics
200 Enable/disable internal graphics.
201 $EN_DIS
202 **/
203 UINT8 InternalGfx;
204
205 /** Offset 0x00E5 - Aperture Size
206 Select the Aperture Size.
207 0:128 MB, 1:256 MB, 2:512 MB
208 **/
209 UINT8 ApertureSize;
210
211 /** Offset 0x00E6 - SA GV
212 System Agent dynamic frequency support and when enabled memory will be training
213 at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
214 2=FixedHigh, and 3=Enabled.
215 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
216 **/
217 UINT8 SaGv;
218
219 /** Offset 0x00E7 - Rank Margin Tool
220 Enable/disable Rank Margin Tool.
221 $EN_DIS
222 **/
223 UINT8 RMT;
224
225 /** Offset 0x00E8 - DDR Frequency Limit
226 Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
227 2133, 2400 and 0 for Auto.
228 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto
229 **/
230 UINT16 DdrFreqLimit;
231
232 /** Offset 0x00EA - Board Type
233 MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
234 Halo, 7=UP Server
235 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
236 **/
237 UINT8 UserBd;
238
239 /** Offset 0x00EB
240 **/
241 UINT8 UnusedUpdSpace3[105];
242
243 /** Offset 0x0154 - MMA Test Content Pointer
244 Pointer to MMA Test Content in Memory
245 **/
246 UINT32 MmaTestContentPtr;
247
248 /** Offset 0x0158 - MMA Test Content Size
249 Size of MMA Test Content in Memory
250 **/
251 UINT32 MmaTestContentSize;
252
253 /** Offset 0x015C - MMA Test Config Pointer
254 Pointer to MMA Test Config in Memory
255 **/
256 UINT32 MmaTestConfigPtr;
257
258 /** Offset 0x0160 - MMA Test Config Size
259 Size of MMA Test Config in Memory
260 **/
261 UINT32 MmaTestConfigSize;
262
263 /** Offset 0x0164
264 **/
265 UINT8 UnusedUpdSpace4[19];
266
267 /** Offset 0x0177 - SPD Profile Selected
268 Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
269 Profile 1, 3=XMP Profile 2
270 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
271 **/
272 UINT8 SpdProfileSelected;
273
274 /** Offset 0x0178 - Memory Voltage
275 Memory Voltage Override (Vddq). Default = no override
276 0:Default, 1100:1.10 Volts, 1150:1.15 Volts, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30
277 Volts, 1350:1.35 Volts, 1400:1.40 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55
278 Volts, 1600:1.60 Volts, 1650:1.65 Volts
279 **/
280 UINT16 VddVoltage;
281
282 /** Offset 0x017A - Memory Reference Clock
283 Automatic, 100MHz, 133MHz.
284 0:Auto, 1:133MHz, 2:100MHz
285 **/
286 UINT8 RefClk;
287
288 /** Offset 0x017B - Memory Ratio
289 Automatic or the frequency will equal ratio times reference clock. Set to Auto to
290 recalculate memory timings listed below.
291 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
292 **/
293 UINT8 Ratio;
294
295 /** Offset 0x017C - QCLK Odd Ratio
296 Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
297 $EN_DIS
298 **/
299 UINT8 OddRatioMode;
300
301 /** Offset 0x017D - tCL
302 CAS Latency, 0: AUTO, max: 31
303 **/
304 UINT8 tCL;
305
306 /** Offset 0x017E - tFAW
307 Min Four Activate Window Delay Time, 0: AUTO, max: 63
308 **/
309 UINT16 tFAW;
310
311 /** Offset 0x0180 - tRAS
312 RAS Active Time, 0: AUTO, max: 64
313 **/
314 UINT16 tRAS;
315
316 /** Offset 0x0182 - tCWL
317 Min CAS Write Latency Delay Time, 0: AUTO, max: 20
318 **/
319 UINT8 tCWL;
320
321 /** Offset 0x0183 - tRCD/tRP
322 RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
323 **/
324 UINT8 tRCDtRP;
325
326 /** Offset 0x0184 - tREFI
327 Refresh Interval, 0: AUTO, max: 65535
328 **/
329 UINT16 tREFI;
330
331 /** Offset 0x0186 - tRFC
332 Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
333 **/
334 UINT16 tRFC;
335
336 /** Offset 0x0188 - tRRD
337 Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
338 **/
339 UINT8 tRRD;
340
341 /** Offset 0x0189 - tRTP
342 Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
343 values: 5, 6, 7, 8, 9, 10, 12
344 **/
345 UINT8 tRTP;
346
347 /** Offset 0x018A - tWR
348 Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24
349 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24
350 **/
351 UINT8 tWR;
352
353 /** Offset 0x018B - tWTR
354 Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
355 **/
356 UINT8 tWTR;
357
358 /** Offset 0x018C - NMode
359 System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
360 **/
361 UINT8 NModeSupport;
362
363 /** Offset 0x018D - DllBwEn[0]
364 DllBwEn[0], for 1067 (0..7)
365 **/
366 UINT8 DllBwEn0;
367
368 /** Offset 0x018E - DllBwEn[1]
369 DllBwEn[1], for 1333 (0..7)
370 **/
371 UINT8 DllBwEn1;
372
373 /** Offset 0x018F - DllBwEn[2]
374 DllBwEn[2], for 1600 (0..7)
375 **/
376 UINT8 DllBwEn2;
377
378 /** Offset 0x0190 - DllBwEn[3]
379 DllBwEn[3], for 1867 and up (0..7)
380 **/
381 UINT8 DllBwEn3;
382
383 /** Offset 0x0191 - Command Tristate Support
384 Enable/Disable Command Tristate; <b>0: Enable</b>; 1: Disable.
385 $EN_DIS
386 **/
387 UINT8 CmdTriStateDis;
388
389 /** Offset 0x0192
390 **/
391 UINT8 UnusedUpdSpace5[14];
392
393 /** Offset 0x01A0 - HECI1 BAR address
394 BAR address of HECI1
395 **/
396 UINT32 Heci1BarAddress;
397
398 /** Offset 0x01A4 - HECI2 BAR address
399 BAR address of HECI2
400 **/
401 UINT32 Heci2BarAddress;
402
403 /** Offset 0x01A8 - HECI3 BAR address
404 BAR address of HECI3
405 **/
406 UINT32 Heci3BarAddress;
407
408 /** Offset 0x01AC - HECI Timeouts
409 Enable/Disable. 0: Disable, disable timeout check for HECI, 1: enable
410 $EN_DIS
411 **/
412 UINT8 HeciTimeouts;
413
414 /** Offset 0x01AD
415 **/
416 UINT8 UnusedUpdSpace6[115];
417
418 /** Offset 0x0220 - SG dGPU Power Delay
419 SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
420 300=300 microseconds
421 **/
422 UINT16 SgDelayAfterPwrEn;
423
424 /** Offset 0x0222 - SG dGPU Reset Delay
425 SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
426 microseconds
427 **/
428 UINT16 SgDelayAfterHoldReset;
429
430 /** Offset 0x0224 - MMIO size adjustment for AUTO mode
431 Positive number means increasing MMIO size, Negative value means decreasing MMIO
432 size: 0 (Default)=no change to AUTO mode MMIO size
433 **/
434 UINT16 MmioSizeAdjustment;
435
436 /** Offset 0x0226 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
437 Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
438 Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
439 $EN_DIS
440 **/
441 UINT8 DmiGen3ProgramStaticEq;
442
443 /** Offset 0x0227 - Enable/Disable PEG 0
444 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
445 it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
446 0:Disable, 1:Enable, 2:AUTO
447 **/
448 UINT8 Peg0Enable;
449
450 /** Offset 0x0228 - Enable/Disable PEG 1
451 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
452 it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
453 0:Disable, 1:Enable, 2:AUTO
454 **/
455 UINT8 Peg1Enable;
456
457 /** Offset 0x0229 - Enable/Disable PEG 2
458 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
459 it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
460 0:Disable, 1:Enable, 2:AUTO
461 **/
462 UINT8 Peg2Enable;
463
464 /** Offset 0x022A - PEG 0 Max Link Speed
465 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
466 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
467 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
468 **/
469 UINT8 Peg0MaxLinkSpeed;
470
471 /** Offset 0x022B - PEG 1 Max Link Speed
472 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
473 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
474 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
475 **/
476 UINT8 Peg1MaxLinkSpeed;
477
478 /** Offset 0x022C - PEG 2 Max Link Speed
479 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
480 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
481 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
482 **/
483 UINT8 Peg2MaxLinkSpeed;
484
485 /** Offset 0x022D - PEG 0 Max Link Width
486 Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
487 Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
488 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
489 **/
490 UINT8 Peg0MaxLinkWidth;
491
492 /** Offset 0x022E - PEG 1 Max Link Width
493 Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
494 Limit Link to x2, (0x3):Limit Link to x4
495 0:Auto, 1:x1, 2:x2, 3:x4
496 **/
497 UINT8 Peg1MaxLinkWidth;
498
499 /** Offset 0x022F - PEG 2 Max Link Width
500 Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
501 Limit Link to x2
502 0:Auto, 1:x1, 2:x2
503 **/
504 UINT8 Peg2MaxLinkWidth;
505
506 /** Offset 0x0230 - Power down unused lanes on PEG 0
507 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
508 on the max possible link width
509 0:No power saving, 1:Auto
510 **/
511 UINT8 Peg0PowerDownUnusedLanes;
512
513 /** Offset 0x0231 - Power down unused lanes on PEG 1
514 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
515 on the max possible link width
516 0:No power saving, 1:Auto
517 **/
518 UINT8 Peg1PowerDownUnusedLanes;
519
520 /** Offset 0x0232 - Power down unused lanes on PEG 2
521 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
522 on the max possible link width
523 0:No power saving, 1:Auto
524 **/
525 UINT8 Peg2PowerDownUnusedLanes;
526
527 /** Offset 0x0233 - PCIe ASPM programming will happen in relation to the Oprom
528 Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
529 Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
530 Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
531 0:Before, 1:After
532 **/
533 UINT8 InitPcieAspmAfterOprom;
534
535 /** Offset 0x0234 - PCIe Disable Spread Spectrum Clocking
536 PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
537 Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
538 0:Normal Operation, 1:Disable SSC
539 **/
540 UINT8 PegDisableSpreadSpectrumClocking;
541
542 /** Offset 0x0235 - DMI Gen3 Root port preset values per lane
543 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane
544 **/
545 UINT8 DmiGen3RootPortPreset[4];
546
547 /** Offset 0x0239 - DMI Gen3 End port preset values per lane
548 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
549 **/
550 UINT8 DmiGen3EndPointPreset[4];
551
552 /** Offset 0x023D - DMI Gen3 End port Hint values per lane
553 Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
554 **/
555 UINT8 DmiGen3EndPointHint[4];
556
557 /** Offset 0x0241 - DMI Gen3 RxCTLEp per-Bundle control
558 Range: 0-15, 3 is default for each bundle, must be specified based upon platform design
559 **/
560 UINT8 DmiGen3RxCtlePeaking[2];
561
562 /** Offset 0x0243 - DeEmphasis control for DMI
563 DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
564 0: -6dB, 1: -3.5dB
565 **/
566 UINT8 DmiDeEmphasis;
567
568 /** Offset 0x0244 - PEG Gen3 RxCTLEp per-Bundle control
569 Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
570 **/
571 UINT8 PegGen3RxCtlePeaking[8];
572
573 /** Offset 0x024C - Memory data pointer for saved preset search results
574 The reference code will store the Gen3 Preset Search results in the SaDataHob's
575 PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
576 skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
577 **/
578 UINT32 PegDataPtr;
579
580 /** Offset 0x0250 - PEG PERST# GPIO information
581 The reference code will use the information in this structure in order to reset
582 PCIe Gen3 devices during equalization, if necessary
583 **/
584 UINT8 PegGpioData[16];
585
586 /** Offset 0x0260
587 **/
588 UINT8 UnusedUpdSpace7[1];
589
590 /** Offset 0x0261 - PCIe Hot Plug Enable/Disable per port
591 0(Default): Disable, 1: Enable
592 **/
593 UINT8 PegRootPortHPE[3];
594
595 /** Offset 0x0264 - Temporary MMIO address for GTTMMADR
596 The reference code will use the information in this structure in order to reset
597 PCIe Gen3 devices during equalization, if necessary
598 **/
599 UINT32 GttMmAdr;
600
601 /** Offset 0x0268 - Selection of iGFX GTT Memory size
602 1=2MB, 2=4MB, 3=8MB, Default is 3
603 1:2MB, 2:4MB, 3:8MB
604 **/
605 UINT16 GttSize;
606
607 /** Offset 0x026A - Selection of the primary display device
608 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
609 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
610 **/
611 UINT8 PrimaryDisplay;
612
613 /** Offset 0x026B - Switchable Graphics GPIO information for PEG 0
614 Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
615 **/
616 UINT8 SaRtd3Pcie0Gpio[24];
617
618 /** Offset 0x0283 - Switchable Graphics GPIO information for PEG 1
619 Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
620 **/
621 UINT8 SaRtd3Pcie1Gpio[24];
622
623 /** Offset 0x029B - Switchable Graphics GPIO information for PEG 2
624 Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
625 **/
626 UINT8 SaRtd3Pcie2Gpio[24];
627
628 /** Offset 0x02B3 - PEG root port Device number for Switchable Graphics dGPU
629 Device number to indicate which PEG root port has dGPU
630 **/
631 UINT8 RootPortDev;
632
633 /** Offset 0x02B4 - PEG root port Function number for Switchable Graphics dGPU
634 Function number to indicate which PEG root port has dGPU
635 **/
636 UINT8 RootPortFun;
637
638 /** Offset 0x02B5 - Enable/Disable MRC TXT dependency
639 When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
640 MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
641 $EN_DIS
642 **/
643 UINT8 TxtImplemented;
644
645 /** Offset 0x02B6 - Enable/Disable SA OcSupport
646 Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
647 $EN_DIS
648 **/
649 UINT8 SaOcSupport;
650
651 /** Offset 0x02B7 - GT slice Voltage Mode
652 0(Default): Adaptive, 1: Override
653 0: Adaptive, 1: Override
654 **/
655 UINT8 GtsVoltageMode;
656
657 /** Offset 0x02B8 - GT unslice Voltage Mode
658 0(Default): Adaptive, 1: Override
659 0: Adaptive, 1: Override
660 **/
661 UINT8 GtusVoltageMode;
662
663 /** Offset 0x02B9 - Maximum GTs turbo ratio override
664 0(Default)=Minimal/Auto, 60=Maximum
665 **/
666 UINT8 GtsMaxOcRatio;
667
668 /** Offset 0x02BA - The voltage offset applied to GT slice
669 0(Default)=Minimal, 1000=Maximum
670 **/
671 UINT16 GtsVoltageOffset;
672
673 /** Offset 0x02BC - The GT slice voltage override which is applied to the entire range of GT frequencies
674 0(Default)=Minimal, 2000=Maximum
675 **/
676 UINT16 GtsVoltageOverride;
677
678 /** Offset 0x02BE - adaptive voltage applied during turbo frequencies
679 0(Default)=Minimal, 2000=Maximum
680 **/
681 UINT16 GtsExtraTurboVoltage;
682
683 /** Offset 0x02C0 - voltage offset applied to GT unslice
684 0(Default)=Minimal, 2000=Maximum
685 **/
686 UINT16 GtusVoltageOffset;
687
688 /** Offset 0x02C2 - GT unslice voltage override which is applied to the entire range of GT frequencies
689 0(Default)=Minimal, 2000=Maximum
690 **/
691 UINT16 GtusVoltageOverride;
692
693 /** Offset 0x02C4 - adaptive voltage applied during turbo frequencies
694 0(Default)=Minimal, 2000=Maximum
695 **/
696 UINT16 GtusExtraTurboVoltage;
697
698 /** Offset 0x02C6 - voltage offset applied to the SA
699 0(Default)=Minimal, 1000=Maximum
700 **/
701 UINT16 SaVoltageOffset;
702
703 /** Offset 0x02C8 - EDRAM ratio override
704 EdramRatio is deprecated on Kabylake
705 **/
706 UINT8 EdramRatio;
707
708 /** Offset 0x02C9 - Maximum GTus turbo ratio override
709 0(Default)=Minimal, 60=Maximum
710 **/
711 UINT8 GtusMaxOcRatio;
712
713 /** Offset 0x02CA - BIST on Reset
714 Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
715 $EN_DIS
716 **/
717 UINT8 BistOnReset;
718
719 /** Offset 0x02CB - Skip Stop PBET Timer Enable/Disable
720 Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
721 $EN_DIS
722 **/
723 UINT8 SkipStopPbet;
724
725 /** Offset 0x02CC - C6DRAM power gating feature
726 This feature is not supported. BIOS is required to disable. <b>0: Disable</b>
727 $EN_DIS
728 **/
729 UINT8 EnableC6Dram;
730
731 /** Offset 0x02CD - Over clocking support
732 Over clocking support; <b>0: Disable</b>; 1: Enable
733 $EN_DIS
734 **/
735 UINT8 OcSupport;
736
737 /** Offset 0x02CE - Over clocking Lock
738 Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
739 $EN_DIS
740 **/
741 UINT8 OcLock;
742
743 /** Offset 0x02CF - Maximum Core Turbo Ratio Override
744 Maximum core turbo ratio override allows to increase CPU core frequency beyond the
745 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
746 **/
747 UINT8 CoreMaxOcRatio;
748
749 /** Offset 0x02D0 - Core voltage mode
750 Core voltage mode; <b>0: Adaptive</b>; 1: Override.
751 $EN_DIS
752 **/
753 UINT8 CoreVoltageMode;
754
755 /** Offset 0x02D1 - Minimum clr turbo ratio override
756 Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-255
757 **/
758 UINT8 RingMinOcRatio;
759
760 /** Offset 0x02D2 - Maximum clr turbo ratio override
761 Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
762 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
763 **/
764 UINT8 RingMaxOcRatio;
765
766 /** Offset 0x02D3 - Hyper Threading Enable/Disable
767 Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
768 $EN_DIS
769 **/
770 UINT8 HyperThreading;
771
772 /** Offset 0x02D4 - Enable or Disable CPU Ratio Override
773 Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. @note If disabled,
774 BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting.
775 $EN_DIS
776 **/
777 UINT8 CpuRatioOverride;
778
779 /** Offset 0x02D5 - CPU ratio value
780 CPU ratio value. Valid Range 0 to 63
781 **/
782 UINT8 CpuRatio;
783
784 /** Offset 0x02D6 - Boot frequency
785 Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
786 <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
787 is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
788 0:0, 1:1, 2:2
789 **/
790 UINT8 BootFrequency;
791
792 /** Offset 0x02D7 - Number of active cores
793 Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
794 2 </b>;<b>3: 3 </b>
795 0:All, 1:1, 2:2, 3:3
796 **/
797 UINT8 ActiveCoreCount;
798
799 /** Offset 0x02D8 - Processor Early Power On Configuration FCLK setting
800 <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
801 2: 400 MHz. - 3: Reserved
802 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
803 **/
804 UINT8 FClkFrequency;
805
806 /** Offset 0x02D9 - Power JTAG in C10 and deeper power states
807 Power JTAG in C10 and deeper power states; <b>0: Disable</b>; 1: Enable.
808 $EN_DIS
809 **/
810 UINT8 JtagC10PowerGateDisable;
811
812 /** Offset 0x02DA - Enable or Disable VMX
813 Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
814 $EN_DIS
815 **/
816 UINT8 VmxEnable;
817
818 /** Offset 0x02DB - AVX2 Ratio Offset
819 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
820 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
821 **/
822 UINT8 Avx2RatioOffset;
823
824 /** Offset 0x02DC - core voltage override
825 The core voltage override which is applied to the entire range of cpu core frequencies.
826 Valid Range 0 to 2000
827 **/
828 UINT16 CoreVoltageOverride;
829
830 /** Offset 0x02DE - Core Turbo voltage Adaptive
831 Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
832 Valid Range 0 to 2000
833 **/
834 UINT16 CoreVoltageAdaptive;
835
836 /** Offset 0x02E0 - Core Turbo voltage Offset
837 The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
838 **/
839 UINT16 CoreVoltageOffset;
840
841 /** Offset 0x02E2 - Core PLL voltage offset
842 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
843 **/
844 UINT8 CorePllVoltageOffset;
845
846 /** Offset 0x02E3 - Ring Downbin
847 Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
848 lower than the core ratio. 0: Disable; <b>1: Enable.</b>
849 $EN_DIS
850 **/
851 UINT8 RingDownBin;
852
853 /** Offset 0x02E4 - BCLK Adaptive Voltage Enable
854 When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
855 Disable;<b> 1: Enable
856 $EN_DIS
857 **/
858 UINT8 BclkAdaptiveVoltage;
859
860 /** Offset 0x02E5 - BiosGuard
861 Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
862 $EN_DIS
863 **/
864 UINT8 BiosGuard;
865
866 /** Offset 0x02E6 - EnableSgx
867 Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable
868 $EN_DIS
869 **/
870 UINT8 EnableSgx;
871
872 /** Offset 0x02E7 - Txt
873 Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
874 $EN_DIS
875 **/
876 UINT8 Txt;
877
878 /** Offset 0x02E8 - PrmrrSize
879 Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
880 **/
881 UINT32 PrmrrSize;
882
883 /** Offset 0x02EC - SinitMemorySize
884 Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
885 **/
886 UINT32 SinitMemorySize;
887
888 /** Offset 0x02F0 - TxtDprMemoryBase
889 Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
890 **/
891 UINT64 TxtDprMemoryBase;
892
893 /** Offset 0x02F8 - TxtDprMemorySize
894 Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
895 **/
896 UINT32 TxtDprMemorySize;
897
898 /** Offset 0x02FC - TxtHeapMemorySize
899 Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
900 **/
901 UINT32 TxtHeapMemorySize;
902
903 /** Offset 0x0300 - FlashWearOutProtection
904 Enable/Disable. 0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable
905 $EN_DIS
906 **/
907 UINT8 FlashWearOutProtection;
908
909 /** Offset 0x0301 - Thermal Velocity Boost Ratio clipping
910 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
911 caused by high package temperatures for processors that implement the Intel Thermal
912 Velocity Boost (TVB) feature
913 0: Disabled, 1: Enabled
914 **/
915 UINT8 TvbRatioClipping;
916
917 /** Offset 0x0302 - Thermal Velocity Boost voltage optimization
918 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
919 for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
920 0: Disabled, 1: Enabled
921 **/
922 UINT8 TvbVoltageOptimization;
923
924 /** Offset 0x0303 - ReservedSecurityPreMem
925 Reserved for Security Pre-Mem
926 $EN_DIS
927 **/
928 UINT8 ReservedSecurityPreMem[7];
929
930 /** Offset 0x030A - PCH HPET Enabled
931 Enable/disable PCH HPET.
932 $EN_DIS
933 **/
934 UINT8 PchHpetEnable;
935
936 /** Offset 0x030B - PCH HPET BDF valid
937 Whether the BDF value is valid. 0: Disable; 1: Enable.
938 $EN_DIS
939 **/
940 UINT8 PchHpetBdfValid;
941
942 /** Offset 0x030C - The HPET Base Address
943 The HPET base address. Default is 0xFED00000.
944 **/
945 UINT32 PchHpetBase;
946
947 /** Offset 0x0310 - PCH HPET Bus Number
948 Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0.
949 **/
950 UINT8 PchHpetBusNumber;
951
952 /** Offset 0x0311 - PCH HPET Device Number
953 Device Number HPETn used as Requestor / Completer ID. Default is 0x1F.
954 **/
955 UINT8 PchHpetDeviceNumber;
956
957 /** Offset 0x0312 - PCH HPET Function Number
958 Function Number HPETn used as Requestor / Completer ID. Default is 0x00.
959 **/
960 UINT8 PchHpetFunctionNumber;
961
962 /** Offset 0x0313 - Enable PCH HSIO PCIE Rx Set Ctle
963 Enable PCH PCIe Gen 3 Set CTLE Value.
964 **/
965 UINT8 PchPcieHsioRxSetCtleEnable[24];
966
967 /** Offset 0x032B - PCH HSIO PCIE Rx Set Ctle Value
968 PCH PCIe Gen 3 Set CTLE Value.
969 **/
970 UINT8 PchPcieHsioRxSetCtle[24];
971
972 /** Offset 0x0343 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
973 0: Disable; 1: Enable.
974 **/
975 UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
976
977 /** Offset 0x035B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
978 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
979 **/
980 UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
981
982 /** Offset 0x0373 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
983 0: Disable; 1: Enable.
984 **/
985 UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
986
987 /** Offset 0x038B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
988 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
989 **/
990 UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
991
992 /** Offset 0x03A3 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
993 0: Disable; 1: Enable.
994 **/
995 UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
996
997 /** Offset 0x03BB - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
998 PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
999 **/
1000 UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
1001
1002 /** Offset 0x03D3 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
1003 0: Disable; 1: Enable.
1004 **/
1005 UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
1006
1007 /** Offset 0x03EB - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
1008 PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
1009 **/
1010 UINT8 PchPcieHsioTxGen1DeEmph[24];
1011
1012 /** Offset 0x0403 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
1013 0: Disable; 1: Enable.
1014 **/
1015 UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
1016
1017 /** Offset 0x041B - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
1018 PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
1019 **/
1020 UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
1021
1022 /** Offset 0x0433 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
1023 0: Disable; 1: Enable.
1024 **/
1025 UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
1026
1027 /** Offset 0x044B - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
1028 PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
1029 **/
1030 UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
1031
1032 /** Offset 0x0463 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1033 0: Disable; 1: Enable.
1034 **/
1035 UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
1036
1037 /** Offset 0x046B - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1038 PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1039 **/
1040 UINT8 PchSataHsioRxGen1EqBoostMag[8];
1041
1042 /** Offset 0x0473 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1043 0: Disable; 1: Enable.
1044 **/
1045 UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
1046
1047 /** Offset 0x047B - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1048 PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1049 **/
1050 UINT8 PchSataHsioRxGen2EqBoostMag[8];
1051
1052 /** Offset 0x0483 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1053 0: Disable; 1: Enable.
1054 **/
1055 UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
1056
1057 /** Offset 0x048B - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1058 PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1059 **/
1060 UINT8 PchSataHsioRxGen3EqBoostMag[8];
1061
1062 /** Offset 0x0493 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
1063 0: Disable; 1: Enable.
1064 **/
1065 UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
1066
1067 /** Offset 0x049B - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
1068 PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
1069 **/
1070 UINT8 PchSataHsioTxGen1DownscaleAmp[8];
1071
1072 /** Offset 0x04A3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
1073 0: Disable; 1: Enable.
1074 **/
1075 UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
1076
1077 /** Offset 0x04AB - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
1078 PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
1079 **/
1080 UINT8 PchSataHsioTxGen2DownscaleAmp[8];
1081
1082 /** Offset 0x04B3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
1083 0: Disable; 1: Enable.
1084 **/
1085 UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
1086
1087 /** Offset 0x04BB - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
1088 PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
1089 **/
1090 UINT8 PchSataHsioTxGen3DownscaleAmp[8];
1091
1092 /** Offset 0x04C3 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
1093 0: Disable; 1: Enable.
1094 **/
1095 UINT8 PchSataHsioTxGen1DeEmphEnable[8];
1096
1097 /** Offset 0x04CB - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
1098 PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
1099 **/
1100 UINT8 PchSataHsioTxGen1DeEmph[8];
1101
1102 /** Offset 0x04D3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
1103 0: Disable; 1: Enable.
1104 **/
1105 UINT8 PchSataHsioTxGen2DeEmphEnable[8];
1106
1107 /** Offset 0x04DB - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
1108 PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
1109 **/
1110 UINT8 PchSataHsioTxGen2DeEmph[8];
1111
1112 /** Offset 0x04E3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
1113 0: Disable; 1: Enable.
1114 **/
1115 UINT8 PchSataHsioTxGen3DeEmphEnable[8];
1116
1117 /** Offset 0x04EB - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
1118 PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
1119 **/
1120 UINT8 PchSataHsioTxGen3DeEmph[8];
1121
1122 /** Offset 0x04F3 - PCH LPC Enhance the port 8xh decoding
1123 Original LPC only decodes one byte of port 80h.
1124 $EN_DIS
1125 **/
1126 UINT8 PchLpcEnhancePort8xhDecoding;
1127
1128 /** Offset 0x04F4 - PCH Acpi Base
1129 Power management I/O base address. Default is 0x1800.
1130 **/
1131 UINT16 PchAcpiBase;
1132
1133 /** Offset 0x04F6 - PCH Port80 Route
1134 Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
1135 $EN_DIS
1136 **/
1137 UINT8 PchPort80Route;
1138
1139 /** Offset 0x04F7 - Enable SMBus ARP support
1140 Enable SMBus ARP support.
1141 $EN_DIS
1142 **/
1143 UINT8 SmbusArpEnable;
1144
1145 /** Offset 0x04F8 - SMBUS Base Address
1146 SMBUS Base Address (IO space).
1147 **/
1148 UINT16 PchSmbusIoBase;
1149
1150 /** Offset 0x04FA - Number of RsvdSmbusAddressTable.
1151 The number of elements in the RsvdSmbusAddressTable.
1152 **/
1153 UINT8 PchNumRsvdSmbusAddresses;
1154
1155 /** Offset 0x04FB
1156 **/
1157 UINT8 UnusedUpdSpace8;
1158
1159 /** Offset 0x04FC - Point of RsvdSmbusAddressTable
1160 Array of addresses reserved for non-ARP-capable SMBus devices.
1161 **/
1162 UINT32 RsvdSmbusAddressTablePtr;
1163
1164 /** Offset 0x0500 - Trace Hub Memory Region 0
1165 Trace Hub Memory Region 0.
1166 **/
1167 UINT32 TraceHubMemReg0Size;
1168
1169 /** Offset 0x0504 - Trace Hub Memory Region 1
1170 Trace Hub Memory Region 1.
1171 **/
1172 UINT32 TraceHubMemReg1Size;
1173
1174 /** Offset 0x0508 - Enable PCIE RP Mask
1175 Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
1176 for port1, bit1 for port2, and so on.
1177 **/
1178 UINT32 PcieRpEnableMask;
1179
1180 /** Offset 0x050C - Debug Interfaces
1181 Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
1182 BIT2 - Not used.
1183 **/
1184 UINT8 PcdDebugInterfaceFlags;
1185
1186 /** Offset 0x050D - SerialIo Uart Number Selection
1187 Select SerialIo Uart Controller for debug.
1188 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
1189 **/
1190 UINT8 PcdSerialIoUartNumber;
1191
1192 /** Offset 0x050E - ISA Serial Base selection
1193 Select ISA Serial Base address. Default is 0x3F8.
1194 0:0x3F8, 1:0x2F8
1195 **/
1196 UINT8 PcdIsaSerialUartBase;
1197
1198 /** Offset 0x050F - PCH Pm Pcie Pll Ssc
1199 Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
1200 BIOS override.
1201 **/
1202 UINT8 PchPmPciePllSsc;
1203
1204 /** Offset 0x0510 - Enable or Disable Peci C10 Reset command
1205 Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.
1206 $EN_DIS
1207 **/
1208 UINT8 PeciC10Reset;
1209
1210 /** Offset 0x0511 - Enable or Disable Peci Sx Reset command
1211 Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
1212 $EN_DIS
1213 **/
1214 UINT8 PeciSxReset;
1215
1216 /** Offset 0x0512 - PcdSerialDebugBaudRate
1217 Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
1218 3:9600, 4:19200, 6:56700, 7:115200
1219 **/
1220 UINT8 PcdSerialDebugBaudRate;
1221
1222 /** Offset 0x0513 - PcdSerialDebugLevel
1223 Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
1224 Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
1225 Info & Verbose
1226 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
1227 Error Warnings and Info, 5:Load Error Warnings Info and Verbose
1228 **/
1229 UINT8 PcdSerialDebugLevel;
1230
1231 /** Offset 0x0514 - Enable or Disable EV Loader
1232 Enable or Disable EV Loader; <b>0: Disable;</b> 1: Enable.
1233 $EN_DIS
1234 **/
1235 UINT8 EvLoader;
1236
1237 /** Offset 0x0515 - GT PLL voltage offset
1238 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1239 0x0:0xFF
1240 **/
1241 UINT8 GtPllVoltageOffset;
1242
1243 /** Offset 0x0516 - Ring PLL voltage offset
1244 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1245 0x0:0xFF
1246 **/
1247 UINT8 RingPllVoltageOffset;
1248
1249 /** Offset 0x0517 - System Agent PLL voltage offset
1250 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1251 0x0:0xFF
1252 **/
1253 UINT8 SaPllVoltageOffset;
1254
1255 /** Offset 0x0518 - Memory Controller PLL voltage offset
1256 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1257 0x0:0xFF
1258 **/
1259 UINT8 McPllVoltageOffset;
1260
1261 /** Offset 0x0519 - Realtime Memory Timing
1262 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
1263 realtime memory timing changes after MRC_DONE.
1264 0: Disabled, 1: Enabled
1265 **/
1266 UINT8 RealtimeMemoryTiming;
1267
1268 /** Offset 0x051A - AVX3 Ratio Offset
1269 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
1270 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
1271 **/
1272 UINT8 Avx3RatioOffset;
1273
1274 /** Offset 0x051B - Ask MRC to clear memory content
1275 Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
1276 $EN_DIS
1277 **/
1278 UINT8 CleanMemory;
1279
1280 /** Offset 0x051C - TjMax Offset
1281 TjMax offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support
1282 TjMax in the range of 62 to 115 deg Celsius. Valid Range 0 - 63
1283 **/
1284 UINT8 TjMaxOffset;
1285
1286 /** Offset 0x051D
1287 **/
1288 UINT8 ReservedFspmUpd[3];
1289 } FSP_M_CONFIG;
1290
1291 /** Fsp M Test Configuration
1292 **/
1293 typedef struct {
1294
1295 /** Offset 0x0520
1296 **/
1297 UINT32 Signature;
1298
1299 /** Offset 0x0524 - Skip external display device scanning
1300 Enable: Do not scan for external display device, Disable (Default): Scan external
1301 display devices
1302 $EN_DIS
1303 **/
1304 UINT8 SkipExtGfxScan;
1305
1306 /** Offset 0x0525 - Generate BIOS Data ACPI Table
1307 Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
1308 $EN_DIS
1309 **/
1310 UINT8 BdatEnable;
1311
1312 /** Offset 0x0526 - Detect External Graphics device for LegacyOpROM
1313 Detect and report if external graphics device only support LegacyOpROM or not (to
1314 support CSM auto-enable). Enable(Default)=1, Disable=0
1315 $EN_DIS
1316 **/
1317 UINT8 ScanExtGfxForLegacyOpRom;
1318
1319 /** Offset 0x0527 - Lock PCU Thermal Management registers
1320 Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
1321 $EN_DIS
1322 **/
1323 UINT8 LockPTMregs;
1324
1325 /** Offset 0x0528 - Enable/Disable DmiVc1
1326 Enable/Disable DmiVc1. Enable = 1, Disable (Default) = 0
1327 $EN_DIS
1328 **/
1329 UINT8 DmiVc1;
1330
1331 /** Offset 0x0529 - Enable/Disable DmiVcm
1332 Enable/Disable DmiVcm. Enable (Default) = 1, Disable = 0
1333 $EN_DIS
1334 **/
1335 UINT8 DmiVcm;
1336
1337 /** Offset 0x052A - DMI Max Link Speed
1338 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
1339 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
1340 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
1341 **/
1342 UINT8 DmiMaxLinkSpeed;
1343
1344 /** Offset 0x052B - DMI Equalization Phase 2
1345 DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
1346 AUTO - Use the current default method
1347 0:Disable phase2, 1:Enable phase2, 2:Auto
1348 **/
1349 UINT8 DmiGen3EqPh2Enable;
1350
1351 /** Offset 0x052C - DMI Gen3 Equalization Phase3
1352 DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
1353 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
1354 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
1355 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
1356 Phase1), Disabled(0x4): Bypass Equalization Phase 3
1357 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
1358 **/
1359 UINT8 DmiGen3EqPh3Method;
1360
1361 /** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:0.
1362 Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
1363 Enable phase 2, Auto(0x2)(Default): Use the current default method
1364 0:Disable, 1:Enable, 2:Auto
1365 **/
1366 UINT8 Peg0Gen3EqPh2Enable;
1367
1368 /** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:1.
1369 Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
1370 Enable phase 2, Auto(0x2)(Default): Use the current default method
1371 0:Disable, 1:Enable, 2:Auto
1372 **/
1373 UINT8 Peg1Gen3EqPh2Enable;
1374
1375 /** Offset 0x052F - Phase2 EQ enable on the PEG 0:1:2.
1376 Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
1377 Enable phase 2, Auto(0x2)(Default): Use the current default method
1378 0:Disable, 1:Enable, 2:Auto
1379 **/
1380 UINT8 Peg2Gen3EqPh2Enable;
1381
1382 /** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:0.
1383 PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
1384 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
1385 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
1386 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
1387 Phase1), Disabled(0x4): Bypass Equalization Phase 3
1388 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
1389 **/
1390 UINT8 Peg0Gen3EqPh3Method;
1391
1392 /** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:1.
1393 PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
1394 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
1395 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
1396 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
1397 Phase1), Disabled(0x4): Bypass Equalization Phase 3
1398 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
1399 **/
1400 UINT8 Peg1Gen3EqPh3Method;
1401
1402 /** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:2.
1403 PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
1404 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
1405 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
1406 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
1407 Phase1), Disabled(0x4): Bypass Equalization Phase 3
1408 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
1409 **/
1410 UINT8 Peg2Gen3EqPh3Method;
1411
1412 /** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
1413 Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
1414 Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
1415 $EN_DIS
1416 **/
1417 UINT8 PegGen3ProgramStaticEq;
1418
1419 /** Offset 0x0534 - PEG Gen3 SwEq Always Attempt
1420 Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
1421 Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
1422 and generate new EQ values every boot, not recommended
1423 0:Disable, 1:Enable
1424 **/
1425 UINT8 Gen3SwEqAlwaysAttempt;
1426
1427 /** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq
1428 Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
1429 Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
1430 current default method (Default)Auto will test Presets 7, 3, and 5. It is possible
1431 for this default to change over time;using Auto will ensure Reference Code always
1432 uses the latest default settings
1433 0:P7 P3 P5, 1:P0 to P9, 2:Auto
1434 **/
1435 UINT8 Gen3SwEqNumberOfPresets;
1436
1437 /** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
1438 Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
1439 Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
1440 Use the current default
1441 0:Disable, 1:Enable, 2:Auto
1442 **/
1443 UINT8 Gen3SwEqEnableVocTest;
1444
1445 /** Offset 0x0537 - PPCIe Rx Compliance Testing Mode
1446 Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
1447 PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
1448 it should only be set when doing PCIe compliance testing
1449 $EN_DIS
1450 **/
1451 UINT8 PegRxCemTestingMode;
1452
1453 /** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
1454 the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0
1455 **/
1456 UINT8 PegRxCemLoopbackLane;
1457
1458 /** Offset 0x0539 - Generate PCIe BDAT Margin Table
1459 Set this policy to enable the generation and addition of PCIe margin data to the
1460 BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
1461 data generation, Enable(0x1): Generate PCIe BDAT margin data
1462 $EN_DIS
1463 **/
1464 UINT8 PegGenerateBdatMarginTable;
1465
1466 /** Offset 0x053A
1467 **/
1468 UINT8 UnusedUpdSpace9[6];
1469
1470 /** Offset 0x0540 - PCIe Non-Protocol Awareness for Rx Compliance Testing
1471 Set this policy to enable the generation and addition of PCIe margin data to the
1472 BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
1473 Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
1474 compliance testing
1475 $EN_DIS
1476 **/
1477 UINT8 PegRxCemNonProtocolAwareness;
1478
1479 /** Offset 0x0541 - PCIe Override RxCTLE
1480 Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
1481 Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
1482 peak values unmodified
1483 $EN_DIS
1484 **/
1485 UINT8 PegGen3RxCtleOverride;
1486
1487 /** Offset 0x0542 - Rsvd
1488 Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
1489 Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
1490 peak values unmodified
1491 $EN_DIS
1492 **/
1493 UINT8 PegGen3Rsvd;
1494
1495 /** Offset 0x0543 - Panel Power Enable
1496 Control for enabling/disabling VDD force bit (Required only for early enabling of
1497 eDP panel). 0=Disable, 1(Default)=Enable
1498 $EN_DIS
1499 **/
1500 UINT8 PanelPowerEnable;
1501
1502 /** Offset 0x0544 - PEG Gen3 Root port preset values per lane
1503 Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
1504 **/
1505 UINT8 PegGen3RootPortPreset[16];
1506
1507 /** Offset 0x0554 - PEG Gen3 End port preset values per lane
1508 Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
1509 **/
1510 UINT8 PegGen3EndPointPreset[16];
1511
1512 /** Offset 0x0564 - PEG Gen3 End port Hint values per lane
1513 Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
1514 **/
1515 UINT8 PegGen3EndPointHint[16];
1516
1517 /** Offset 0x0574 - Jitter Dwell Time for PCIe Gen3 Software Equalization
1518 Range: 0-65535, default is 1000. @warning Do not change from the default
1519 **/
1520 UINT16 Gen3SwEqJitterDwellTime;
1521
1522 /** Offset 0x0576 - Jitter Error Target for PCIe Gen3 Software Equalization
1523 Range: 0-65535, default is 1. @warning Do not change from the default
1524 **/
1525 UINT16 Gen3SwEqJitterErrorTarget;
1526
1527 /** Offset 0x0578 - VOC Dwell Time for PCIe Gen3 Software Equalization
1528 Range: 0-65535, default is 10000. @warning Do not change from the default
1529 **/
1530 UINT16 Gen3SwEqVocDwellTime;
1531
1532 /** Offset 0x057A - VOC Error Target for PCIe Gen3 Software Equalization
1533 Range: 0-65535, default is 2. @warning Do not change from the default
1534 **/
1535 UINT16 Gen3SwEqVocErrorTarget;
1536
1537 /** Offset 0x057C - SaPreMemTestRsvd
1538 Reserved for SA Pre-Mem Test
1539 $EN_DIS
1540 **/
1541 UINT8 SaPreMemTestRsvd[4];
1542
1543 /** Offset 0x0580 - BiosAcmBase
1544 Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
1545 **/
1546 UINT64 BiosAcmBase;
1547
1548 /** Offset 0x0588 - BiosAcmSize
1549 Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
1550 **/
1551 UINT32 BiosAcmSize;
1552
1553 /** Offset 0x058C - TgaSize
1554 Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
1555 **/
1556 UINT32 TgaSize;
1557
1558 /** Offset 0x0590 - TxtLcpPdBase
1559 Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
1560 **/
1561 UINT64 TxtLcpPdBase;
1562
1563 /** Offset 0x0598 - TxtLcpPdSize
1564 Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
1565 **/
1566 UINT64 TxtLcpPdSize;
1567
1568 /** Offset 0x05A0 - TotalFlashSize
1569 Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
1570 **/
1571 UINT16 TotalFlashSize;
1572
1573 /** Offset 0x05A2 - BiosSize
1574 Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
1575 **/
1576 UINT16 BiosSize;
1577
1578 /** Offset 0x05A4 - PCH Dci Enable
1579 Enable/disable PCH Dci.
1580 $EN_DIS
1581 **/
1582 UINT8 PchDciEn;
1583
1584 /** Offset 0x05A5 - PCH Dci Auto Detect
1585 Deprecated
1586 $EN_DIS
1587 **/
1588 UINT8 PchDciAutoDetect;
1589
1590 /** Offset 0x05A6 - Smbus dynamic power gating
1591 Disable or Enable Smbus dynamic power gating.
1592 $EN_DIS
1593 **/
1594 UINT8 SmbusDynamicPowerGating;
1595
1596 /** Offset 0x05A7 - Disable and Lock Watch Dog Register
1597 Set 1 to clear WDT status, then disable and lock WDT registers.
1598 $EN_DIS
1599 **/
1600 UINT8 WdtDisableAndLock;
1601
1602 /** Offset 0x05A8 - SMBUS SPD Write Disable
1603 Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
1604 Disable bit. For security recommendations, SPD write disable bit must be set.
1605 $EN_DIS
1606 **/
1607 UINT8 SmbusSpdWriteDisable;
1608
1609 /** Offset 0x05A9 - ChipsetInit HECI message
1610 Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.
1611 If disabled, it prevents from sending ChipsetInit HECI message.
1612 $EN_DIS
1613 **/
1614 UINT8 ChipsetInitMessage;
1615
1616 /** Offset 0x05AA - Bypass ChipsetInit sync reset.
1617 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.
1618 $EN_DIS
1619 **/
1620 UINT8 BypassPhySyncReset;
1621
1622 /** Offset 0x05AB - Force ME DID Init Status
1623 Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4:
1624 Memory not preserved across reset, Set ME DID init stat value
1625 $EN_DIS
1626 **/
1627 UINT8 DidInitStat;
1628
1629 /** Offset 0x05AC - CPU Replaced Polling Disable
1630 Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
1631 $EN_DIS
1632 **/
1633 UINT8 DisableCpuReplacedPolling;
1634
1635 /** Offset 0x05AD - ME DID Message
1636 Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
1637 the DID message from being sent)
1638 $EN_DIS
1639 **/
1640 UINT8 SendDidMsg;
1641
1642 /** Offset 0x05AE - Retry mechanism for HECI APIs
1643 Test, 0: disable, 1: enable, Enable/Disable HECI retry.
1644 $EN_DIS
1645 **/
1646 UINT8 DisableHeciRetry;
1647
1648 /** Offset 0x05AF - Check HECI message before send
1649 Test, 0: disable, 1: enable, Enable/Disable message check.
1650 $EN_DIS
1651 **/
1652 UINT8 DisableMessageCheck;
1653
1654 /** Offset 0x05B0 - Skip MBP HOB
1655 Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
1656 $EN_DIS
1657 **/
1658 UINT8 SkipMbpHob;
1659
1660 /** Offset 0x05B1 - HECI2 Interface Communication
1661 Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
1662 $EN_DIS
1663 **/
1664 UINT8 HeciCommunication2;
1665
1666 /** Offset 0x05B2 - Enable KT device
1667 Test, 0: disable, 1: enable, Enable or Disable KT device.
1668 $EN_DIS
1669 **/
1670 UINT8 KtDeviceEnable;
1671
1672 /** Offset 0x05B3 - Enable IDEr
1673 Test, 0: disable, 1: enable, Enable or Disable IDEr.
1674 $EN_DIS
1675 **/
1676 UINT8 IderDeviceEnable;
1677
1678 /** Offset 0x05B4
1679 **/
1680 UINT8 ReservedFspmTestUpd[12];
1681 } FSP_M_TEST_CONFIG;
1682
1683 /** Fsp M UPD Configuration
1684 **/
1685 typedef struct {
1686
1687 /** Offset 0x0000
1688 **/
1689 FSP_UPD_HEADER FspUpdHeader;
1690
1691 /** Offset 0x0020
1692 **/
1693 FSPM_ARCH_UPD FspmArchUpd;
1694
1695 /** Offset 0x0040
1696 **/
1697 FSP_M_CONFIG FspmConfig;
1698
1699 /** Offset 0x0520
1700 **/
1701 FSP_M_TEST_CONFIG FspmTestConfig;
1702
1703 /** Offset 0x05C0
1704 **/
1705 UINT8 UnusedUpdSpace10[134];
1706
1707 /** Offset 0x0646
1708 **/
1709 UINT16 UpdTerminator;
1710 } FSPM_UPD;
1711
1712 #pragma pack()
1713
1714 #endif
FSP_M_CONFIG::PchHpetDeviceNumber
UINT8 PchHpetDeviceNumber
Offset 0x0311 - PCH HPET Device Number Device Number HPETn used as Requestor / Completer ID...
Definition: FspmUpd.h:955
FSP_M_CONFIG::MmioSize
UINT16 MmioSize
Offset 0x00A0 - MMIO Size Size of MMIO space reserved for devices.
Definition: FspmUpd.h:164
FSP_M_TEST_CONFIG::Gen3SwEqJitterDwellTime
UINT16 Gen3SwEqJitterDwellTime
Offset 0x0574 - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000.
Definition: FspmUpd.h:1520
FSP_M_TEST_CONFIG::Signature
UINT32 Signature
Offset 0x0520.
Definition: FspmUpd.h:1297
FSP_M_CONFIG::TvbRatioClipping
UINT8 TvbRatioClipping
Offset 0x0301 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled.
Definition: FspmUpd.h:915
FSP_M_CONFIG::RootPortDev
UINT8 RootPortDev
Offset 0x02B3 - PEG root port Device number for Switchable Graphics dGPU Device number to indicate wh...
Definition: FspmUpd.h:631
FSP_M_CONFIG::CleanMemory
UINT8 CleanMemory
Offset 0x051B - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memor...
Definition: FspmUpd.h:1278
FSP_M_CONFIG::GtusVoltageMode
UINT8 GtusVoltageMode
Offset 0x02B8 - GT unslice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
Definition: FspmUpd.h:661
FSP_M_CONFIG::IedSize
UINT32 IedSize
Offset 0x0098 - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB...
Definition: FspmUpd.h:153
FSP_M_CONFIG::DllBwEn1
UINT8 DllBwEn1
Offset 0x018E - DllBwEn[1] DllBwEn[1], for 1333 (0..7)
Definition: FspmUpd.h:371
FSP_M_TEST_CONFIG::TxtLcpPdBase
UINT64 TxtLcpPdBase
Offset 0x0590 - TxtLcpPdBase Enable/Disable.
Definition: FspmUpd.h:1561
FSP_M_CONFIG::PchAcpiBase
UINT16 PchAcpiBase
Offset 0x04F4 - PCH Acpi Base Power management I/O base address.
Definition: FspmUpd.h:1131
FSP_M_TEST_CONFIG::DmiMaxLinkSpeed
UINT8 DmiMaxLinkSpeed
Offset 0x052A - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:1342
FSP_M_CONFIG::JtagC10PowerGateDisable
UINT8 JtagC10PowerGateDisable
Offset 0x02D9 - Power JTAG in C10 and deeper power states Power JTAG in C10 and deeper power states; ...
Definition: FspmUpd.h:810
FSP_M_CONFIG::OcSupport
UINT8 OcSupport
Offset 0x02CD - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS...
Definition: FspmUpd.h:735
FSPM_UPD::UpdTerminator
UINT16 UpdTerminator
Offset 0x0646.
Definition: FspmUpd.h:1709
FSP_M_CONFIG::GtusExtraTurboVoltage
UINT16 GtusExtraTurboVoltage
Offset 0x02C4 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
Definition: FspmUpd.h:696
FSP_M_CONFIG::Peg1MaxLinkSpeed
UINT8 Peg1MaxLinkSpeed
Offset 0x022B - PEG 1 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:476
FSP_M_TEST_CONFIG::Peg0Gen3EqPh2Enable
UINT8 Peg0Gen3EqPh2Enable
Offset 0x052D - Phase2 EQ enable on the PEG 0:1:0.
Definition: FspmUpd.h:1366
FSP_M_CONFIG::MrcFastBoot
UINT8 MrcFastBoot
Offset 0x0095 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC $EN_DIS.
Definition: FspmUpd.h:143
FSP_M_CONFIG::EnableTraceHub
UINT8 EnableTraceHub
Offset 0x00A6 - Enable Trace Hub Enable/disable Trace Hub function.
Definition: FspmUpd.h:187
FSP_M_CONFIG::GtusVoltageOffset
UINT16 GtusVoltageOffset
Offset 0x02C0 - voltage offset applied to GT unslice 0(Default)=Minimal, 2000=Maximum.
Definition: FspmUpd.h:686
FSP_M_CONFIG::MemorySpdDataLen
UINT16 MemorySpdDataLen
Offset 0x0058 - SPD Data Length Length of SPD Data 0x100:256 Bytes, 0x200:512 Bytes.
Definition: FspmUpd.h:88
FSP_M_CONFIG::DmiGen3ProgramStaticEq
UINT8 DmiGen3ProgramStaticEq
Offset 0x0226 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Stati...
Definition: FspmUpd.h:441
FSP_M_CONFIG::tRAS
UINT16 tRAS
Offset 0x0180 - tRAS RAS Active Time, 0: AUTO, max: 64.
Definition: FspmUpd.h:314
FSP_M_TEST_CONFIG::TotalFlashSize
UINT16 TotalFlashSize
Offset 0x05A0 - TotalFlashSize Enable/Disable.
Definition: FspmUpd.h:1571
FSP_M_TEST_CONFIG::Gen3SwEqVocErrorTarget
UINT16 Gen3SwEqVocErrorTarget
Offset 0x057A - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2.
Definition: FspmUpd.h:1535
FSP_M_TEST_CONFIG::PegGenerateBdatMarginTable
UINT8 PegGenerateBdatMarginTable
Offset 0x0539 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition...
Definition: FspmUpd.h:1464
FSP_M_TEST_CONFIG::DidInitStat
UINT8 DidInitStat
Offset 0x05AB - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels...
Definition: FspmUpd.h:1627
FSP_M_CONFIG::MemorySpdPtr11
UINT32 MemorySpdPtr11
Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 Pointer to SPD data in Memory.
Definition: FspmUpd.h:82
FSP_M_CONFIG::Peg1MaxLinkWidth
UINT8 Peg1MaxLinkWidth
Offset 0x022E - PEG 1 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4 0:Auto, 1:x1, 2:x2, 3:x4.
Definition: FspmUpd.h:497
FSP_M_TEST_CONFIG::BiosAcmSize
UINT32 BiosAcmSize
Offset 0x0588 - BiosAcmSize Enable/Disable.
Definition: FspmUpd.h:1551
FSP_M_CONFIG::tREFI
UINT16 tREFI
Offset 0x0184 - tREFI Refresh Interval, 0: AUTO, max: 65535.
Definition: FspmUpd.h:329
FSP_M_CONFIG::PchPort80Route
UINT8 PchPort80Route
Offset 0x04F6 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI...
Definition: FspmUpd.h:1137
FSP_M_CONFIG::InternalGfx
UINT8 InternalGfx
Offset 0x00E4 - Internal Graphics Enable/disable internal graphics.
Definition: FspmUpd.h:203
FSP_M_TEST_CONFIG::BiosAcmBase
UINT64 BiosAcmBase
Offset 0x0580 - BiosAcmBase Enable/Disable.
Definition: FspmUpd.h:1546
FSP_M_CONFIG::SmramMask
UINT8 SmramMask
Offset 0x0094 - Smram Mask The SMM Regions AB-SEG and/or H-SEG reserved 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both.
Definition: FspmUpd.h:137
FSP_M_CONFIG::Avx3RatioOffset
UINT8 Avx3RatioOffset
Offset 0x051A - AVX3 Ratio Offset 0(Default)= No Offset.
Definition: FspmUpd.h:1272
FSP_M_CONFIG::PrimaryDisplay
UINT8 PrimaryDisplay
Offset 0x026A - Selection of the primary display device 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH...
Definition: FspmUpd.h:611
FSP_M_CONFIG::MmaTestConfigSize
UINT32 MmaTestConfigSize
Offset 0x0160 - MMA Test Config Size Size of MMA Test Config in Memory.
Definition: FspmUpd.h:261
FSP_M_CONFIG::CoreVoltageOverride
UINT16 CoreVoltageOverride
Offset 0x02DC - core voltage override The core voltage override which is applied to the entire range ...
Definition: FspmUpd.h:828
FSP_M_CONFIG::PcieRpEnableMask
UINT32 PcieRpEnableMask
Offset 0x0508 - Enable PCIE RP Mask Enable/disable PCIE Root Ports.
Definition: FspmUpd.h:1178
FSP_M_CONFIG::TraceHubMemReg1Size
UINT32 TraceHubMemReg1Size
Offset 0x0504 - Trace Hub Memory Region 1 Trace Hub Memory Region 1.
Definition: FspmUpd.h:1172
FSP_M_CONFIG::VddVoltage
UINT16 VddVoltage
Offset 0x0178 - Memory Voltage Memory Voltage Override (Vddq).
Definition: FspmUpd.h:280
FSP_M_CONFIG::GtsVoltageOverride
UINT16 GtsVoltageOverride
Offset 0x02BC - The GT slice voltage override which is applied to the entire range of GT frequencies ...
Definition: FspmUpd.h:676
FSP_M_CONFIG::RsvdSmbusAddressTablePtr
UINT32 RsvdSmbusAddressTablePtr
Offset 0x04FC - Point of RsvdSmbusAddressTable Array of addresses reserved for non-ARP-capable SMBus ...
Definition: FspmUpd.h:1162
FSP_M_CONFIG::HyperThreading
UINT8 HyperThreading
Offset 0x02D3 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enab...
Definition: FspmUpd.h:770
FSP_M_CONFIG::Heci2BarAddress
UINT32 Heci2BarAddress
Offset 0x01A4 - HECI2 BAR address BAR address of HECI2.
Definition: FspmUpd.h:401
FSP_M_CONFIG::MmaTestContentSize
UINT32 MmaTestContentSize
Offset 0x0158 - MMA Test Content Size Size of MMA Test Content in Memory.
Definition: FspmUpd.h:251
FSP_M_CONFIG::GtsMaxOcRatio
UINT8 GtsMaxOcRatio
Offset 0x02B9 - Maximum GTs turbo ratio override 0(Default)=Minimal/Auto, 60=Maximum.
Definition: FspmUpd.h:666
FSP_M_CONFIG::Peg2PowerDownUnusedLanes
UINT8 Peg2PowerDownUnusedLanes
Offset 0x0232 - Power down unused lanes on PEG 2 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
Definition: FspmUpd.h:525
FSP_M_TEST_CONFIG::Gen3SwEqJitterErrorTarget
UINT16 Gen3SwEqJitterErrorTarget
Offset 0x0576 - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1.
Definition: FspmUpd.h:1525
FSP_M_CONFIG::ActiveCoreCount
UINT8 ActiveCoreCount
Offset 0x02D7 - Number of active cores Number of active cores(Depends on Number of cores)...
Definition: FspmUpd.h:797
FSPM_UPD::FspmArchUpd
FSPM_ARCH_UPD FspmArchUpd
Offset 0x0020.
Definition: FspmUpd.h:1693
FSP_M_CONFIG::OddRatioMode
UINT8 OddRatioMode
Offset 0x017C - QCLK Odd Ratio Adds 133 or 100 MHz to QCLK frequency, depending on RefClk $EN_DIS...
Definition: FspmUpd.h:299
FSP_M_TEST_CONFIG::Peg0Gen3EqPh3Method
UINT8 Peg0Gen3EqPh3Method
Offset 0x0530 - Phase3 EQ method on the PEG 0:1:0.
Definition: FspmUpd.h:1390
FSP_M_CONFIG::MmaTestConfigPtr
UINT32 MmaTestConfigPtr
Offset 0x015C - MMA Test Config Pointer Pointer to MMA Test Config in Memory.
Definition: FspmUpd.h:256
FSP_M_TEST_CONFIG::SmbusSpdWriteDisable
UINT8 SmbusSpdWriteDisable
Offset 0x05A8 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable.
Definition: FspmUpd.h:1607
FSP_M_CONFIG::MemorySpdPtr00
UINT32 MemorySpdPtr00
Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 Pointer to SPD data in Memory.
Definition: FspmUpd.h:67
FSP_M_TEST_CONFIG::PegGen3RxCtleOverride
UINT8 PegGen3RxCtleOverride
Offset 0x0541 - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavi...
Definition: FspmUpd.h:1485
FSP_M_CONFIG::tRRD
UINT8 tRRD
Offset 0x0188 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 15.
Definition: FspmUpd.h:339
FSP_M_CONFIG::Peg0MaxLinkWidth
UINT8 Peg0MaxLinkWidth
Offset 0x022D - PEG 0 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8.
Definition: FspmUpd.h:490
FSP_M_CONFIG::TraceHubMemReg0Size
UINT32 TraceHubMemReg0Size
Offset 0x0500 - Trace Hub Memory Region 0 Trace Hub Memory Region 0.
Definition: FspmUpd.h:1167
FSP_M_CONFIG::PcdSerialIoUartNumber
UINT8 PcdSerialIoUartNumber
Offset 0x050D - SerialIo Uart Number Selection Select SerialIo Uart Controller for debug...
Definition: FspmUpd.h:1190
FSP_M_CONFIG::GtsExtraTurboVoltage
UINT16 GtsExtraTurboVoltage
Offset 0x02BE - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
Definition: FspmUpd.h:681
FSP_M_CONFIG::McPllVoltageOffset
UINT8 McPllVoltageOffset
Offset 0x0518 - Memory Controller PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1259
FSP_M_TEST_CONFIG::Gen3SwEqAlwaysAttempt
UINT8 Gen3SwEqAlwaysAttempt
Offset 0x0534 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot...
Definition: FspmUpd.h:1425
FSP_M_TEST_CONFIG::PegRxCemLoopbackLane
UINT8 PegRxCemLoopbackLane
Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied ...
Definition: FspmUpd.h:1456
FSP_M_CONFIG::IgdDvmt50PreAlloc
UINT8 IgdDvmt50PreAlloc
Offset 0x00E3 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graph...
Definition: FspmUpd.h:197
FSP_M_TEST_CONFIG::Peg1Gen3EqPh3Method
UINT8 Peg1Gen3EqPh3Method
Offset 0x0531 - Phase3 EQ method on the PEG 0:1:1.
Definition: FspmUpd.h:1400
FSP_M_TEST_CONFIG::SkipMbpHob
UINT8 SkipMbpHob
Offset 0x05B0 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. ...
Definition: FspmUpd.h:1658
FSP_M_CONFIG::GtusVoltageOverride
UINT16 GtusVoltageOverride
Offset 0x02C2 - GT unslice voltage override which is applied to the entire range of GT frequencies 0(...
Definition: FspmUpd.h:691
FSP_M_CONFIG::RootPortFun
UINT8 RootPortFun
Offset 0x02B4 - PEG root port Function number for Switchable Graphics dGPU Function number to indicat...
Definition: FspmUpd.h:636
FSP_M_CONFIG::tRCDtRP
UINT8 tRCDtRP
Offset 0x0183 - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63.
Definition: FspmUpd.h:324
FSP_M_TEST_CONFIG::IderDeviceEnable
UINT8 IderDeviceEnable
Offset 0x05B3 - Enable IDEr Test, 0: disable, 1: enable, Enable or Disable IDEr.
Definition: FspmUpd.h:1676
FSP_M_TEST_CONFIG::PegRxCemNonProtocolAwareness
UINT8 PegRxCemNonProtocolAwareness
Offset 0x0540 - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the g...
Definition: FspmUpd.h:1477
FSP_M_CONFIG::BootFrequency
UINT8 BootFrequency
Offset 0x02D6 - Boot frequency Sets the boot frequency starting from reset vector.
Definition: FspmUpd.h:790
FSP_M_CONFIG::ProbelessTrace
UINT8 ProbelessTrace
Offset 0x00A2 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable.
Definition: FspmUpd.h:171
FSP_M_CONFIG::PrmrrSize
UINT32 PrmrrSize
Offset 0x02E8 - PrmrrSize Enable/Disable.
Definition: FspmUpd.h:881
FSP_M_CONFIG::CoreMaxOcRatio
UINT8 CoreMaxOcRatio
Offset 0x02CF - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increas...
Definition: FspmUpd.h:747
FSP_M_CONFIG::GtPllVoltageOffset
UINT8 GtPllVoltageOffset
Offset 0x0515 - GT PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1241
FSP_M_TEST_CONFIG::PchDciEn
UINT8 PchDciEn
Offset 0x05A4 - PCH Dci Enable Enable/disable PCH Dci.
Definition: FspmUpd.h:1582
FSP_M_CONFIG::PcdSerialDebugLevel
UINT8 PcdSerialDebugLevel
Offset 0x0513 - PcdSerialDebugLevel Serial Debug Message Level.
Definition: FspmUpd.h:1229
FSP_M_TEST_CONFIG
Fsp M Test Configuration.
Definition: FspmUpd.h:1293
FSP_M_CONFIG::GttMmAdr
UINT32 GttMmAdr
Offset 0x0264 - Temporary MMIO address for GTTMMADR The reference code will use the information in th...
Definition: FspmUpd.h:599
FSP_M_CONFIG::CoreVoltageOffset
UINT16 CoreVoltageOffset
Offset 0x02E0 - Core Turbo voltage Offset The voltage offset applied to the core while operating in t...
Definition: FspmUpd.h:839
FSP_M_CONFIG::Heci3BarAddress
UINT32 Heci3BarAddress
Offset 0x01A8 - HECI3 BAR address BAR address of HECI3.
Definition: FspmUpd.h:406
FspUpd.h
FSP_M_CONFIG::SaOcSupport
UINT8 SaOcSupport
Offset 0x02B6 - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA...
Definition: FspmUpd.h:649
FSP_M_CONFIG::Peg0PowerDownUnusedLanes
UINT8 Peg0PowerDownUnusedLanes
Offset 0x0230 - Power down unused lanes on PEG 0 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
Definition: FspmUpd.h:511
FSP_M_CONFIG::TvbVoltageOptimization
UINT8 TvbVoltageOptimization
Offset 0x0302 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default).
Definition: FspmUpd.h:922
FSP_M_CONFIG::RingPllVoltageOffset
UINT8 RingPllVoltageOffset
Offset 0x0516 - Ring PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1247
FSP_M_CONFIG::MemorySpdPtr10
UINT32 MemorySpdPtr10
Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 Pointer to SPD data in Memory.
Definition: FspmUpd.h:77
FSP_M_CONFIG::Peg0MaxLinkSpeed
UINT8 Peg0MaxLinkSpeed
Offset 0x022A - PEG 0 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:469
FSP_M_CONFIG::RMT
UINT8 RMT
Offset 0x00E7 - Rank Margin Tool Enable/disable Rank Margin Tool.
Definition: FspmUpd.h:223
FSP_M_CONFIG::ApertureSize
UINT8 ApertureSize
Offset 0x00E5 - Aperture Size Select the Aperture Size.
Definition: FspmUpd.h:209
FSPM_UPD::FspmConfig
FSP_M_CONFIG FspmConfig
Offset 0x0040.
Definition: FspmUpd.h:1697
FSP_M_TEST_CONFIG::TgaSize
UINT32 TgaSize
Offset 0x058C - TgaSize Enable/Disable.
Definition: FspmUpd.h:1556
FSP_M_CONFIG::EdramRatio
UINT8 EdramRatio
Offset 0x02C8 - EDRAM ratio override EdramRatio is deprecated on Kabylake.
Definition: FspmUpd.h:706
FSP_M_TEST_CONFIG::DisableMessageCheck
UINT8 DisableMessageCheck
Offset 0x05AF - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message ch...
Definition: FspmUpd.h:1652
FSP_M_CONFIG::TxtDprMemoryBase
UINT64 TxtDprMemoryBase
Offset 0x02F0 - TxtDprMemoryBase Enable/Disable.
Definition: FspmUpd.h:891
FSP_M_CONFIG::PeciSxReset
UINT8 PeciSxReset
Offset 0x0511 - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: D...
Definition: FspmUpd.h:1214
FSP_M_CONFIG::Peg2MaxLinkWidth
UINT8 Peg2MaxLinkWidth
Offset 0x022F - PEG 2 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
Definition: FspmUpd.h:504
FSP_M_TEST_CONFIG::SkipExtGfxScan
UINT8 SkipExtGfxScan
Offset 0x0524 - Skip external display device scanning Enable: Do not scan for external display device...
Definition: FspmUpd.h:1304
FSP_M_CONFIG::SgDelayAfterHoldReset
UINT16 SgDelayAfterHoldReset
Offset 0x0222 - SG dGPU Reset Delay SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds.
Definition: FspmUpd.h:428
FSP_M_CONFIG::GtsVoltageOffset
UINT16 GtsVoltageOffset
Offset 0x02BA - The voltage offset applied to GT slice 0(Default)=Minimal, 1000=Maximum.
Definition: FspmUpd.h:671
FSP_M_CONFIG::BistOnReset
UINT8 BistOnReset
Offset 0x02CA - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
Definition: FspmUpd.h:717
FSP_M_CONFIG::PlatformMemorySize
UINT64 PlatformMemorySize
Offset 0x0040 - Platform Reserved Memory Size The minimum platform memory size required to pass contr...
Definition: FspmUpd.h:62
FSP_M_CONFIG::tCWL
UINT8 tCWL
Offset 0x0182 - tCWL Min CAS Write Latency Delay Time, 0: AUTO, max: 20.
Definition: FspmUpd.h:319
FSP_M_TEST_CONFIG::KtDeviceEnable
UINT8 KtDeviceEnable
Offset 0x05B2 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device...
Definition: FspmUpd.h:1670
FSP_M_TEST_CONFIG::ChipsetInitMessage
UINT8 ChipsetInitMessage
Offset 0x05A9 - ChipsetInit HECI message Enable/Disable.
Definition: FspmUpd.h:1614
FSP_M_CONFIG::DllBwEn2
UINT8 DllBwEn2
Offset 0x018F - DllBwEn[2] DllBwEn[2], for 1600 (0..7)
Definition: FspmUpd.h:376
FSP_M_CONFIG::Peg2MaxLinkSpeed
UINT8 Peg2MaxLinkSpeed
Offset 0x022C - PEG 2 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:483
FSP_M_TEST_CONFIG::DmiVcm
UINT8 DmiVcm
Offset 0x0529 - Enable/Disable DmiVcm Enable/Disable DmiVcm.
Definition: FspmUpd.h:1335
FSP_M_TEST_CONFIG::PanelPowerEnable
UINT8 PanelPowerEnable
Offset 0x0543 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for ea...
Definition: FspmUpd.h:1500
FSP_M_CONFIG::PcdDebugInterfaceFlags
UINT8 PcdDebugInterfaceFlags
Offset 0x050C - Debug Interfaces Debug Interfaces.
Definition: FspmUpd.h:1184
FSP_M_CONFIG::tWR
UINT8 tWR
Offset 0x018A - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24.
Definition: FspmUpd.h:351
FSP_M_CONFIG::SinitMemorySize
UINT32 SinitMemorySize
Offset 0x02EC - SinitMemorySize Enable/Disable.
Definition: FspmUpd.h:886
FSP_M_TEST_CONFIG::TxtLcpPdSize
UINT64 TxtLcpPdSize
Offset 0x0598 - TxtLcpPdSize Enable/Disable.
Definition: FspmUpd.h:1566
FSP_M_CONFIG::RingMaxOcRatio
UINT8 RingMaxOcRatio
Offset 0x02D2 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase ...
Definition: FspmUpd.h:764
FSP_M_CONFIG::Peg2Enable
UINT8 Peg2Enable
Offset 0x0229 - Enable/Disable PEG 2 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (...
Definition: FspmUpd.h:462
FSP_M_CONFIG::EnableC6Dram
UINT8 EnableC6Dram
Offset 0x02CC - C6DRAM power gating feature This feature is not supported.
Definition: FspmUpd.h:729
FSP_M_CONFIG::CoreVoltageAdaptive
UINT16 CoreVoltageAdaptive
Offset 0x02DE - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu ...
Definition: FspmUpd.h:834
FSP_M_CONFIG::tCL
UINT8 tCL
Offset 0x017D - tCL CAS Latency, 0: AUTO, max: 31.
Definition: FspmUpd.h:304
FSP_M_CONFIG::tWTR
UINT8 tWTR
Offset 0x018B - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28...
Definition: FspmUpd.h:356
FSP_M_TEST_CONFIG::LockPTMregs
UINT8 LockPTMregs
Offset 0x0527 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers...
Definition: FspmUpd.h:1323
FSPM_UPD::FspmTestConfig
FSP_M_TEST_CONFIG FspmTestConfig
Offset 0x0520.
Definition: FspmUpd.h:1701
FSP_M_TEST_CONFIG::WdtDisableAndLock
UINT8 WdtDisableAndLock
Offset 0x05A7 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock ...
Definition: FspmUpd.h:1600
FSP_M_CONFIG::PegDisableSpreadSpectrumClocking
UINT8 PegDisableSpreadSpectrumClocking
Offset 0x0234 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking...
Definition: FspmUpd.h:540
FSP_M_CONFIG::BclkAdaptiveVoltage
UINT8 BclkAdaptiveVoltage
Offset 0x02E4 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequ...
Definition: FspmUpd.h:858
FSP_M_TEST_CONFIG::DmiGen3EqPh2Enable
UINT8 DmiGen3EqPh2Enable
Offset 0x052B - DMI Equalization Phase 2 DMI Equalization Phase 2.
Definition: FspmUpd.h:1349
FSP_M_CONFIG::TxtHeapMemorySize
UINT32 TxtHeapMemorySize
Offset 0x02FC - TxtHeapMemorySize Enable/Disable.
Definition: FspmUpd.h:901
FSP_M_CONFIG::tRTP
UINT8 tRTP
Offset 0x0189 - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15...
Definition: FspmUpd.h:345
FSP_M_CONFIG::DllBwEn3
UINT8 DllBwEn3
Offset 0x0190 - DllBwEn[3] DllBwEn[3], for 1867 and up (0..7)
Definition: FspmUpd.h:381
FSP_M_CONFIG::TsegSize
UINT32 TsegSize
Offset 0x009C - Tseg Size Size of SMRAM memory reserved.
Definition: FspmUpd.h:159
FSP_M_CONFIG::EnableSgx
UINT8 EnableSgx
Offset 0x02E6 - EnableSgx Enable/Disable.
Definition: FspmUpd.h:870
FSP_M_CONFIG::TjMaxOffset
UINT8 TjMaxOffset
Offset 0x051C - TjMax Offset TjMax offset.
Definition: FspmUpd.h:1284
FSP_M_CONFIG::PchPmPciePllSsc
UINT8 PchPmPciePllSsc
Offset 0x050F - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage.
Definition: FspmUpd.h:1202
FSP_M_CONFIG::CaVrefConfig
UINT8 CaVrefConfig
Offset 0x0093 - VREF_CA CA Vref routing: board-dependent 0:VREF_CA goes to both CH_A and CH_B...
Definition: FspmUpd.h:131
FSP_M_CONFIG::HeciTimeouts
UINT8 HeciTimeouts
Offset 0x01AC - HECI Timeouts Enable/Disable.
Definition: FspmUpd.h:412
FSP_M_CONFIG::PchSmbusIoBase
UINT16 PchSmbusIoBase
Offset 0x04F8 - SMBUS Base Address SMBUS Base Address (IO space).
Definition: FspmUpd.h:1148
MemInfoHob.h
This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Mem...
FSP_M_TEST_CONFIG::SmbusDynamicPowerGating
UINT8 SmbusDynamicPowerGating
Offset 0x05A6 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating.
Definition: FspmUpd.h:1594
FSP_M_CONFIG::PcdIsaSerialUartBase
UINT8 PcdIsaSerialUartBase
Offset 0x050E - ISA Serial Base selection Select ISA Serial Base address.
Definition: FspmUpd.h:1196
FSP_M_CONFIG::PchNumRsvdSmbusAddresses
UINT8 PchNumRsvdSmbusAddresses
Offset 0x04FA - Number of RsvdSmbusAddressTable.
Definition: FspmUpd.h:1153
FSP_M_CONFIG::tFAW
UINT16 tFAW
Offset 0x017E - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63.
Definition: FspmUpd.h:309
FSP_M_CONFIG::Heci1BarAddress
UINT32 Heci1BarAddress
Offset 0x01A0 - HECI1 BAR address BAR address of HECI1.
Definition: FspmUpd.h:396
FSP_M_TEST_CONFIG::PchDciAutoDetect
UINT8 PchDciAutoDetect
Offset 0x05A5 - PCH Dci Auto Detect Deprecated $EN_DIS.
Definition: FspmUpd.h:1588
FSP_M_TEST_CONFIG::Gen3SwEqNumberOfPresets
UINT8 Gen3SwEqNumberOfPresets
Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq pres...
Definition: FspmUpd.h:1435
FSP_M_CONFIG::RealtimeMemoryTiming
UINT8 RealtimeMemoryTiming
Offset 0x0519 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled.
Definition: FspmUpd.h:1266
FSP_M_CONFIG::SmbusArpEnable
UINT8 SmbusArpEnable
Offset 0x04F7 - Enable SMBus ARP support Enable SMBus ARP support.
Definition: FspmUpd.h:1143
FSP_M_TEST_CONFIG::DisableHeciRetry
UINT8 DisableHeciRetry
Offset 0x05AE - Retry mechanism for HECI APIs Test, 0: disable, 1: enable, Enable/Disable HECI retry...
Definition: FspmUpd.h:1646
FSP_M_CONFIG::MmioSizeAdjustment
UINT16 MmioSizeAdjustment
Offset 0x0224 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size...
Definition: FspmUpd.h:434
FSP_M_CONFIG::Peg1Enable
UINT8 Peg1Enable
Offset 0x0228 - Enable/Disable PEG 1 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (...
Definition: FspmUpd.h:455
FSP_M_CONFIG::DqPinsInterleaved
UINT8 DqPinsInterleaved
Offset 0x0092 - Dqs Pins Interleaved Setting Indicates DqPinsInterleaved setting: board-dependent $EN...
Definition: FspmUpd.h:124
FSP_M_TEST_CONFIG::DisableCpuReplacedPolling
UINT8 DisableCpuReplacedPolling
Offset 0x05AC - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disable...
Definition: FspmUpd.h:1633
FSP_M_CONFIG::tRFC
UINT16 tRFC
Offset 0x0186 - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 1023.
Definition: FspmUpd.h:334
SI_CHIPSET_INIT_INFO
The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CR...
Definition: FspmUpd.h:47
FSP_M_TEST_CONFIG::ScanExtGfxForLegacyOpRom
UINT8 ScanExtGfxForLegacyOpRom
Offset 0x0526 - Detect External Graphics device for LegacyOpROM Detect and report if external graphic...
Definition: FspmUpd.h:1317
FSP_M_TEST_CONFIG::Peg2Gen3EqPh3Method
UINT8 Peg2Gen3EqPh3Method
Offset 0x0532 - Phase3 EQ method on the PEG 0:1:2.
Definition: FspmUpd.h:1410
FSP_M_CONFIG::CoreVoltageMode
UINT8 CoreVoltageMode
Offset 0x02D0 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override.
Definition: FspmUpd.h:753
FSP_M_CONFIG::SmbusEnable
UINT8 SmbusEnable
Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller.
Definition: FspmUpd.h:181
FSP_M_CONFIG::SaPllVoltageOffset
UINT8 SaPllVoltageOffset
Offset 0x0517 - System Agent PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1253
FSP_M_CONFIG::PchHpetEnable
UINT8 PchHpetEnable
Offset 0x030A - PCH HPET Enabled Enable/disable PCH HPET.
Definition: FspmUpd.h:934
FSP_M_CONFIG::Txt
UINT8 Txt
Offset 0x02E7 - Txt Enable/Disable.
Definition: FspmUpd.h:876
FSP_M_TEST_CONFIG::PegGen3Rsvd
UINT8 PegGen3Rsvd
Offset 0x0542 - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled...
Definition: FspmUpd.h:1493
FSP_M_CONFIG::UserBd
UINT8 UserBd
Offset 0x00EA - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo...
Definition: FspmUpd.h:237
FSP_M_CONFIG::FlashWearOutProtection
UINT8 FlashWearOutProtection
Offset 0x0300 - FlashWearOutProtection Enable/Disable.
Definition: FspmUpd.h:907
FSP_M_TEST_CONFIG::SendDidMsg
UINT8 SendDidMsg
Offset 0x05AD - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable wi...
Definition: FspmUpd.h:1640
FSP_M_CONFIG::TxtImplemented
UINT8 TxtImplemented
Offset 0x02B5 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initia...
Definition: FspmUpd.h:643
FSP_M_CONFIG::SgDelayAfterPwrEn
UINT16 SgDelayAfterPwrEn
Offset 0x0220 - SG dGPU Power Delay SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds.
Definition: FspmUpd.h:422
FSP_M_CONFIG::BiosGuard
UINT8 BiosGuard
Offset 0x02E5 - BiosGuard Enable/Disable.
Definition: FspmUpd.h:864
FSP_M_CONFIG::Peg1PowerDownUnusedLanes
UINT8 Peg1PowerDownUnusedLanes
Offset 0x0231 - Power down unused lanes on PEG 1 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
Definition: FspmUpd.h:518
FSPM_UPD
Fsp M UPD Configuration.
Definition: FspmUpd.h:1685
FSP_M_TEST_CONFIG::Peg2Gen3EqPh2Enable
UINT8 Peg2Gen3EqPh2Enable
Offset 0x052F - Phase2 EQ enable on the PEG 0:1:2.
Definition: FspmUpd.h:1380
FSP_M_CONFIG::InitPcieAspmAfterOprom
UINT8 InitPcieAspmAfterOprom
Offset 0x0233 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM prog...
Definition: FspmUpd.h:533
FSP_M_CONFIG::Avx2RatioOffset
UINT8 Avx2RatioOffset
Offset 0x02DB - AVX2 Ratio Offset 0(Default)= No Offset.
Definition: FspmUpd.h:822
FSP_M_TEST_CONFIG::DmiVc1
UINT8 DmiVc1
Offset 0x0528 - Enable/Disable DmiVc1 Enable/Disable DmiVc1.
Definition: FspmUpd.h:1329
FSP_M_CONFIG::SkipStopPbet
UINT8 SkipStopPbet
Offset 0x02CB - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_D...
Definition: FspmUpd.h:723
FSP_M_CONFIG::DdrFreqLimit
UINT16 DdrFreqLimit
Offset 0x00E8 - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz.
Definition: FspmUpd.h:230
FSP_M_TEST_CONFIG::Peg1Gen3EqPh2Enable
UINT8 Peg1Gen3EqPh2Enable
Offset 0x052E - Phase2 EQ enable on the PEG 0:1:1.
Definition: FspmUpd.h:1373
FSP_M_CONFIG::PchHpetBase
UINT32 PchHpetBase
Offset 0x030C - The HPET Base Address The HPET base address.
Definition: FspmUpd.h:945
FSP_M_CONFIG::SpdProfileSelected
UINT8 SpdProfileSelected
Offset 0x0177 - SPD Profile Selected Select DIMM timing profile.
Definition: FspmUpd.h:272
FSP_M_TEST_CONFIG::BypassPhySyncReset
UINT8 BypassPhySyncReset
Offset 0x05AA - Bypass ChipsetInit sync reset.
Definition: FspmUpd.h:1620
FSP_M_CONFIG::SaVoltageOffset
UINT16 SaVoltageOffset
Offset 0x02C6 - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum.
Definition: FspmUpd.h:701
FSP_M_CONFIG::PchHpetBusNumber
UINT8 PchHpetBusNumber
Offset 0x0310 - PCH HPET Bus Number Bus Number HPETn used as Requestor / Completer ID...
Definition: FspmUpd.h:950
FSP_M_CONFIG::NModeSupport
UINT8 NModeSupport
Offset 0x018C - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N.
Definition: FspmUpd.h:361
FSP_M_TEST_CONFIG::Gen3SwEqEnableVocTest
UINT8 Gen3SwEqEnableVocTest
Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of th...
Definition: FspmUpd.h:1443
FSP_M_TEST_CONFIG::Gen3SwEqVocDwellTime
UINT16 Gen3SwEqVocDwellTime
Offset 0x0578 - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000.
Definition: FspmUpd.h:1530
FSP_M_CONFIG::PeciC10Reset
UINT8 PeciC10Reset
Offset 0x0510 - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command; 0:...
Definition: FspmUpd.h:1208
FSP_M_CONFIG::DmiDeEmphasis
UINT8 DmiDeEmphasis
Offset 0x0243 - DeEmphasis control for DMI DeEmphasis control for DMI.
Definition: FspmUpd.h:566
FSP_M_CONFIG::CpuRatio
UINT8 CpuRatio
Offset 0x02D5 - CPU ratio value CPU ratio value.
Definition: FspmUpd.h:782
FSP_M_CONFIG::TxtDprMemorySize
UINT32 TxtDprMemorySize
Offset 0x02F8 - TxtDprMemorySize Enable/Disable.
Definition: FspmUpd.h:896
FSP_M_CONFIG::OcLock
UINT8 OcLock
Offset 0x02CE - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable...
Definition: FspmUpd.h:741
FSP_M_CONFIG::MemorySpdPtr01
UINT32 MemorySpdPtr01
Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 Pointer to SPD data in Memory.
Definition: FspmUpd.h:72
FSP_M_CONFIG::Ratio
UINT8 Ratio
Offset 0x017B - Memory Ratio Automatic or the frequency will equal ratio times reference clock...
Definition: FspmUpd.h:293
FSP_M_CONFIG::GtusMaxOcRatio
UINT8 GtusMaxOcRatio
Offset 0x02C9 - Maximum GTus turbo ratio override 0(Default)=Minimal, 60=Maximum. ...
Definition: FspmUpd.h:711
FSP_M_CONFIG::DllBwEn0
UINT8 DllBwEn0
Offset 0x018D - DllBwEn[0] DllBwEn[0], for 1067 (0..7)
Definition: FspmUpd.h:366
FSP_M_CONFIG::GtsVoltageMode
UINT8 GtsVoltageMode
Offset 0x02B7 - GT slice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
Definition: FspmUpd.h:655
FSP_M_CONFIG::PchHpetBdfValid
UINT8 PchHpetBdfValid
Offset 0x030B - PCH HPET BDF valid Whether the BDF value is valid.
Definition: FspmUpd.h:940
FSP_M_TEST_CONFIG::PegRxCemTestingMode
UINT8 PegRxCemTestingMode
Offset 0x0537 - PPCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable P...
Definition: FspmUpd.h:1451
FSP_M_CONFIG::GttSize
UINT16 GttSize
Offset 0x0268 - Selection of iGFX GTT Memory size 1=2MB, 2=4MB, 3=8MB, Default is 3 1:2MB...
Definition: FspmUpd.h:605
FSP_M_CONFIG::Peg0Enable
UINT8 Peg0Enable
Offset 0x0227 - Enable/Disable PEG 0 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (...
Definition: FspmUpd.h:448
FSP_M_CONFIG::UnusedUpdSpace8
UINT8 UnusedUpdSpace8
Offset 0x04FB.
Definition: FspmUpd.h:1157
FSP_M_CONFIG::RingMinOcRatio
UINT8 RingMinOcRatio
Offset 0x02D1 - Minimum clr turbo ratio override Minimum clr turbo ratio override.
Definition: FspmUpd.h:758
FSP_M_TEST_CONFIG::BiosSize
UINT16 BiosSize
Offset 0x05A2 - BiosSize Enable/Disable.
Definition: FspmUpd.h:1576
FSP_M_CONFIG
Fsp M Configuration.
Definition: FspmUpd.h:57
FSP_M_CONFIG::CpuRatioOverride
UINT8 CpuRatioOverride
Offset 0x02D4 - Enable or Disable CPU Ratio Override Enable or Disable CPU Ratio Override; 0: Disable...
Definition: FspmUpd.h:777
FSPM_UPD::FspUpdHeader
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FspmUpd.h:1689
FSP_M_CONFIG::RefClk
UINT8 RefClk
Offset 0x017A - Memory Reference Clock Automatic, 100MHz, 133MHz.
Definition: FspmUpd.h:286
FSP_M_CONFIG::VmxEnable
UINT8 VmxEnable
Offset 0x02DA - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable.
Definition: FspmUpd.h:816
FSP_M_TEST_CONFIG::HeciCommunication2
UINT8 HeciCommunication2
Offset 0x05B1 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Devi...
Definition: FspmUpd.h:1664
FSP_M_CONFIG::PcdSerialDebugBaudRate
UINT8 PcdSerialDebugBaudRate
Offset 0x0512 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages.
Definition: FspmUpd.h:1220
FSP_M_CONFIG::CorePllVoltageOffset
UINT8 CorePllVoltageOffset
Offset 0x02E2 - Core PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:844
FSP_M_CONFIG::FClkFrequency
UINT8 FClkFrequency
Offset 0x02D8 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX).
Definition: FspmUpd.h:804
FSP_M_CONFIG::PchLpcEnhancePort8xhDecoding
UINT8 PchLpcEnhancePort8xhDecoding
Offset 0x04F3 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h...
Definition: FspmUpd.h:1126
FSP_M_TEST_CONFIG::PegGen3ProgramStaticEq
UINT8 PegGen3ProgramStaticEq
Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Stati...
Definition: FspmUpd.h:1417
FSP_M_CONFIG::EvLoader
UINT8 EvLoader
Offset 0x0514 - Enable or Disable EV Loader Enable or Disable EV Loader; 0: Disable; 1: Enable...
Definition: FspmUpd.h:1235
FSP_M_CONFIG::SaGv
UINT8 SaGv
Offset 0x00E6 - SA GV System Agent dynamic frequency support and when enabled memory will be training...
Definition: FspmUpd.h:217
FSP_M_CONFIG::PegDataPtr
UINT32 PegDataPtr
Offset 0x024C - Memory data pointer for saved preset search results The reference code will store the...
Definition: FspmUpd.h:578
FSP_M_CONFIG::PchHpetFunctionNumber
UINT8 PchHpetFunctionNumber
Offset 0x0312 - PCH HPET Function Number Function Number HPETn used as Requestor / Completer ID...
Definition: FspmUpd.h:960
FSP_M_CONFIG::CmdTriStateDis
UINT8 CmdTriStateDis
Offset 0x0191 - Command Tristate Support Enable/Disable Command Tristate; 0: Enable; 1: Disable...
Definition: FspmUpd.h:387
FSP_M_CONFIG::RingDownBin
UINT8 RingDownBin
Offset 0x02E3 - Ring Downbin Ring Downbin enable/disable.
Definition: FspmUpd.h:851
FSP_M_TEST_CONFIG::BdatEnable
UINT8 BdatEnable
Offset 0x0525 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data...
Definition: FspmUpd.h:1310
FSP_M_CONFIG::MmaTestContentPtr
UINT32 MmaTestContentPtr
Offset 0x0154 - MMA Test Content Pointer Pointer to MMA Test Content in Memory.
Definition: FspmUpd.h:246
FSP_M_TEST_CONFIG::DmiGen3EqPh3Method
UINT8 DmiGen3EqPh3Method
Offset 0x052C - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3.
Definition: FspmUpd.h:1359
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FspsUpd.h File Reference

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Classes | Macros | Enumerations
FspsUpd.h File Reference
#include <FspUpd.h>
#include <ConfigBlock/CpuConfigFspData.h>
Include dependency graph for FspsUpd.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | AZALIA_HEADER
Azalia Header structure. More...
struct | AUDIO_AZALIA_VERB_TABLE
Audio Azalia Verb Table structure. More...
struct | SI_PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...
struct | FSP_S_CONFIG
Fsp S Configuration. More...
struct | FSP_S_TEST_CONFIG
Fsp S Test Configuration. More...
struct | FSPS_UPD
Fsp S UPD Configuration. More...

Macros

#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64
Number of all PCH devices.

Enumerations

enum SI_PCH_INT_PIN
Refer to the definition of PCH_INT_PIN. More...

Detailed Description

Copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FspsUpd.h.

Enumeration Type Documentation

enum SI_PCH_INT_PIN

Refer to the definition of PCH_INT_PIN.

Enumerator
SiPchNoInt

No Interrupt Pin.

Definition at line 66 of file FspsUpd.h.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FspsUpd.h Source File

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FspsUpd.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
5
6 Redistribution and use in source and binary forms, with or without modification,
7 are permitted provided that the following conditions are met:
8
9 * Redistributions of source code must retain the above copyright notice, this
10 list of conditions and the following disclaimer.
11 * Redistributions in binary form must reproduce the above copyright notice, this
12 list of conditions and the following disclaimer in the documentation and/or
13 other materials provided with the distribution.
14 * Neither the name of Intel Corporation nor the names of its contributors may
15 be used to endorse or promote products derived from this software without
16 specific prior written permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 THE POSSIBILITY OF SUCH DAMAGE.
29
30 This file is automatically generated. Please do NOT modify !!!
31
32 **/
33
34 #ifndef __FSPSUPD_H__
35 #define __FSPSUPD_H__
36
37 #include <FspUpd.h>
38
39 #pragma pack(1)
40
41
42 #include <ConfigBlock/CpuConfigFspData.h>
43 ///
44 /// Azalia Header structure
45 ///
46 typedef struct {
47 UINT16 VendorId; ///< Codec Vendor ID
48 UINT16 DeviceId; ///< Codec Device ID
49 UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
50 UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
51 UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
52 UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
53 } AZALIA_HEADER;
54
55 ///
56 /// Audio Azalia Verb Table structure
57 ///
58 typedef struct {
59 AZALIA_HEADER Header; ///< AZALIA PCH header
60 UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
61 } AUDIO_AZALIA_VERB_TABLE;
62
63 ///
64 /// Refer to the definition of PCH_INT_PIN
65 ///
66 typedef enum {
67 SiPchNoInt, ///< No Interrupt Pin
68 SiPchIntA,
69 SiPchIntB,
70 SiPchIntC,
71 SiPchIntD
72 } SI_PCH_INT_PIN;
73 ///
74 /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
75 ///
76 typedef struct {
77 UINT8 Device; ///< Device number
78 UINT8 Function; ///< Device function
79 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
80 UINT8 Irq; ///< IRQ to be set for device.
81 } SI_PCH_DEVICE_INTERRUPT_CONFIG;
82
83 #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
84
85
86 /** Fsp S Configuration
87 **/
88 typedef struct {
89
90 /** Offset 0x0020 - Logo Pointer
91 Points to PEI Display Logo Image
92 **/
93 UINT32 LogoPtr;
94
95 /** Offset 0x0024 - Logo Size
96 Size of PEI Display Logo Image
97 **/
98 UINT32 LogoSize;
99
100 /** Offset 0x0028 - Graphics Configuration Ptr
101 Points to VBT
102 **/
103 UINT32 GraphicsConfigPtr;
104
105 /** Offset 0x002C - Enable Device 4
106 Enable/disable Device 4
107 $EN_DIS
108 **/
109 UINT8 Device4Enable;
110
111 /** Offset 0x002D - Enable Intel HD Audio (Azalia)
112 Enable/disable Azalia controller.
113 $EN_DIS
114 **/
115 UINT8 PchHdaEnable;
116
117 /** Offset 0x002E - Enable HD Audio DSP
118 Enable/disable HD Audio DSP feature.
119 $EN_DIS
120 **/
121 UINT8 PchHdaDspEnable;
122
123 /** Offset 0x002F - Select HDAudio IoBuffer Ownership
124 Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 /
125 I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link
126 owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4
127 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports
128 own all the I/O buffers.
129 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports
130 **/
131 UINT8 PchHdaIoBufferOwnership;
132
133 /** Offset 0x0030 - Enable CIO2 Controller
134 Enable/disable SKYCAM CIO2 Controller.
135 $EN_DIS
136 **/
137 UINT8 PchCio2Enable;
138
139 /** Offset 0x0031 - Enable eMMC Controller
140 Enable/disable eMMC Controller.
141 $EN_DIS
142 **/
143 UINT8 ScsEmmcEnabled;
144
145 /** Offset 0x0032 - Enable eMMC HS400 Mode
146 Enable eMMC HS400 Mode.
147 $EN_DIS
148 **/
149 UINT8 ScsEmmcHs400Enabled;
150
151 /** Offset 0x0033 - Enable SdCard Controller
152 Enable/disable SD Card Controller.
153 $EN_DIS
154 **/
155 UINT8 ScsSdCardEnabled;
156
157 /** Offset 0x0034 - Enable PCH ISH Controller
158 Enable/disable ISH Controller.
159 $EN_DIS
160 **/
161 UINT8 PchIshEnable;
162
163 /** Offset 0x0035 - Show SPI controller
164 Enable/disable to show SPI controller.
165 $EN_DIS
166 **/
167 UINT8 ShowSpiController;
168
169 /** Offset 0x0036 - Flash Configuration Lock Down
170 Enable/disable flash lock down. If platform decides to skip this programming, it
171 must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
172 $EN_DIS
173 **/
174 UINT8 SpiFlashCfgLockDown;
175
176 /** Offset 0x0037
177 **/
178 UINT8 UnusedUpdSpace0;
179
180 /** Offset 0x0038 - MicrocodeRegionBase
181 Memory Base of Microcode Updates
182 **/
183 UINT32 MicrocodeRegionBase;
184
185 /** Offset 0x003C - MicrocodeRegionSize
186 Size of Microcode Updates
187 **/
188 UINT32 MicrocodeRegionSize;
189
190 /** Offset 0x0040 - Turbo Mode
191 Enable/Disable Turbo mode. 0: disable, 1: enable
192 $EN_DIS
193 **/
194 UINT8 TurboMode;
195
196 /** Offset 0x0041 - Enable SATA SALP Support
197 Enable/disable SATA Aggressive Link Power Management.
198 $EN_DIS
199 **/
200 UINT8 SataSalpSupport;
201
202 /** Offset 0x0042 - Enable SATA ports
203 Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
204 and so on.
205 **/
206 UINT8 SataPortsEnable[8];
207
208 /** Offset 0x004A - Enable SATA DEVSLP Feature
209 Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
210 port, byte0 for port0, byte1 for port1, and so on.
211 **/
212 UINT8 SataPortsDevSlp[8];
213
214 /** Offset 0x0052 - Enable USB2 ports
215 Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
216 port1, and so on.
217 **/
218 UINT8 PortUsb20Enable[16];
219
220 /** Offset 0x0062 - Enable USB3 ports
221 Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
222 port1, and so on.
223 **/
224 UINT8 PortUsb30Enable[10];
225
226 /** Offset 0x006C - Enable xDCI controller
227 Enable/disable to xDCI controller.
228 $EN_DIS
229 **/
230 UINT8 XdciEnable;
231
232 /** Offset 0x006D - Enable XHCI SSIC Enable
233 Enable/disable XHCI SSIC port.
234 $EN_DIS
235 **/
236 UINT8 SsicPortEnable;
237
238 /** Offset 0x006E
239 **/
240 UINT8 UnusedUpdSpace1;
241
242 /** Offset 0x006F - Number of DevIntConfig Entry
243 Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
244 must not be NULL.
245 **/
246 UINT8 NumOfDevIntConfig;
247
248 /** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
249 The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
250 **/
251 UINT32 DevIntConfigPtr;
252
253 /** Offset 0x0074 - Enable SerialIo Device Mode
254 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable
255 SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode
256 respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
257 **/
258 UINT8 SerialIoDevMode[11];
259
260 /** Offset 0x007F - PIRQx to IRQx Map Config
261 PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
262 PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
263 8259 PCI mode.
264 **/
265 UINT8 PxRcConfig[8];
266
267 /** Offset 0x0087 - Select GPIO IRQ Route
268 GPIO IRQ Select. The valid value is 14 or 15.
269 **/
270 UINT8 GpioIrqRoute;
271
272 /** Offset 0x0088 - Select SciIrqSelect
273 SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
274 **/
275 UINT8 SciIrqSelect;
276
277 /** Offset 0x0089 - Select TcoIrqSelect
278 TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
279 **/
280 UINT8 TcoIrqSelect;
281
282 /** Offset 0x008A - Enable/Disable Tco IRQ
283 Enable/disable TCO IRQ
284 $EN_DIS
285 **/
286 UINT8 TcoIrqEnable;
287
288 /** Offset 0x008B - PCH HDA Verb Table Entry Number
289 Number of Entries in Verb Table.
290 **/
291 UINT8 PchHdaVerbTableEntryNum;
292
293 /** Offset 0x008C - PCH HDA Verb Table Pointer
294 Pointer to Array of pointers to Verb Table.
295 **/
296 UINT32 PchHdaVerbTablePtr;
297
298 /** Offset 0x0090
299 **/
300 UINT8 UnusedUpdSpace2;
301
302 /** Offset 0x0091 - Enable SATA
303 Enable/disable SATA controller.
304 $EN_DIS
305 **/
306 UINT8 SataEnable;
307
308 /** Offset 0x0092 - SATA Mode
309 Select SATA controller working mode.
310 0:AHCI, 1:RAID
311 **/
312 UINT8 SataMode;
313
314 /** Offset 0x0093 - USB Per Port HS Preemphasis Bias
315 USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
316 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
317 **/
318 UINT8 Usb2AfePetxiset[16];
319
320 /** Offset 0x00A3 - USB Per Port HS Transmitter Bias
321 USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
322 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
323 **/
324 UINT8 Usb2AfeTxiset[16];
325
326 /** Offset 0x00B3 - USB Per Port HS Transmitter Emphasis
327 USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
328 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
329 **/
330 UINT8 Usb2AfePredeemp[16];
331
332 /** Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis
333 USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
334 One byte for each port.
335 **/
336 UINT8 Usb2AfePehalfbit[16];
337
338 /** Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
339 Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
340 in arrary can be between 0-1. One byte for each port.
341 **/
342 UINT8 Usb3HsioTxDeEmphEnable[10];
343
344 /** Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
345 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
346 <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
347 **/
348 UINT8 Usb3HsioTxDeEmph[10];
349
350 /** Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
351 Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
352 in arrary can be between 0-1. One byte for each port.
353 **/
354 UINT8 Usb3HsioTxDownscaleAmpEnable[10];
355
356 /** Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment
357 USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
358 = 00h</b>. One byte for each port.
359 **/
360 UINT8 Usb3HsioTxDownscaleAmp[10];
361
362 /** Offset 0x00FB - Enable LAN
363 Enable/disable LAN controller.
364 $EN_DIS
365 **/
366 UINT8 PchLanEnable;
367
368 /** Offset 0x00FC - Delay USB PDO Programming
369 Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0:
370 disable, 1: enable
371 $EN_DIS
372 **/
373 UINT8 DelayUsbPdoProgramming;
374
375 /** Offset 0x00FD
376 **/
377 UINT8 UnusedUpdSpace3[23];
378
379 /** Offset 0x0114 - Enable PCIE RP CLKREQ Support
380 Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for
381 each port, byte0 for port1, byte1 for port2, and so on.
382 **/
383 UINT8 PcieRpClkReqSupport[24];
384
385 /** Offset 0x012C - Configure CLKREQ Number
386 Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can
387 be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
388 **/
389 UINT8 PcieRpClkReqNumber[24];
390
391 /** Offset 0x0144
392 **/
393 UINT8 UnusedUpdSpace4[5];
394
395 /** Offset 0x0149 - HECI3 state
396 The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
397 0: disable, 1: enable
398 $EN_DIS
399 **/
400 UINT8 Heci3Enabled;
401
402 /** Offset 0x014A
403 **/
404 UINT8 UnusedUpdSpace5[9];
405
406 /** Offset 0x0153 - AMT Switch
407 Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
408 $EN_DIS
409 **/
410 UINT8 AmtEnabled;
411
412 /** Offset 0x0154 - WatchDog Timer Switch
413 Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
414 $EN_DIS
415 **/
416 UINT8 WatchDog;
417
418 /** Offset 0x0155 - ASF Switch
419 Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
420 $EN_DIS
421 **/
422 UINT8 AsfEnabled;
423
424 /** Offset 0x0156 - Manageability Mode set by Mebx
425 Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
426 $EN_DIS
427 **/
428 UINT8 ManageabilityMode;
429
430 /** Offset 0x0157 - PET Progress
431 Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
432 PET Events.
433 $EN_DIS
434 **/
435 UINT8 FwProgress;
436
437 /** Offset 0x0158 - OS Timer
438 16 bits Value, Set OS watchdog timer.
439 $EN_DIS
440 **/
441 UINT16 WatchDogTimerOs;
442
443 /** Offset 0x015A - BIOS Timer
444 16 bits Value, Set BIOS watchdog timer.
445 $EN_DIS
446 **/
447 UINT16 WatchDogTimerBios;
448
449 /** Offset 0x015C - SOL Switch
450 Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
451 $EN_DIS
452 **/
453 UINT8 AmtSolEnabled;
454
455 /** Offset 0x015D - Configure CLKSRC Number
456 Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid
457 clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for
458 port1, byte1 for port2, and so on.
459 **/
460 UINT8 PcieRpClkSrcNumber[24];
461
462 /** Offset 0x0175
463 **/
464 UINT8 UnusedUpdSpace6[139];
465
466 /** Offset 0x0200 - Subsystem Vendor ID for SA devices
467 Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086
468 **/
469 UINT16 DefaultSvid;
470
471 /** Offset 0x0202 - Subsystem Device ID for SA devices
472 Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015
473 **/
474 UINT16 DefaultSid;
475
476 /** Offset 0x0204 - Enable/Disable SA CRID
477 Enable: SA CRID, Disable (Default): SA CRID
478 $EN_DIS
479 **/
480 UINT8 CridEnable;
481
482 /** Offset 0x0205 - DMI ASPM
483 0=Disable, 2(Default)=L1
484 0:Disable, 2:L1
485 **/
486 UINT8 DmiAspm;
487
488 /** Offset 0x0206 - PCIe Physical Slot Number per root port
489 Physical Slot Number per root port
490 **/
491 UINT16 PegPhysicalSlotNumber[3];
492
493 /** Offset 0x020C - PCIe DeEmphasis control per root port
494 0: -6dB, 1(Default): -3.5dB
495 0:-6dB, 1:-3.5dB
496 **/
497 UINT8 PegDeEmphasis[3];
498
499 /** Offset 0x020F - PCIe Slot Power Limit value per root port
500 Slot power limit value per root port
501 **/
502 UINT8 PegSlotPowerLimitValue[3];
503
504 /** Offset 0x0212 - PCIe Slot Power Limit scale per root port
505 Slot power limit scale per root port
506 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
507 **/
508 UINT8 PegSlotPowerLimitScale[3];
509
510 /** Offset 0x0215 - Enable/Disable PavpEnable
511 Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
512 $EN_DIS
513 **/
514 UINT8 PavpEnable;
515
516 /** Offset 0x0216 - CdClock Frequency selection
517 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz
518 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
519 **/
520 UINT8 CdClock;
521
522 /** Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit
523 Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
524 $EN_DIS
525 **/
526 UINT8 PeiGraphicsPeimInit;
527
528 /** Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM)
529 Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM)
530 $EN_DIS
531 **/
532 UINT8 SaImguEnable;
533
534 /** Offset 0x0219 - Enable or disable GMM device
535 0=Disable, 1(Default)=Enable
536 $EN_DIS
537 **/
538 UINT8 GmmEnable;
539
540 /** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table
541 0=Disable/Clear, 1=Enable/Set
542 $EN_DIS
543 **/
544 UINT8 X2ApicOptOut;
545
546 /** Offset 0x021B
547 **/
548 UINT8 UnusedUpdSpace7[1];
549
550 /** Offset 0x021C - Base addresses for VT-d function MMIO access
551 Base addresses for VT-d MMIO access per VT-d engine
552 **/
553 UINT32 VtdBaseAddress[2];
554
555 /** Offset 0x0224
556 **/
557 UINT8 UnusedUpdSpace8[19];
558
559 /** Offset 0x0237 - SaPostMemProductionRsvd
560 Reserved for SA Post-Mem Production
561 $EN_DIS
562 **/
563 UINT8 SaPostMemProductionRsvd[16];
564
565 /** Offset 0x0247
566 **/
567 UINT8 UnusedUpdSpace9[7];
568
569 /** Offset 0x024E - Power State 3 enable/disable
570 PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
571 For all VR Indexes
572 **/
573 UINT8 Psi3Enable[5];
574
575 /** Offset 0x0253 - Power State 4 enable/disable
576 PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
577 all VR Indexes
578 **/
579 UINT8 Psi4Enable[5];
580
581 /** Offset 0x0258 - Imon slope correction
582 PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
583 Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
584 **/
585 UINT8 ImonSlope[5];
586
587 /** Offset 0x025D - Imon offset correction
588 PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
589 Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
590 **/
591 UINT8 ImonOffset[5];
592
593 /** Offset 0x0262 - Enable/Disable BIOS configuration of VR
594 Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
595 **/
596 UINT8 VrConfigEnable[5];
597
598 /** Offset 0x0267 - Thermal Design Current enable/disable
599 PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
600 Enable.For all VR Indexes
601 **/
602 UINT8 TdcEnable[5];
603
604 /** Offset 0x026C - HECI3 state
605 PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
606 Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
607 , 8 - 8ms , 10 - 10ms.For all VR Indexe
608 **/
609 UINT8 TdcTimeWindow[5];
610
611 /** Offset 0x0271 - Thermal Design Current Lock
612 PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
613 all VR Indexes
614 **/
615 UINT8 TdcLock[5];
616
617 /** Offset 0x0276 - Platform Psys slope correction
618 PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
619 1/100 increment values. Range is 0-200. 125 = 1.25
620 **/
621 UINT8 PsysSlope;
622
623 /** Offset 0x0277 - Platform Psys offset correction
624 PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
625 Range 0-255. Value of 100 = 100/4 = 25 offset
626 **/
627 UINT8 PsysOffset;
628
629 /** Offset 0x0278 - Acoustic Noise Mitigation feature
630 Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
631 $EN_DIS
632 **/
633 UINT8 AcousticNoiseMitigation;
634
635 /** Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
636 Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
637 feature enabled. <b>0: False</b>; 1: True
638 $EN_DIS
639 **/
640 UINT8 FastPkgCRampDisableIa;
641
642 /** Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain
643 Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
644 Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
645 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
646 **/
647 UINT8 SlowSlewRateForIa;
648
649 /** Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain
650 Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
651 Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
652 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
653 **/
654 UINT8 SlowSlewRateForGt;
655
656 /** Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain
657 Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
658 Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
659 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
660 **/
661 UINT8 SlowSlewRateForSa;
662
663 /** Offset 0x027D
664 **/
665 UINT8 UnusedUpdSpace10[9];
666
667 /** Offset 0x0286 - Thermal Design Current current limit
668 PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
669 Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
670 **/
671 UINT16 TdcPowerLimit[5];
672
673 /** Offset 0x0290 - CPU VR Power Delivery Design
674 Used to communicate the power delivery design capability of the board. This value
675 is an enum of the available power delivery segments that are defined in the Platform
676 Design Guide.
677 **/
678 UINT32 VrPowerDeliveryDesign;
679
680 /** Offset 0x0294
681 **/
682 UINT8 UnusedUpdSpace11[4];
683
684 /** Offset 0x0298 - AcLoadline
685 PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
686 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
687 **/
688 UINT16 AcLoadline[5];
689
690 /** Offset 0x02A2 - DcLoadline
691 PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
692 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
693 **/
694 UINT16 DcLoadline[5];
695
696 /** Offset 0x02AC - Power State 1 Threshold current
697 PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is
698 0-128A. Default Value = 20A.
699 **/
700 UINT16 Psi1Threshold[5];
701
702 /** Offset 0x02B6 - Power State 2 Threshold current
703 PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is
704 0-128A. Default Value = 5A.
705 **/
706 UINT16 Psi2Threshold[5];
707
708 /** Offset 0x02C0 - Power State 3 Threshold current
709 PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is
710 0-128A. Default Value = 1A.
711 **/
712 UINT16 Psi3Threshold[5];
713
714 /** Offset 0x02CA - Icc Max limit
715 PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
716 **/
717 UINT16 IccMax[5];
718
719 /** Offset 0x02D4 - VR Voltage Limit
720 PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
721 **/
722 UINT16 VrVoltageLimit[5];
723
724 /** Offset 0x02DE
725 **/
726 UINT8 UnusedUpdSpace12;
727
728 /** Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain
729 Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
730 feature enabled. <b>0: False</b>; 1: True
731 $EN_DIS
732 **/
733 UINT8 FastPkgCRampDisableGt;
734
735 /** Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
736 Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
737 feature enabled. <b>0: False</b>; 1: True
738 $EN_DIS
739 **/
740 UINT8 FastPkgCRampDisableSa;
741
742 /** Offset 0x02E1
743 **/
744 UINT8 UnusedUpdSpace13;
745
746 /** Offset 0x02E2 - Enable VR specific mailbox command
747 VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
748 VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
749 command sent for PS4 exit issue. 11b - Reserved.
750 $EN_DIS
751 **/
752 UINT8 SendVrMbxCmd;
753
754 /** Offset 0x02E3 - Select VR specific mailbox command to send
755 VR specific mailbox commands. <b>000b - no VR specific command sent.</b> 001b -
756 VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific
757 command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue.
758 **/
759 UINT8 SendVrMbxCmd1;
760
761 /** Offset 0x02E4 - CpuS3ResumeMtrrData
762 Pointer to CPU S3 Resume MTRR Data
763 **/
764 UINT32 CpuS3ResumeMtrrData;
765
766 /** Offset 0x02E8 - Cpu Configuration
767 Cpu Configuration data.
768 **/
769 CPU_CONFIG_FSP_DATA CpuConfig;
770
771 /** Offset 0x02F0 - MicrocodePatchAddress
772 Pointer to microcode patch that is suitable for this processor.
773 0:Disable, 1:Enable
774 **/
775 UINT64 MicrocodePatchAddress;
776
777 /** Offset 0x02F8 - CpuS3ResumeMtrrDataSize
778 Size of S3 resume MTRR data.
779 **/
780 UINT16 CpuS3ResumeMtrrDataSize;
781
782 /** Offset 0x02FA
783 **/
784 UINT8 UnusedUpdSpace14;
785
786 /** Offset 0x02FB - Enable SkyCam PortA Termination override
787 Enable/disable PortA Termination override.
788 $EN_DIS
789 **/
790 UINT8 PchSkyCamPortATermOvrEnable;
791
792 /** Offset 0x02FC - Enable SkyCam PortB Termination override
793 Enable/disable PortB Termination override.
794 $EN_DIS
795 **/
796 UINT8 PchSkyCamPortBTermOvrEnable;
797
798 /** Offset 0x02FD - Enable SkyCam PortC Termination override
799 Enable/disable PortC Termination override.
800 $EN_DIS
801 **/
802 UINT8 PchSkyCamPortCTermOvrEnable;
803
804 /** Offset 0x02FE - Enable SkyCam PortD Termination override
805 Enable/disable PortD Termination override.
806 $EN_DIS
807 **/
808 UINT8 PchSkyCamPortDTermOvrEnable;
809
810 /** Offset 0x02FF - Enable SkyCam PortA Clk Trim
811 Enable/disable PortA Clk Trim.
812 $EN_DIS
813 **/
814 UINT8 PchSkyCamPortATrimEnable;
815
816 /** Offset 0x0300 - Enable SkyCam PortB Clk Trim
817 Enable/disable PortB Clk Trim.
818 $EN_DIS
819 **/
820 UINT8 PchSkyCamPortBTrimEnable;
821
822 /** Offset 0x0301 - Enable SkyCam PortC Clk Trim
823 Enable/disable PortC Clk Trim.
824 $EN_DIS
825 **/
826 UINT8 PchSkyCamPortCTrimEnable;
827
828 /** Offset 0x0302 - Enable SkyCam PortD Clk Trim
829 Enable/disable PortD Clk Trim.
830 $EN_DIS
831 **/
832 UINT8 PchSkyCamPortDTrimEnable;
833
834 /** Offset 0x0303 - Enable SkyCam PortA Ctle
835 Enable/disable PortA Ctle.
836 $EN_DIS
837 **/
838 UINT8 PchSkyCamPortACtleEnable;
839
840 /** Offset 0x0304 - Enable SkyCam PortB Ctle
841 Enable/disable PortB Ctle.
842 $EN_DIS
843 **/
844 UINT8 PchSkyCamPortBCtleEnable;
845
846 /** Offset 0x0305 - Enable SkyCam PortCD Ctle
847 Enable/disable PortCD Ctle.
848 $EN_DIS
849 **/
850 UINT8 PchSkyCamPortCDCtleEnable;
851
852 /** Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value
853 Enable/disable PortA Ctle Cap Value.
854 **/
855 UINT8 PchSkyCamPortACtleCapValue;
856
857 /** Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value
858 Enable/disable PortB Ctle Cap Value.
859 **/
860 UINT8 PchSkyCamPortBCtleCapValue;
861
862 /** Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value
863 Enable/disable PortCD Ctle Cap Value.
864 **/
865 UINT8 PchSkyCamPortCDCtleCapValue;
866
867 /** Offset 0x0309 - Enable SkyCam PortA Ctle Res Value
868 Enable/disable PortA Ctle Res Value.
869 **/
870 UINT8 PchSkyCamPortACtleResValue;
871
872 /** Offset 0x030A - Enable SkyCam PortB Ctle Res Value
873 Enable/disable PortB Ctle Res Value.
874 **/
875 UINT8 PchSkyCamPortBCtleResValue;
876
877 /** Offset 0x030B - Enable SkyCam PortCD Ctle Res Value
878 Enable/disable PortCD Ctle Res Value.
879 **/
880 UINT8 PchSkyCamPortCDCtleResValue;
881
882 /** Offset 0x030C - Enable SkyCam PortA Clk Trim Value
883 Enable/disable PortA Clk Trim Value.
884 **/
885 UINT8 PchSkyCamPortAClkTrimValue;
886
887 /** Offset 0x030D - Enable SkyCam PortB Clk Trim Value
888 Enable/disable PortB Clk Trim Value.
889 **/
890 UINT8 PchSkyCamPortBClkTrimValue;
891
892 /** Offset 0x030E - Enable SkyCam PortC Clk Trim Value
893 Enable/disable PortC Clk Trim Value.
894 **/
895 UINT8 PchSkyCamPortCClkTrimValue;
896
897 /** Offset 0x030F - Enable SkyCam PortD Clk Trim Value
898 Enable/disable PortD Clk Trim Value.
899 **/
900 UINT8 PchSkyCamPortDClkTrimValue;
901
902 /** Offset 0x0310 - Enable SkyCam Port A Data Trim Value
903 Enable/disable Port A Data Trim Value.
904 **/
905 UINT16 PchSkyCamPortADataTrimValue;
906
907 /** Offset 0x0312 - Enable SkyCam Port B Data Trim Value
908 Enable/disable Port B Data Trim Value.
909 **/
910 UINT16 PchSkyCamPortBDataTrimValue;
911
912 /** Offset 0x0314 - Enable SkyCam C/D Data Trim Value
913 Enable/disable C/D Data Trim Value.
914 **/
915 UINT16 PchSkyCamPortCDDataTrimValue;
916
917 /** Offset 0x0316 - Enable DMI ASPM
918 ASPM on PCH side of the DMI Link.
919 $EN_DIS
920 **/
921 UINT8 PchDmiAspm;
922
923 /** Offset 0x0317 - Enable Power Optimizer
924 Enable DMI Power Optimizer on PCH side.
925 $EN_DIS
926 **/
927 UINT8 PchPwrOptEnable;
928
929 /** Offset 0x0318 - PCH Flash Protection Ranges Write Enble
930 Write or erase is blocked by hardware.
931 **/
932 UINT8 PchWriteProtectionEnable[5];
933
934 /** Offset 0x031D - PCH Flash Protection Ranges Read Enble
935 Read is blocked by hardware.
936 **/
937 UINT8 PchReadProtectionEnable[5];
938
939 /** Offset 0x0322 - PCH Protect Range Limit
940 Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
941 limit comparison.
942 **/
943 UINT16 PchProtectedRangeLimit[5];
944
945 /** Offset 0x032C - PCH Protect Range Base
946 Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
947 **/
948 UINT16 PchProtectedRangeBase[5];
949
950 /** Offset 0x0336 - Enable Pme
951 Enable Azalia wake-on-ring.
952 $EN_DIS
953 **/
954 UINT8 PchHdaPme;
955
956 /** Offset 0x0337 - IO Buffer Voltage
957 I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V.
958 **/
959 UINT8 PchHdaIoBufferVoltage;
960
961 /** Offset 0x0338 - VC Type
962 Virtual Channel Type Select: 0: VC0, 1: VC1.
963 **/
964 UINT8 PchHdaVcType;
965
966 /** Offset 0x0339 - HD Audio Link Frequency
967 HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz.
968 **/
969 UINT8 PchHdaLinkFrequency;
970
971 /** Offset 0x033A - iDisp-Link Frequency
972 iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
973 **/
974 UINT8 PchHdaIDispLinkFrequency;
975
976 /** Offset 0x033B - iDisp-Link T-mode
977 iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
978 **/
979 UINT8 PchHdaIDispLinkTmode;
980
981 /** Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system
982 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
983 driver or SST driver supported).
984 $EN_DIS
985 **/
986 UINT8 PchHdaDspUaaCompliance;
987
988 /** Offset 0x033D - iDisplay Audio Codec disconnection
989 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
990 $EN_DIS
991 **/
992 UINT8 PchHdaIDispCodecDisconnect;
993
994 /** Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum)
995 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array.
996 **/
997 UINT8 PchHdaDspEndpointDmic;
998
999 /** Offset 0x033F - DSP Bluetooth enablement
1000 0: Disable; 1: Enable.
1001 $EN_DIS
1002 **/
1003 UINT8 PchHdaDspEndpointBluetooth;
1004
1005 /** Offset 0x0340 - Bitmask of supported DSP features
1006 [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6]
1007 - BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0:
1008 Intel WoV, 1: Windows Voice Activation.
1009 **/
1010 UINT32 PchHdaDspFeatureMask;
1011
1012 /** Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules
1013 Deprecated: Specific pre/post-processing module bit position must be coherent with
1014 the ACPI implementation: \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing
1015 Module Support.
1016 **/
1017 UINT32 PchHdaDspPpModuleMask;
1018
1019 /** Offset 0x0348 - DSP I2S enablement
1020 0: Disable; 1: Enable.
1021 $EN_DIS
1022 **/
1023 UINT8 PchHdaDspEndpointI2s;
1024
1025 /** Offset 0x0349 - Enable PCH Io Apic
1026 Set to 1 if BDF value is valid.
1027 $EN_DIS
1028 **/
1029 UINT8 PchIoApicBdfValid;
1030
1031 /** Offset 0x034A - PCH Io Apic Bus Number
1032 Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0.
1033 **/
1034 UINT8 PchIoApicBusNumber;
1035
1036 /** Offset 0x034B - PCH Io Apic Device Number
1037 Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F.
1038 **/
1039 UINT8 PchIoApicDeviceNumber;
1040
1041 /** Offset 0x034C - PCH Io Apic Function Number
1042 Bus/Device/Function used as Requestor / Completer ID. Default is 0x00.
1043 **/
1044 UINT8 PchIoApicFunctionNumber;
1045
1046 /** Offset 0x034D - Enable PCH Io Apic Entry 24-119
1047 0: Disable; 1: Enable.
1048 $EN_DIS
1049 **/
1050 UINT8 PchIoApicEntry24_119;
1051
1052 /** Offset 0x034E - PCH Io Apic ID
1053 This member determines IOAPIC ID. Default is 0x02.
1054 **/
1055 UINT8 PchIoApicId;
1056
1057 /** Offset 0x034F - PCH Io Apic Range Select
1058 Define address bits 19:12 for the IOxAPIC range. Default is 0.
1059 **/
1060 UINT8 PchIoApicRangeSelect;
1061
1062 /** Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned
1063 0: Disable; 1: Enable.
1064 $EN_DIS
1065 **/
1066 UINT8 PchIshSpiGpioAssign;
1067
1068 /** Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned
1069 0: Disable; 1: Enable.
1070 $EN_DIS
1071 **/
1072 UINT8 PchIshUart0GpioAssign;
1073
1074 /** Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned
1075 0: Disable; 1: Enable.
1076 $EN_DIS
1077 **/
1078 UINT8 PchIshUart1GpioAssign;
1079
1080 /** Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned
1081 0: Disable; 1: Enable.
1082 $EN_DIS
1083 **/
1084 UINT8 PchIshI2c0GpioAssign;
1085
1086 /** Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned
1087 0: Disable; 1: Enable.
1088 $EN_DIS
1089 **/
1090 UINT8 PchIshI2c1GpioAssign;
1091
1092 /** Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned
1093 0: Disable; 1: Enable.
1094 $EN_DIS
1095 **/
1096 UINT8 PchIshI2c2GpioAssign;
1097
1098 /** Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned
1099 0: Disable; 1: Enable.
1100 $EN_DIS
1101 **/
1102 UINT8 PchIshGp0GpioAssign;
1103
1104 /** Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned
1105 0: Disable; 1: Enable.
1106 $EN_DIS
1107 **/
1108 UINT8 PchIshGp1GpioAssign;
1109
1110 /** Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned
1111 0: Disable; 1: Enable.
1112 $EN_DIS
1113 **/
1114 UINT8 PchIshGp2GpioAssign;
1115
1116 /** Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned
1117 0: Disable; 1: Enable.
1118 $EN_DIS
1119 **/
1120 UINT8 PchIshGp3GpioAssign;
1121
1122 /** Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned
1123 0: Disable; 1: Enable.
1124 $EN_DIS
1125 **/
1126 UINT8 PchIshGp4GpioAssign;
1127
1128 /** Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned
1129 0: Disable; 1: Enable.
1130 $EN_DIS
1131 **/
1132 UINT8 PchIshGp5GpioAssign;
1133
1134 /** Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned
1135 0: Disable; 1: Enable.
1136 $EN_DIS
1137 **/
1138 UINT8 PchIshGp6GpioAssign;
1139
1140 /** Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned
1141 0: Disable; 1: Enable.
1142 $EN_DIS
1143 **/
1144 UINT8 PchIshGp7GpioAssign;
1145
1146 /** Offset 0x035E - PCH ISH PDT Unlock Msg
1147 0: False; 1: True.
1148 $EN_DIS
1149 **/
1150 UINT8 PchIshPdtUnlock;
1151
1152 /** Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN
1153 0: Disable; 1: Enable.
1154 $EN_DIS
1155 **/
1156 UINT8 PchLanLtrEnable;
1157
1158 /** Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management
1159 0: Disable; 1: Enable.
1160 $EN_DIS
1161 **/
1162 UINT8 PchLanK1OffEnable;
1163
1164 /** Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported
1165 0: Disable; 1: Enable.
1166 $EN_DIS
1167 **/
1168 UINT8 PchLanClkReqSupported;
1169
1170 /** Offset 0x0362 - CLKREQ# used by GbE
1171 Valid if ClkReqSupported is TRUE.
1172 **/
1173 UINT8 PchLanClkReqNumber;
1174
1175 /** Offset 0x0363 - Enable LOCKDOWN BIOS LOCK
1176 Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
1177 protection.
1178 $EN_DIS
1179 **/
1180 UINT8 PchLockDownBiosLock;
1181
1182 /** Offset 0x0364 - Enable LOCKDOWN SPI Eiss
1183 Enable InSMM.STS (EISS) in SPI.
1184 $EN_DIS
1185 **/
1186 UINT8 PchLockDownSpiEiss;
1187
1188 /** Offset 0x0365 - PCH Compatibility Revision ID
1189 This member describes whether or not the CRID feature of PCH should be enabled.
1190 $EN_DIS
1191 **/
1192 UINT8 PchCrid;
1193
1194 /** Offset 0x0366 - PCH Sub system vendor ID
1195 Default Subsystem Vendor ID of the PCH devices. Default is 0x8086.
1196 **/
1197 UINT16 PchSubSystemVendorId;
1198
1199 /** Offset 0x0368 - PCH Sub system ID
1200 Default Subsystem ID of the PCH devices. Default is 0x7270.
1201 **/
1202 UINT16 PchSubSystemId;
1203
1204 /** Offset 0x036A - PCH Legacy IO Low Latency Enable
1205 todo
1206 $EN_DIS
1207 **/
1208 UINT8 PchLegacyIoLowLatency;
1209
1210 /** Offset 0x036B
1211 **/
1212 UINT8 UnusedUpdSpace15[5];
1213
1214 /** Offset 0x0370 - Enable PCIE RP HotPlug
1215 Indicate whether the root port is hot plug available.
1216 **/
1217 UINT8 PcieRpHotPlug[24];
1218
1219 /** Offset 0x0388 - Enable PCIE RP Pm Sci
1220 Indicate whether the root port power manager SCI is enabled.
1221 **/
1222 UINT8 PcieRpPmSci[24];
1223
1224 /** Offset 0x03A0 - Enable PCIE RP Ext Sync
1225 Indicate whether the extended synch is enabled.
1226 **/
1227 UINT8 PcieRpExtSync[24];
1228
1229 /** Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing
1230 Indicate whether the Transmitter Half Swing is enabled.
1231 **/
1232 UINT8 PcieRpTransmitterHalfSwing[24];
1233
1234 /** Offset 0x03D0 - Enable PCIE RP Clk Req Detect
1235 Probe CLKREQ# signal before enabling CLKREQ# based power management.
1236 **/
1237 UINT8 PcieRpClkReqDetect[24];
1238
1239 /** Offset 0x03E8 - PCIE RP Advanced Error Report
1240 Indicate whether the Advanced Error Reporting is enabled.
1241 **/
1242 UINT8 PcieRpAdvancedErrorReporting[24];
1243
1244 /** Offset 0x0400 - PCIE RP Unsupported Request Report
1245 Indicate whether the Unsupported Request Report is enabled.
1246 **/
1247 UINT8 PcieRpUnsupportedRequestReport[24];
1248
1249 /** Offset 0x0418 - PCIE RP Fatal Error Report
1250 Indicate whether the Fatal Error Report is enabled.
1251 **/
1252 UINT8 PcieRpFatalErrorReport[24];
1253
1254 /** Offset 0x0430 - PCIE RP No Fatal Error Report
1255 Indicate whether the No Fatal Error Report is enabled.
1256 **/
1257 UINT8 PcieRpNoFatalErrorReport[24];
1258
1259 /** Offset 0x0448 - PCIE RP Correctable Error Report
1260 Indicate whether the Correctable Error Report is enabled.
1261 **/
1262 UINT8 PcieRpCorrectableErrorReport[24];
1263
1264 /** Offset 0x0460 - PCIE RP System Error On Fatal Error
1265 Indicate whether the System Error on Fatal Error is enabled.
1266 **/
1267 UINT8 PcieRpSystemErrorOnFatalError[24];
1268
1269 /** Offset 0x0478 - PCIE RP System Error On Non Fatal Error
1270 Indicate whether the System Error on Non Fatal Error is enabled.
1271 **/
1272 UINT8 PcieRpSystemErrorOnNonFatalError[24];
1273
1274 /** Offset 0x0490 - PCIE RP System Error On Correctable Error
1275 Indicate whether the System Error on Correctable Error is enabled.
1276 **/
1277 UINT8 PcieRpSystemErrorOnCorrectableError[24];
1278
1279 /** Offset 0x04A8 - PCIE RP Max Payload
1280 Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
1281 **/
1282 UINT8 PcieRpMaxPayload[24];
1283
1284 /** Offset 0x04C0 - PCIE RP Device Reset Pad Active High
1285 Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad.
1286 **/
1287 UINT8 PcieRpDeviceResetPadActiveHigh[24];
1288
1289 /** Offset 0x04D8 - PCIE RP Pcie Speed
1290 Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
1291 PCH_PCIE_SPEED).
1292 **/
1293 UINT8 PcieRpPcieSpeed[24];
1294
1295 /** Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method
1296 PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search;
1297 4: Fixed Coeficients.
1298 **/
1299 UINT8 PcieRpGen3EqPh3Method[24];
1300
1301 /** Offset 0x0508 - PCIE RP Physical Slot Number
1302 Indicates the slot number for the root port. Default is the value as root port index.
1303 **/
1304 UINT8 PcieRpPhysicalSlotNumber[24];
1305
1306 /** Offset 0x0520 - PCIE RP Completion Timeout
1307 The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
1308 **/
1309 UINT8 PcieRpCompletionTimeout[24];
1310
1311 /** Offset 0x0538 - PCIE RP Device Reset Pad
1312 The PCH pin assigned to device PERST# signal if available, zero otherwise. See
1313 also DeviceResetPadActiveHigh.
1314 **/
1315 UINT32 PcieRpDeviceResetPad[24];
1316
1317 /** Offset 0x0598 - PCIE RP Aspm
1318 The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
1319 PchPcieAspmAutoConfig.
1320 **/
1321 UINT8 PcieRpAspm[24];
1322
1323 /** Offset 0x05B0 - PCIE RP L1 Substates
1324 The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
1325 Default is PchPcieL1SubstatesL1_1_2.
1326 **/
1327 UINT8 PcieRpL1Substates[24];
1328
1329 /** Offset 0x05C8 - PCIE RP Ltr Enable
1330 Latency Tolerance Reporting Mechanism.
1331 **/
1332 UINT8 PcieRpLtrEnable[24];
1333
1334 /** Offset 0x05E0 - PCIE RP Ltr Config Lock
1335 0: Disable; 1: Enable.
1336 **/
1337 UINT8 PcieRpLtrConfigLock[24];
1338
1339 /** Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm
1340 PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
1341 **/
1342 UINT8 PcieEqPh3LaneParamCm[24];
1343
1344 /** Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp
1345 PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
1346 **/
1347 UINT8 PcieEqPh3LaneParamCp[24];
1348
1349 /** Offset 0x0628 - PCIE Sw Eq CoeffList Cm
1350 PCH_PCIE_EQ_PARAM. Coefficient C-1.
1351 **/
1352 UINT8 PcieSwEqCoeffListCm[5];
1353
1354 /** Offset 0x062D - PCIE Sw Eq CoeffList Cp
1355 PCH_PCIE_EQ_PARAM. Coefficient C+1.
1356 **/
1357 UINT8 PcieSwEqCoeffListCp[5];
1358
1359 /** Offset 0x0632 - PCIE Disable RootPort Clock Gating
1360 Describes whether the PCI Express Clock Gating for each root port is enabled by
1361 platform modules. 0: Disable; 1: Enable.
1362 $EN_DIS
1363 **/
1364 UINT8 PcieDisableRootPortClockGating;
1365
1366 /** Offset 0x0633 - PCIE Enable Peer Memory Write
1367 This member describes whether Peer Memory Writes are enabled on the platform.
1368 $EN_DIS
1369 **/
1370 UINT8 PcieEnablePeerMemoryWrite;
1371
1372 /** Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown
1373 Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
1374 or leaving untouched.
1375 $EN_DIS
1376 **/
1377 UINT8 PcieAllowNoLtrIccPllShutdown;
1378
1379 /** Offset 0x0635 - PCIE Compliance Test Mode
1380 Compliance Test Mode shall be enabled when using Compliance Load Board.
1381 $EN_DIS
1382 **/
1383 UINT8 PcieComplianceTestMode;
1384
1385 /** Offset 0x0636 - PCIE Rp Detect Timeout Ms
1386 Will wait for link to exit Detect state for enabled ports before assuming there
1387 is no device and potentially disabling the port.
1388 **/
1389 UINT16 PcieDetectTimeoutMs;
1390
1391 /** Offset 0x0638 - PCIE Rp Function Swap
1392 Allows BIOS to use root port function number swapping when root port of function
1393 0 is disabled.
1394 $EN_DIS
1395 **/
1396 UINT8 PcieRpFunctionSwap;
1397
1398 /** Offset 0x0639 - PCH Pm PME_B0_S5_DIS
1399 When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
1400 $EN_DIS
1401 **/
1402 UINT8 PchPmPmeB0S5Dis;
1403
1404 /** Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable
1405 Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state.
1406 $EN_DIS
1407 **/
1408 UINT8 PchPmSlpS0VmEnable;
1409
1410 /** Offset 0x063B
1411 **/
1412 UINT8 UnusedUpdSpace16[5];
1413
1414 /** Offset 0x0640 - PCH Pm Wol Enable Override
1415 Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
1416 $EN_DIS
1417 **/
1418 UINT8 PchPmWolEnableOverride;
1419
1420 /** Offset 0x0641 - PCH Pm Pcie Wake From DeepSx
1421 Determine if enable PCIe to wake from deep Sx.
1422 $EN_DIS
1423 **/
1424 UINT8 PchPmPcieWakeFromDeepSx;
1425
1426 /** Offset 0x0642 - PCH Pm WoW lan Enable
1427 Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
1428 $EN_DIS
1429 **/
1430 UINT8 PchPmWoWlanEnable;
1431
1432 /** Offset 0x0643 - PCH Pm WoW lan DeepSx Enable
1433 Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
1434 PWRM_CFG3 register.
1435 $EN_DIS
1436 **/
1437 UINT8 PchPmWoWlanDeepSxEnable;
1438
1439 /** Offset 0x0644 - PCH Pm Lan Wake From DeepSx
1440 Determine if enable LAN to wake from deep Sx.
1441 $EN_DIS
1442 **/
1443 UINT8 PchPmLanWakeFromDeepSx;
1444
1445 /** Offset 0x0645 - PCH Pm Deep Sx Pol
1446 Deep Sx Policy.
1447 $EN_DIS
1448 **/
1449 UINT8 PchPmDeepSxPol;
1450
1451 /** Offset 0x0646 - PCH Pm Slp S3 Min Assert
1452 SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
1453 **/
1454 UINT8 PchPmSlpS3MinAssert;
1455
1456 /** Offset 0x0647 - PCH Pm Slp S4 Min Assert
1457 SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
1458 **/
1459 UINT8 PchPmSlpS4MinAssert;
1460
1461 /** Offset 0x0648 - PCH Pm Slp Sus Min Assert
1462 SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
1463 **/
1464 UINT8 PchPmSlpSusMinAssert;
1465
1466 /** Offset 0x0649 - PCH Pm Slp A Min Assert
1467 SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
1468 **/
1469 UINT8 PchPmSlpAMinAssert;
1470
1471 /** Offset 0x064A
1472 **/
1473 UINT8 UnusedUpdSpace17[6];
1474
1475 /** Offset 0x0650 - PCH Pm Lpc Clock Run
1476 This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
1477 $EN_DIS
1478 **/
1479 UINT8 PchPmLpcClockRun;
1480
1481 /** Offset 0x0651 - PCH Pm Slp Strch Sus Up
1482 Enable SLP_X Stretching After SUS Well Power Up.
1483 $EN_DIS
1484 **/
1485 UINT8 PchPmSlpStrchSusUp;
1486
1487 /** Offset 0x0652 - PCH Pm Slp Lan Low Dc
1488 Enable/Disable SLP_LAN# Low on DC Power.
1489 $EN_DIS
1490 **/
1491 UINT8 PchPmSlpLanLowDc;
1492
1493 /** Offset 0x0653 - PCH Pm Pwr Btn Override Period
1494 PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
1495 **/
1496 UINT8 PchPmPwrBtnOverridePeriod;
1497
1498 /** Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown
1499 When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
1500 $EN_DIS
1501 **/
1502 UINT8 PchPmDisableDsxAcPresentPulldown;
1503
1504 /** Offset 0x0655 - PCH Pm Capsule Reset Type
1505 Deprecated: Determines type of reset issued during UpdateCapsule(). Always Warm reset.
1506 $EN_DIS
1507 **/
1508 UINT8 PchPmCapsuleResetType;
1509
1510 /** Offset 0x0656 - PCH Pm Disable Native Power Button
1511 Power button native mode disable.
1512 $EN_DIS
1513 **/
1514 UINT8 PchPmDisableNativePowerButton;
1515
1516 /** Offset 0x0657 - PCH Pm Slp S0 Enable
1517 Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
1518 $EN_DIS
1519 **/
1520 UINT8 PchPmSlpS0Enable;
1521
1522 /** Offset 0x0658 - PCH Pm ME_WAKE_STS
1523 Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
1524 $EN_DIS
1525 **/
1526 UINT8 PchPmMeWakeSts;
1527
1528 /** Offset 0x0659 - PCH Pm WOL_OVR_WK_STS
1529 Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
1530 $EN_DIS
1531 **/
1532 UINT8 PchPmWolOvrWkSts;
1533
1534 /** Offset 0x065A - PCH Pm Reset Power Cycle Duration
1535 Could be customized in the unit of second. Please refer to EDS for all support settings.
1536 0 is default, 1 is 1 second, 2 is 2 seconds, ...
1537 **/
1538 UINT8 PchPmPwrCycDur;
1539
1540 /** Offset 0x065B
1541 **/
1542 UINT8 UnusedUpdSpace18;
1543
1544 /** Offset 0x065C - PCH Port 61h Config Enable/Disable
1545 Used for the emulation feature for Port61h read. The port is trapped and the SMI
1546 handler will toggle bit4 according to the handler's internal state.
1547 $EN_DIS
1548 **/
1549 UINT8 PchPort61hEnable;
1550
1551 /** Offset 0x065D - PCH Sata Pwr Opt Enable
1552 SATA Power Optimizer on PCH side.
1553 $EN_DIS
1554 **/
1555 UINT8 SataPwrOptEnable;
1556
1557 /** Offset 0x065E - PCH Sata eSATA Speed Limit
1558 When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
1559 $EN_DIS
1560 **/
1561 UINT8 EsataSpeedLimit;
1562
1563 /** Offset 0x065F - PCH Sata Speed Limit
1564 Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
1565 **/
1566 UINT8 SataSpeedLimit;
1567
1568 /** Offset 0x0660 - Enable SATA Port HotPlug
1569 Enable SATA Port HotPlug.
1570 **/
1571 UINT8 SataPortsHotPlug[8];
1572
1573 /** Offset 0x0668 - Enable SATA Port Interlock Sw
1574 Enable SATA Port Interlock Sw.
1575 **/
1576 UINT8 SataPortsInterlockSw[8];
1577
1578 /** Offset 0x0670 - Enable SATA Port External
1579 Enable SATA Port External.
1580 **/
1581 UINT8 SataPortsExternal[8];
1582
1583 /** Offset 0x0678 - Enable SATA Port SpinUp
1584 Enable the COMRESET initialization Sequence to the device.
1585 **/
1586 UINT8 SataPortsSpinUp[8];
1587
1588 /** Offset 0x0680 - Enable SATA Port Solid State Drive
1589 0: HDD; 1: SSD.
1590 **/
1591 UINT8 SataPortsSolidStateDrive[8];
1592
1593 /** Offset 0x0688 - Enable SATA Port Enable Dito Config
1594 Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
1595 **/
1596 UINT8 SataPortsEnableDitoConfig[8];
1597
1598 /** Offset 0x0690 - Enable SATA Port DmVal
1599 DITO multiplier. Default is 15.
1600 **/
1601 UINT8 SataPortsDmVal[8];
1602
1603 /** Offset 0x0698 - Enable SATA Port DmVal
1604 DEVSLP Idle Timeout (DITO), Default is 625.
1605 **/
1606 UINT16 SataPortsDitoVal[8];
1607
1608 /** Offset 0x06A8 - Enable SATA Port ZpOdd
1609 Support zero power ODD.
1610 **/
1611 UINT8 SataPortsZpOdd[8];
1612
1613 /** Offset 0x06B0 - PCH Sata Rst Raid Alternate Id
1614 Enable RAID Alternate ID.
1615 0:Client, 1:Alternate, 2:Server
1616 **/
1617 UINT8 SataRstRaidAlternateId;
1618
1619 /** Offset 0x06B1 - PCH Sata Rst Raid0
1620 RAID0.
1621 $EN_DIS
1622 **/
1623 UINT8 SataRstRaid0;
1624
1625 /** Offset 0x06B2 - PCH Sata Rst Raid1
1626 RAID1.
1627 $EN_DIS
1628 **/
1629 UINT8 SataRstRaid1;
1630
1631 /** Offset 0x06B3 - PCH Sata Rst Raid10
1632 RAID10.
1633 $EN_DIS
1634 **/
1635 UINT8 SataRstRaid10;
1636
1637 /** Offset 0x06B4 - PCH Sata Rst Raid5
1638 RAID5.
1639 $EN_DIS
1640 **/
1641 UINT8 SataRstRaid5;
1642
1643 /** Offset 0x06B5 - PCH Sata Rst Irrt
1644 Intel Rapid Recovery Technology.
1645 $EN_DIS
1646 **/
1647 UINT8 SataRstIrrt;
1648
1649 /** Offset 0x06B6 - PCH Sata Rst Orom Ui Banner
1650 OROM UI and BANNER.
1651 $EN_DIS
1652 **/
1653 UINT8 SataRstOromUiBanner;
1654
1655 /** Offset 0x06B7 - PCH Sata Rst Orom Ui Delay
1656 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
1657 **/
1658 UINT8 SataRstOromUiDelay;
1659
1660 /** Offset 0x06B8 - PCH Sata Rst Hdd Unlock
1661 Indicates that the HDD password unlock in the OS is enabled.
1662 $EN_DIS
1663 **/
1664 UINT8 SataRstHddUnlock;
1665
1666 /** Offset 0x06B9 - PCH Sata Rst Led Locate
1667 Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
1668 enabled on the OS.
1669 $EN_DIS
1670 **/
1671 UINT8 SataRstLedLocate;
1672
1673 /** Offset 0x06BA - PCH Sata Rst Irrt Only
1674 Allow only IRRT drives to span internal and external ports.
1675 $EN_DIS
1676 **/
1677 UINT8 SataRstIrrtOnly;
1678
1679 /** Offset 0x06BB - PCH Sata Rst Smart Storage
1680 RST Smart Storage caching Bit.
1681 $EN_DIS
1682 **/
1683 UINT8 SataRstSmartStorage;
1684
1685 /** Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable
1686 Enable Intel RST for PCIe Storage remapping.
1687 **/
1688 UINT8 SataRstPcieEnable[3];
1689
1690 /** Offset 0x06BF - PCH Sata Rst Pcie Storage Port
1691 Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
1692 **/
1693 UINT8 SataRstPcieStoragePort[3];
1694
1695 /** Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay
1696 PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
1697 **/
1698 UINT8 SataRstPcieDeviceResetDelay[3];
1699
1700 /** Offset 0x06C5 - Enable eMMC HS400 Training
1701 Determine if HS400 Training is required.
1702 $EN_DIS
1703 **/
1704 UINT8 PchScsEmmcHs400TuningRequired;
1705
1706 /** Offset 0x06C6 - Set HS400 Tuning Data Valid
1707 Set if HS400 Tuning Data Valid.
1708 $EN_DIS
1709 **/
1710 UINT8 PchScsEmmcHs400DllDataValid;
1711
1712 /** Offset 0x06C7 - Rx Strobe Delay Control
1713 Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
1714 **/
1715 UINT8 PchScsEmmcHs400RxStrobeDll1;
1716
1717 /** Offset 0x06C8 - Tx Data Delay Control
1718 Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
1719 **/
1720 UINT8 PchScsEmmcHs400TxDataDll;
1721
1722 /** Offset 0x06C9 - I/O Driver Strength
1723 I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm.
1724 **/
1725 UINT8 PchScsEmmcHs400DriverStrength;
1726
1727 /** Offset 0x06CA - Enable Pch Serial IO GPIO
1728 Determines if enable Serial IO GPIO.
1729 $EN_DIS
1730 **/
1731 UINT8 SerialIoGpio;
1732
1733 /** Offset 0x06CB - IO voltage for I2C controllers
1734 Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V.
1735 **/
1736 UINT8 SerialIoI2cVoltage[6];
1737
1738 /** Offset 0x06D1 - SPI ChipSelect signal polarity
1739 Selects SPI ChipSelect signal polarity.
1740 **/
1741 UINT8 SerialIoSpiCsPolarity[2];
1742
1743 /** Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines
1744 Enables UART hardware flow control, CTS and RTS linesh.
1745 **/
1746 UINT8 SerialIoUartHwFlowCtrl[3];
1747
1748 /** Offset 0x06D6 - UART Number For Debug Purpose
1749 UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2.
1750 **/
1751 UINT8 SerialIoDebugUartNumber;
1752
1753 /** Offset 0x06D7 - Enable Debug UART Controller
1754 Enable debug UART controller after post.
1755 **/
1756 UINT8 SerialIoEnableDebugUartAfterPost;
1757
1758 /** Offset 0x06D8 - Enable Serial IRQ
1759 Determines if enable Serial IRQ.
1760 $EN_DIS
1761 **/
1762 UINT8 PchSirqEnable;
1763
1764 /** Offset 0x06D9 - Serial IRQ Mode Select
1765 Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
1766 $EN_DIS
1767 **/
1768 UINT8 PchSirqMode;
1769
1770 /** Offset 0x06DA - Start Frame Pulse Width
1771 Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
1772 **/
1773 UINT8 PchStartFramePulse;
1774
1775 /** Offset 0x06DB - Enable Thermal Device
1776 Enable Thermal Device.
1777 $EN_DIS
1778 **/
1779 UINT8 PchThermalDeviceEnable;
1780
1781 /** Offset 0x06DC - Thermal Throttling Custimized T0Level Value
1782 Custimized T0Level value.
1783 **/
1784 UINT16 PchT0Level;
1785
1786 /** Offset 0x06DE - Thermal Throttling Custimized T1Level Value
1787 Custimized T1Level value.
1788 **/
1789 UINT16 PchT1Level;
1790
1791 /** Offset 0x06E0 - Thermal Throttling Custimized T2Level Value
1792 Custimized T2Level value.
1793 **/
1794 UINT16 PchT2Level;
1795
1796 /** Offset 0x06E2 - Thermal Device SMI Enable
1797 This locks down SMI Enable on Alert Thermal Sensor Trip.
1798 $EN_DIS
1799 **/
1800 UINT8 PchTsmicLock;
1801
1802 /** Offset 0x06E3 - Enable The Thermal Throttle
1803 Enable the thermal throttle function.
1804 $EN_DIS
1805 **/
1806 UINT8 PchTTEnable;
1807
1808 /** Offset 0x06E4 - PMSync State 13
1809 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
1810 at least T2 state.
1811 $EN_DIS
1812 **/
1813 UINT8 PchTTState13Enable;
1814
1815 /** Offset 0x06E5 - Thermal Throttle Lock
1816 Thermal Throttle Lock.
1817 $EN_DIS
1818 **/
1819 UINT8 PchTTLock;
1820
1821 /** Offset 0x06E6 - Thermal Throttling Suggested Setting
1822 Thermal Throttling Suggested Setting.
1823 $EN_DIS
1824 **/
1825 UINT8 TTSuggestedSetting;
1826
1827 /** Offset 0x06E7 - Enable PCH Cross Throttling
1828 Enable/Disable PCH Cross Throttling
1829 $EN_DIS
1830 **/
1831 UINT8 TTCrossThrottling;
1832
1833 /** Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable
1834 DMI Thermal Sensor Autonomous Width Enable.
1835 $EN_DIS
1836 **/
1837 UINT8 PchDmiTsawEn;
1838
1839 /** Offset 0x06E9 - DMI Thermal Sensor Suggested Setting
1840 DMT thermal sensor suggested representative values.
1841 $EN_DIS
1842 **/
1843 UINT8 DmiSuggestedSetting;
1844
1845 /** Offset 0x06EA - Thermal Sensor 0 Target Width
1846 Thermal Sensor 0 Target Width.
1847 **/
1848 UINT8 DmiTS0TW;
1849
1850 /** Offset 0x06EB - Thermal Sensor 1 Target Width
1851 Thermal Sensor 1 Target Width.
1852 **/
1853 UINT8 DmiTS1TW;
1854
1855 /** Offset 0x06EC - Thermal Sensor 2 Target Width
1856 Thermal Sensor 2 Target Width.
1857 **/
1858 UINT8 DmiTS2TW;
1859
1860 /** Offset 0x06ED - Thermal Sensor 3 Target Width
1861 Thermal Sensor 3 Target Width.
1862 **/
1863 UINT8 DmiTS3TW;
1864
1865 /** Offset 0x06EE - Port 0 T1 Multipler
1866 Port 0 T1 Multipler.
1867 **/
1868 UINT8 SataP0T1M;
1869
1870 /** Offset 0x06EF - Port 0 T2 Multipler
1871 Port 0 T2 Multipler.
1872 **/
1873 UINT8 SataP0T2M;
1874
1875 /** Offset 0x06F0 - Port 0 T3 Multipler
1876 Port 0 T3 Multipler.
1877 **/
1878 UINT8 SataP0T3M;
1879
1880 /** Offset 0x06F1 - Port 0 Tdispatch
1881 Port 0 Tdispatch.
1882 **/
1883 UINT8 SataP0TDisp;
1884
1885 /** Offset 0x06F2 - Port 1 T1 Multipler
1886 Port 1 T1 Multipler.
1887 **/
1888 UINT8 SataP1T1M;
1889
1890 /** Offset 0x06F3 - Port 1 T2 Multipler
1891 Port 1 T2 Multipler.
1892 **/
1893 UINT8 SataP1T2M;
1894
1895 /** Offset 0x06F4 - Port 1 T3 Multipler
1896 Port 1 T3 Multipler.
1897 **/
1898 UINT8 SataP1T3M;
1899
1900 /** Offset 0x06F5 - Port 1 Tdispatch
1901 Port 1 Tdispatch.
1902 **/
1903 UINT8 SataP1TDisp;
1904
1905 /** Offset 0x06F6 - Port 0 Tinactive
1906 Port 0 Tinactive.
1907 **/
1908 UINT8 SataP0Tinact;
1909
1910 /** Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch
1911 Port 0 Alternate Fast Init Tdispatch.
1912 $EN_DIS
1913 **/
1914 UINT8 SataP0TDispFinit;
1915
1916 /** Offset 0x06F8 - Port 1 Tinactive
1917 Port 1 Tinactive.
1918 **/
1919 UINT8 SataP1Tinact;
1920
1921 /** Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch
1922 Port 1 Alternate Fast Init Tdispatch.
1923 $EN_DIS
1924 **/
1925 UINT8 SataP1TDispFinit;
1926
1927 /** Offset 0x06FA - Sata Thermal Throttling Suggested Setting
1928 Sata Thermal Throttling Suggested Setting.
1929 $EN_DIS
1930 **/
1931 UINT8 SataThermalSuggestedSetting;
1932
1933 /** Offset 0x06FB - Enable Memory Thermal Throttling
1934 Enable Memory Thermal Throttling.
1935 $EN_DIS
1936 **/
1937 UINT8 PchMemoryThrottlingEnable;
1938
1939 /** Offset 0x06FC - Memory Thermal Throttling
1940 Enable Memory Thermal Throttling.
1941 **/
1942 UINT8 PchMemoryPmsyncEnable[2];
1943
1944 /** Offset 0x06FE - Enable Memory Thermal Throttling
1945 Enable Memory Thermal Throttling.
1946 **/
1947 UINT8 PchMemoryC0TransmitEnable[2];
1948
1949 /** Offset 0x0700 - Enable Memory Thermal Throttling
1950 Enable Memory Thermal Throttling.
1951 **/
1952 UINT8 PchMemoryPinSelection[2];
1953
1954 /** Offset 0x0702 - Thermal Device Temperature
1955 Decides the temperature.
1956 **/
1957 UINT16 PchTemperatureHotLevel;
1958
1959 /** Offset 0x0704 - Disable XHCI Compliance Mode
1960 This policy will disable XHCI compliance mode on all ports. Complicance Mode should
1961 be default enabled.
1962 $EN_DIS
1963 **/
1964 UINT8 PchDisableComplianceMode;
1965
1966 /** Offset 0x0705 - USB2 Port Over Current Pin
1967 Describe the specific over current pin number of USB 2.0 Port N.
1968 **/
1969 UINT8 Usb2OverCurrentPin[16];
1970
1971 /** Offset 0x0715 - USB3 Port Over Current Pin
1972 Describe the specific over current pin number of USB 3.0 Port N.
1973 **/
1974 UINT8 Usb3OverCurrentPin[10];
1975
1976 /** Offset 0x071F - Enable 8254 Static Clock Gating in early POST time
1977 Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might
1978 fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy
1979 OS boot before enabling this.
1980 $EN_DIS
1981 **/
1982 UINT8 Early8254ClockGatingEnable;
1983
1984 /** Offset 0x0720 - PCH Sata Rst Optane Memory
1985 Optane Memory
1986 $EN_DIS
1987 **/
1988 UINT8 SataRstOptaneMemory;
1989
1990 /** Offset 0x0721 - PCH SATA RST CPU attached storage
1991 RST CPU attached storage
1992 $EN_DIS
1993 **/
1994 UINT8 SataRstCpuAttachedStorage;
1995
1996 /** Offset 0x0722
1997 **/
1998 UINT8 UnusedUpdSpace19[2];
1999
2000 /** Offset 0x0724 - Pch PCIE device override table pointer
2001 The PCIe device table is being used to override PCIe device ASPM settings. This
2002 is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
2003 refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
2004 must be 0.
2005 **/
2006 UINT32 PchPcieDeviceOverrideTablePtr;
2007
2008 /** Offset 0x0728 - Enable TCO timer.
2009 When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
2010 huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
2011 emulation must be enabled, and WDAT table must not be exposed to the OS.
2012 $EN_DIS
2013 **/
2014 UINT8 EnableTcoTimer;
2015
2016 /** Offset 0x0729 - EcCmdProvisionEav
2017 Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
2018 **/
2019 UINT8 EcCmdProvisionEav;
2020
2021 /** Offset 0x072A - EcCmdLock
2022 EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
2023 **/
2024 UINT8 EcCmdLock;
2025
2026 /** Offset 0x072B
2027 **/
2028 UINT8 UnusedUpdSpace20[5];
2029
2030 /** Offset 0x0730 - SendEcCmd
2031 SendEcCmd function pointer. \n
2032 @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
2033 EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
2034 **/
2035 UINT64 SendEcCmd;
2036
2037 /** Offset 0x0738 - BgpdtHash[4]
2038 BgpdtHash values
2039 **/
2040 UINT64 BgpdtHash[4];
2041
2042 /** Offset 0x0758 - BiosGuardModulePtr
2043 BiosGuardModulePtr default values
2044 **/
2045 UINT64 BiosGuardModulePtr;
2046
2047 /** Offset 0x0760 - BiosGuardAttr
2048 BiosGuardAttr default values
2049 **/
2050 UINT32 BiosGuardAttr;
2051
2052 /** Offset 0x0764 - SgxSinitNvsData
2053 SgxSinitNvsData default values
2054 **/
2055 UINT8 SgxSinitNvsData;
2056
2057 /** Offset 0x0765
2058 **/
2059 UINT8 UnusedUpdSpace21[3];
2060
2061 /** Offset 0x0768 - SgxEpoch0
2062 SgxEpoch0 default values
2063 **/
2064 UINT64 SgxEpoch0;
2065
2066 /** Offset 0x0770 - SgxEpoch1
2067 SgxEpoch1 default values
2068 **/
2069 UINT64 SgxEpoch1;
2070
2071 /** Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear
2072 Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear
2073 $EN_DIS
2074 **/
2075 UINT8 MeUnconfigOnRtcClear;
2076
2077 /** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid
2078 The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear.
2079 $EN_DIS
2080 **/
2081 UINT8 MeUnconfigIsValid;
2082
2083 /** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.
2084 Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
2085 command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
2086 **/
2087 UINT8 IslVrCmd;
2088
2089 /** Offset 0x077B
2090 **/
2091 UINT8 ReservedFspsUpd[5];
2092 } FSP_S_CONFIG;
2093
2094 /** Fsp S Test Configuration
2095 **/
2096 typedef struct {
2097
2098 /** Offset 0x0780
2099 **/
2100 UINT32 Signature;
2101
2102 /** Offset 0x0784 - Enable/Disable Device 7
2103 Enable: Device 7 enabled, Disable (Default): Device 7 disabled
2104 $EN_DIS
2105 **/
2106 UINT8 ChapDeviceEnable;
2107
2108 /** Offset 0x0785 - Skip PAM register lock
2109 Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
2110 PAM registers will be locked by RC
2111 $EN_DIS
2112 **/
2113 UINT8 SkipPamLock;
2114
2115 /** Offset 0x0786 - EDRAM Test Mode
2116 Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
2117 PAM registers will be locked by RC
2118 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
2119 **/
2120 UINT8 EdramTestMode;
2121
2122 /** Offset 0x0787 - DMI Extended Sync Control
2123 Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
2124 Sync Control
2125 $EN_DIS
2126 **/
2127 UINT8 DmiExtSync;
2128
2129 /** Offset 0x0788 - DMI IOT Control
2130 Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
2131 $EN_DIS
2132 **/
2133 UINT8 DmiIot;
2134
2135 /** Offset 0x0789 - PEG Max Payload size per root port
2136 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
2137 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
2138 **/
2139 UINT8 PegMaxPayload[3];
2140
2141 /** Offset 0x078C - Enable/Disable IGFX RenderStandby
2142 Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
2143 $EN_DIS
2144 **/
2145 UINT8 RenderStandby;
2146
2147 /** Offset 0x078D - Enable/Disable IGFX PmSupport
2148 Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
2149 $EN_DIS
2150 **/
2151 UINT8 PmSupport;
2152
2153 /** Offset 0x078E - Enable/Disable CdynmaxClamp
2154 Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
2155 $EN_DIS
2156 **/
2157 UINT8 CdynmaxClampEnable;
2158
2159 /** Offset 0x078F - Disable VT-d
2160 0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled)
2161 $EN_DIS
2162 **/
2163 UINT8 VtdDisable;
2164
2165 /** Offset 0x0790 - GT Frequency Limit
2166 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
2167 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
2168 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
2169 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
2170 0x18: 1200 Mhz
2171 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
2172 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
2173 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
2174 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
2175 0x18: 1200 Mhz
2176 **/
2177 UINT8 GtFreqMax;
2178
2179 /** Offset 0x0791 - SaPostMemTestRsvd
2180 Reserved for SA Post-Mem Test
2181 $EN_DIS
2182 **/
2183 UINT8 SaPostMemTestRsvd[11];
2184
2185 /** Offset 0x079C - 1-Core Ratio Limit
2186 1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 1-Core
2187 Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
2188 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
2189 8-Core Ratio Limit. Range is 0 to 255
2190 **/
2191 UINT8 OneCoreRatioLimit;
2192
2193 /** Offset 0x079D - 2-Core Ratio Limit
2194 2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 2-Core
2195 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2196 **/
2197 UINT8 TwoCoreRatioLimit;
2198
2199 /** Offset 0x079E - 3-Core Ratio Limit
2200 3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 3-Core
2201 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2202 **/
2203 UINT8 ThreeCoreRatioLimit;
2204
2205 /** Offset 0x079F - 4-Core Ratio Limit
2206 4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 4-Core
2207 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2208 **/
2209 UINT8 FourCoreRatioLimit;
2210
2211 /** Offset 0x07A0
2212 **/
2213 UINT8 UnusedUpdSpace22;
2214
2215 /** Offset 0x07A1 - Enable or Disable HWP
2216 Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2217 2-3:Reserved
2218 $EN_DIS
2219 **/
2220 UINT8 Hwp;
2221
2222 /** Offset 0x07A2 - Hardware Duty Cycle Control
2223 Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
2224 $EN_DIS
2225 **/
2226 UINT8 HdcControl;
2227
2228 /** Offset 0x07A3 - Package Long duration turbo mode time
2229 Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
2230 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
2231 **/
2232 UINT8 PowerLimit1Time;
2233
2234 /** Offset 0x07A4 - Short Duration Turbo Mode
2235 Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
2236 $EN_DIS
2237 **/
2238 UINT8 PowerLimit2;
2239
2240 /** Offset 0x07A5 - Turbo settings Lock
2241 Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
2242 $EN_DIS
2243 **/
2244 UINT8 TurboPowerLimitLock;
2245
2246 /** Offset 0x07A6 - Package PL3 time window
2247 Package PL3 time window range for this policy in milliseconds. Valid values are
2248 0, 3 to 8, 10, 12, 14, 16, 20 , 24, 28, 32, 40, 48, 55, 56, 64
2249 **/
2250 UINT8 PowerLimit3Time;
2251
2252 /** Offset 0x07A7 - Package PL3 Duty Cycle
2253 Package PL3 Duty Cycle; Valid Range is 0 to 100
2254 **/
2255 UINT8 PowerLimit3DutyCycle;
2256
2257 /** Offset 0x07A8 - Package PL3 Lock
2258 Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
2259 $EN_DIS
2260 **/
2261 UINT8 PowerLimit3Lock;
2262
2263 /** Offset 0x07A9 - Package PL4 Lock
2264 Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
2265 $EN_DIS
2266 **/
2267 UINT8 PowerLimit4Lock;
2268
2269 /** Offset 0x07AA - TCC Activation Offset
2270 TCC Activation Offset. Offset from factory set TCC activation temperature at which
2271 the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
2272 Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
2273 <b>10</b>, For all other SKUs the recommended default are <b>0</b>
2274 **/
2275 UINT8 TccActivationOffset;
2276
2277 /** Offset 0x07AB - Tcc Offset Clamp Enable/Disable
2278 Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
2279 below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
2280 For all other SKUs the recommended default are <b>0: Disabled</b>.
2281 $EN_DIS
2282 **/
2283 UINT8 TccOffsetClamp;
2284
2285 /** Offset 0x07AC - Tcc Offset Lock
2286 Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
2287 target; <b>0: Disabled</b>; 1: Enabled.
2288 $EN_DIS
2289 **/
2290 UINT8 TccOffsetLock;
2291
2292 /** Offset 0x07AD - Custom Ratio State Entries
2293 The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
2294 ratio table.Sets the number of custom P-states. At least 2 states must be present
2295 **/
2296 UINT8 NumberOfEntries;
2297
2298 /** Offset 0x07AE - Custom Short term Power Limit time window
2299 Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
2300 **/
2301 UINT8 Custom1PowerLimit1Time;
2302
2303 /** Offset 0x07AF - Custom Turbo Activation Ratio
2304 Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
2305 **/
2306 UINT8 Custom1TurboActivationRatio;
2307
2308 /** Offset 0x07B0 - Custom Config Tdp Control
2309 Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2310 **/
2311 UINT8 Custom1ConfigTdpControl;
2312
2313 /** Offset 0x07B1 - Custom Short term Power Limit time window
2314 Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
2315 **/
2316 UINT8 Custom2PowerLimit1Time;
2317
2318 /** Offset 0x07B2 - Custom Turbo Activation Ratio
2319 Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
2320 **/
2321 UINT8 Custom2TurboActivationRatio;
2322
2323 /** Offset 0x07B3 - Custom Config Tdp Control
2324 Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2325 **/
2326 UINT8 Custom2ConfigTdpControl;
2327
2328 /** Offset 0x07B4 - Custom Short term Power Limit time window
2329 Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
2330 **/
2331 UINT8 Custom3PowerLimit1Time;
2332
2333 /** Offset 0x07B5 - Custom Turbo Activation Ratio
2334 Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
2335 **/
2336 UINT8 Custom3TurboActivationRatio;
2337
2338 /** Offset 0x07B6 - Custom Config Tdp Control
2339 Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2340 **/
2341 UINT8 Custom3ConfigTdpControl;
2342
2343 /** Offset 0x07B7 - ConfigTdp mode settings Lock
2344 Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
2345 $EN_DIS
2346 **/
2347 UINT8 ConfigTdpLock;
2348
2349 /** Offset 0x07B8 - Load Configurable TDP SSDT
2350 Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
2351 $EN_DIS
2352 **/
2353 UINT8 ConfigTdpBios;
2354
2355 /** Offset 0x07B9 - PL1 Enable value
2356 PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
2357 $EN_DIS
2358 **/
2359 UINT8 PsysPowerLimit1;
2360
2361 /** Offset 0x07BA - PL1 timewindow
2362 PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
2363 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
2364 **/
2365 UINT8 PsysPowerLimit1Time;
2366
2367 /** Offset 0x07BB - PL2 Enable Value
2368 PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
2369 1: Enable.
2370 $EN_DIS
2371 **/
2372 UINT8 PsysPowerLimit2;
2373
2374 /** Offset 0x07BC
2375 **/
2376 UINT8 UnusedUpdSpace23[2];
2377
2378 /** Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher
2379 Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
2380 $EN_DIS
2381 **/
2382 UINT8 MlcStreamerPrefetcher;
2383
2384 /** Offset 0x07BF - Enable or Disable MLC Spatial Prefetcher
2385 Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
2386 $EN_DIS
2387 **/
2388 UINT8 MlcSpatialPrefetcher;
2389
2390 /** Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions
2391 Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
2392 $EN_DIS
2393 **/
2394 UINT8 MonitorMwaitEnable;
2395
2396 /** Offset 0x07C1 - Enable or Disable initialization of machine check registers
2397 Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
2398 $EN_DIS
2399 **/
2400 UINT8 MachineCheckEnable;
2401
2402 /** Offset 0x07C2 - Enable or Disable processor debug features
2403 Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
2404 $EN_DIS
2405 **/
2406 UINT8 DebugInterfaceEnable;
2407
2408 /** Offset 0x07C3 - Lock or Unlock debug interface features
2409 Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
2410 $EN_DIS
2411 **/
2412 UINT8 DebugInterfaceLockEnable;
2413
2414 /** Offset 0x07C4 - AP Idle Manner of waiting for SIPI
2415 AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
2416 1:HALT loop, 2:MWAIT loop, 3:RUN loop
2417 **/
2418 UINT8 ApIdleManner;
2419
2420 /** Offset 0x07C5 - Settings for AP Handoff to OS
2421 Settings for AP Handoff to OS; 1: HALT loop; <b>2: MWAIT loop</b>.
2422 1:HALT loop, 2:MWAIT loop
2423 **/
2424 UINT8 ApHandoffManner;
2425
2426 /** Offset 0x07C6
2427 **/
2428 UINT8 UnusedUpdSpace24[2];
2429
2430 /** Offset 0x07C8 - Control on Processor Trace output scheme
2431 Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
2432 0:Single Range Output, 1:ToPA Output
2433 **/
2434 UINT8 ProcTraceOutputScheme;
2435
2436 /** Offset 0x07C9 - Enable or Disable Processor Trace feature
2437 Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
2438 $EN_DIS
2439 **/
2440 UINT8 ProcTraceEnable;
2441
2442 /** Offset 0x07CA - Memory region allocation for Processor Trace
2443 Memory region allocation for Processor Trace, Total Memory required is up to requested
2444 value * 2 (for memory alignment) * 8 active threads, to enable Processor Trace,
2445 PcdFspReservedMemoryLength must be increased by the total memory required, and
2446 PlatformMemorySize policy must also be increased by the total memory required over
2447 32MB, Valid Values are 0 - 4KB , 0x1 - 8KB , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB
2448 , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB ,
2449 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE - 64MB , 0xF - 128MB , 0xFF: Disable
2450 **/
2451 UINT8 ProcTraceMemSize;
2452
2453 /** Offset 0x07CB
2454 **/
2455 UINT8 UnusedUpdSpace25;
2456
2457 /** Offset 0x07CC - Enable or Disable Voltage Optimization feature
2458 Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
2459 $EN_DIS
2460 **/
2461 UINT8 VoltageOptimization;
2462
2463 /** Offset 0x07CD - Enable or Disable Intel SpeedStep Technology
2464 Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
2465 $EN_DIS
2466 **/
2467 UINT8 Eist;
2468
2469 /** Offset 0x07CE - Enable or Disable Energy Efficient P-state
2470 Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
2471 <b>1: Enable</b>
2472 $EN_DIS
2473 **/
2474 UINT8 EnergyEfficientPState;
2475
2476 /** Offset 0x07CF - Enable or Disable Energy Efficient Turbo
2477 Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
2478 <b>1: Enable</b>
2479 $EN_DIS
2480 **/
2481 UINT8 EnergyEfficientTurbo;
2482
2483 /** Offset 0x07D0 - Enable or Disable T states
2484 Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
2485 $EN_DIS
2486 **/
2487 UINT8 TStates;
2488
2489 /** Offset 0x07D1 - Enable or Disable Bi-Directional PROCHOT#
2490 Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
2491 $EN_DIS
2492 **/
2493 UINT8 BiProcHot;
2494
2495 /** Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally
2496 Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
2497 $EN_DIS
2498 **/
2499 UINT8 DisableProcHotOut;
2500
2501 /** Offset 0x07D3 - Enable or Disable PROCHOT# Response
2502 Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
2503 $EN_DIS
2504 **/
2505 UINT8 ProcHotResponse;
2506
2507 /** Offset 0x07D4 - Enable or Disable VR Thermal Alert
2508 Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
2509 $EN_DIS
2510 **/
2511 UINT8 DisableVrThermalAlert;
2512
2513 /** Offset 0x07D5 - Enable or Disable Thermal Reporting
2514 Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
2515 $EN_DIS
2516 **/
2517 UINT8 AutoThermalReporting;
2518
2519 /** Offset 0x07D6 - Enable or Disable Thermal Monitor
2520 Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
2521 $EN_DIS
2522 **/
2523 UINT8 ThermalMonitor;
2524
2525 /** Offset 0x07D7 - Enable or Disable CPU power states (C-states)
2526 Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
2527 $EN_DIS
2528 **/
2529 UINT8 Cx;
2530
2531 /** Offset 0x07D8 - Configure C-State Configuration Lock
2532 Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
2533 $EN_DIS
2534 **/
2535 UINT8 PmgCstCfgCtrlLock;
2536
2537 /** Offset 0x07D9 - Enable or Disable Enhanced C-states
2538 Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
2539 $EN_DIS
2540 **/
2541 UINT8 C1e;
2542
2543 /** Offset 0x07DA - Enable or Disable Package C-State Demotion
2544 Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b>
2545 (Auto: Enabled for Skylake; Disabled for Kabylake)
2546 0:Disable, 1:Enable, 2:Auto
2547 **/
2548 UINT8 PkgCStateDemotion;
2549
2550 /** Offset 0x07DB - Enable or Disable Package C-State UnDemotion
2551 Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b>
2552 (Auto: Enabled for Skylake; Disabled for Kabylake)
2553 0:Disable, 1:Enable, 2:Auto
2554 **/
2555 UINT8 PkgCStateUnDemotion;
2556
2557 /** Offset 0x07DC - Enable or Disable CState-Pre wake
2558 Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
2559 $EN_DIS
2560 **/
2561 UINT8 CStatePreWake;
2562
2563 /** Offset 0x07DD - Enable or Disable TimedMwait Support.
2564 Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
2565 $EN_DIS
2566 **/
2567 UINT8 TimedMwait;
2568
2569 /** Offset 0x07DE - Enable or Disable IO to MWAIT redirection
2570 Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
2571 $EN_DIS
2572 **/
2573 UINT8 CstCfgCtrIoMwaitRedirection;
2574
2575 /** Offset 0x07DF - Set the Max Pkg Cstate
2576 Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
2577 C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
2578 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
2579 **/
2580 UINT8 PkgCStateLimit;
2581
2582 /** Offset 0x07E0 - TimeUnit for C-State Latency Control0
2583 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2584 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2585 **/
2586 UINT8 CstateLatencyControl0TimeUnit;
2587
2588 /** Offset 0x07E1 - TimeUnit for C-State Latency Control1
2589 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2590 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2591 **/
2592 UINT8 CstateLatencyControl1TimeUnit;
2593
2594 /** Offset 0x07E2 - TimeUnit for C-State Latency Control2
2595 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2596 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2597 **/
2598 UINT8 CstateLatencyControl2TimeUnit;
2599
2600 /** Offset 0x07E3 - TimeUnit for C-State Latency Control3
2601 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2602 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2603 **/
2604 UINT8 CstateLatencyControl3TimeUnit;
2605
2606 /** Offset 0x07E4 - TimeUnit for C-State Latency Control4
2607 TimeUnit for C-State Latency Control4;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2608 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2609 **/
2610 UINT8 CstateLatencyControl4TimeUnit;
2611
2612 /** Offset 0x07E5 - TimeUnit for C-State Latency Control5
2613 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2614 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2615 **/
2616 UINT8 CstateLatencyControl5TimeUnit;
2617
2618 /** Offset 0x07E6 - Interrupt Redirection Mode Select
2619 Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
2620 PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
2621 **/
2622 UINT8 PpmIrmSetting;
2623
2624 /** Offset 0x07E7 - Lock prochot configuration
2625 Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
2626 $EN_DIS
2627 **/
2628 UINT8 ProcHotLock;
2629
2630 /** Offset 0x07E8 - Configuration for boot TDP selection
2631 Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
2632 Up; 0xFF: Deactivate
2633 0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate
2634 **/
2635 UINT8 ConfigTdpLevel;
2636
2637 /** Offset 0x07E9 - Race To Halt
2638 Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
2639 in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
2640 through MSR 1FC bit 20)Disable; <b>1: Enable</b>
2641 $EN_DIS
2642 **/
2643 UINT8 RaceToHalt;
2644
2645 /** Offset 0x07EA - Max P-State Ratio
2646 Max P-State Ratio , Valid Range 0 to 0x7F
2647 **/
2648 UINT16 MaxRatio;
2649
2650 /** Offset 0x07EC - Maximum P-state ratio to use in the custom P-state table
2651 Maximum P-state ratio to use in the custom P-state table. NumOfCustomPStates has
2652 valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates)
2653 , StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F
2654 **/
2655 UINT16 StateRatio[40];
2656
2657 /** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0
2658 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF,
2659 Default is 0x4E, Server Platform is 0x4B
2660 **/
2661 UINT16 CstateLatencyControl0Irtl;
2662
2663 /** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1
2664 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF,
2665 Default is 0x76, Server Platform is 0x6B
2666 **/
2667 UINT16 CstateLatencyControl1Irtl;
2668
2669 /** Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol2
2670 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
2671 **/
2672 UINT16 CstateLatencyControl2Irtl;
2673
2674 /** Offset 0x0842 - Interrupt Response Time Limit of C-State LatencyContol3
2675 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
2676 **/
2677 UINT16 CstateLatencyControl3Irtl;
2678
2679 /** Offset 0x0844 - Interrupt Response Time Limit of C-State LatencyContol4
2680 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
2681 **/
2682 UINT16 CstateLatencyControl4Irtl;
2683
2684 /** Offset 0x0846 - Interrupt Response Time Limit of C-State LatencyContol5
2685 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
2686 **/
2687 UINT16 CstateLatencyControl5Irtl;
2688
2689 /** Offset 0x0848 - Package Long duration turbo mode power limit
2690 Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
2691 Valid Range 0 to 4095875 in Step size of 125
2692 **/
2693 UINT32 PowerLimit1;
2694
2695 /** Offset 0x084C - Package Short duration turbo mode power limit
2696 Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2697 Range 0 to 4095875 in Step size of 125
2698 **/
2699 UINT32 PowerLimit2Power;
2700
2701 /** Offset 0x0850 - Package PL3 power limit
2702 Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2703 Range 0 to 4095875 in Step size of 125
2704 **/
2705 UINT32 PowerLimit3;
2706
2707 /** Offset 0x0854 - Package PL4 power limit
2708 Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2709 Range 0 to 4095875 in Step size of 125
2710 **/
2711 UINT32 PowerLimit4;
2712
2713 /** Offset 0x0858 - Tcc Offset Time Window for RATL
2714 Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2715 Range 0 to 4095875 in Step size of 125
2716 **/
2717 UINT32 TccOffsetTimeWindowForRatl;
2718
2719 /** Offset 0x085C - Short term Power Limit value for custom cTDP level 1
2720 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2721 Range 0 to 4095875 in Step size of 125
2722 **/
2723 UINT32 Custom1PowerLimit1;
2724
2725 /** Offset 0x0860 - Long term Power Limit value for custom cTDP level 1
2726 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2727 Range 0 to 4095875 in Step size of 125
2728 **/
2729 UINT32 Custom1PowerLimit2;
2730
2731 /** Offset 0x0864 - Short term Power Limit value for custom cTDP level 2
2732 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2733 Range 0 to 4095875 in Step size of 125
2734 **/
2735 UINT32 Custom2PowerLimit1;
2736
2737 /** Offset 0x0868 - Long term Power Limit value for custom cTDP level 2
2738 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2739 Range 0 to 4095875 in Step size of 125
2740 **/
2741 UINT32 Custom2PowerLimit2;
2742
2743 /** Offset 0x086C - Short term Power Limit value for custom cTDP level 3
2744 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2745 Range 0 to 4095875 in Step size of 125
2746 **/
2747 UINT32 Custom3PowerLimit1;
2748
2749 /** Offset 0x0870 - Long term Power Limit value for custom cTDP level 3
2750 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2751 Range 0 to 4095875 in Step size of 125
2752 **/
2753 UINT32 Custom3PowerLimit2;
2754
2755 /** Offset 0x0874 - Platform PL1 power
2756 Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
2757 0 to 4095875 in Step size of 125
2758 **/
2759 UINT32 PsysPowerLimit1Power;
2760
2761 /** Offset 0x0878 - Platform PL2 power
2762 Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
2763 0 to 4095875 in Step size of 125
2764 **/
2765 UINT32 PsysPowerLimit2Power;
2766
2767 /** Offset 0x087C - Platform Power Pmax
2768 PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
2769 Range 0-1024 Watts. Value of 800 = 100W
2770 **/
2771 UINT16 PsysPmax;
2772
2773 /** Offset 0x087E - CpuS3ResumeDataSize
2774 Size of CPU S3 Resume Data
2775 **/
2776 UINT16 CpuS3ResumeDataSize;
2777
2778 /** Offset 0x0880 - CpuS3ResumeData
2779 Pointer to CPU S3 Resume Data
2780 **/
2781 UINT32 CpuS3ResumeData;
2782
2783 /** Offset 0x0884 - 5-Core Ratio Limit
2784 5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 5-Core
2785 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2786 **/
2787 UINT8 FiveCoreRatioLimit;
2788
2789 /** Offset 0x0885 - 6-Core Ratio Limit
2790 6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 6-Core
2791 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2792 **/
2793 UINT8 SixCoreRatioLimit;
2794
2795 /** Offset 0x0886 - 7-Core Ratio Limit
2796 7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 7-Core
2797 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2798 **/
2799 UINT8 SevenCoreRatioLimit;
2800
2801 /** Offset 0x0887 - 8-Core Ratio Limit
2802 8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 8-Core
2803 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2804 **/
2805 UINT8 EightCoreRatioLimit;
2806
2807 /** Offset 0x0888 - Set Three Strike Counter Disable
2808 False (default): Three Strike counter will be incremented and True: Prevents Three
2809 Strike counter from incrementing; <b>0: False</b>; 1: True.
2810 0: False, 1: True
2811 **/
2812 UINT8 ThreeStrikeCounterDisable;
2813
2814 /** Offset 0x0889 - ReservedCpuPostMemTest
2815 Reserved for CPU Post-Mem Test
2816 $EN_DIS
2817 **/
2818 UINT8 ReservedCpuPostMemTest[1];
2819
2820 /** Offset 0x088A - SgxSinitDataFromTpm
2821 SgxSinitDataFromTpm default values
2822 **/
2823 UINT8 SgxSinitDataFromTpm;
2824
2825 /** Offset 0x088B - End of Post message
2826 Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
2827 EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
2828 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
2829 **/
2830 UINT8 EndOfPostMessage;
2831
2832 /** Offset 0x088C - D0I3 Setting for HECI Disable
2833 Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
2834 HECI devices
2835 $EN_DIS
2836 **/
2837 UINT8 DisableD0I3SettingForHeci;
2838
2839 /** Offset 0x088D - Enable LOCKDOWN SMI
2840 Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
2841 $EN_DIS
2842 **/
2843 UINT8 PchLockDownGlobalSmi;
2844
2845 /** Offset 0x088E - HD Audio Reset Wait Timer
2846 The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
2847 **/
2848 UINT16 PchHdaResetWaitTimer;
2849
2850 /** Offset 0x0890 - Enable LOCKDOWN BIOS Interface
2851 Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
2852 $EN_DIS
2853 **/
2854 UINT8 PchLockDownBiosInterface;
2855
2856 /** Offset 0x0891 - RTC CMOS RAM LOCK
2857 Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
2858 and and lower 128-byte bank of RTC RAM.
2859 $EN_DIS
2860 **/
2861 UINT8 PchLockDownRtcLock;
2862
2863 /** Offset 0x0892 - PCH Sbi lock bit
2864 This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable.
2865 $EN_DIS
2866 **/
2867 UINT8 PchSbiUnlock;
2868
2869 /** Offset 0x0893 - PCH Psf lock bit
2870 The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable.
2871 $EN_DIS
2872 **/
2873 UINT8 PchSbAccessUnlock;
2874
2875 /** Offset 0x0894 - PCIE RP Ltr Max Snoop Latency
2876 Latency Tolerance Reporting, Max Snoop Latency.
2877 **/
2878 UINT16 PcieRpLtrMaxSnoopLatency[24];
2879
2880 /** Offset 0x08C4 - PCIE RP Ltr Max No Snoop Latency
2881 Latency Tolerance Reporting, Max Non-Snoop Latency.
2882 **/
2883 UINT16 PcieRpLtrMaxNoSnoopLatency[24];
2884
2885 /** Offset 0x08F4 - PCIE RP Snoop Latency Override Mode
2886 Latency Tolerance Reporting, Snoop Latency Override Mode.
2887 **/
2888 UINT8 PcieRpSnoopLatencyOverrideMode[24];
2889
2890 /** Offset 0x090C - PCIE RP Snoop Latency Override Multiplier
2891 Latency Tolerance Reporting, Snoop Latency Override Multiplier.
2892 **/
2893 UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
2894
2895 /** Offset 0x0924 - PCIE RP Snoop Latency Override Value
2896 Latency Tolerance Reporting, Snoop Latency Override Value.
2897 **/
2898 UINT16 PcieRpSnoopLatencyOverrideValue[24];
2899
2900 /** Offset 0x0954 - PCIE RP Non Snoop Latency Override Mode
2901 Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
2902 **/
2903 UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
2904
2905 /** Offset 0x096C - PCIE RP Non Snoop Latency Override Multiplier
2906 Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
2907 **/
2908 UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
2909
2910 /** Offset 0x0984 - PCIE RP Non Snoop Latency Override Value
2911 Latency Tolerance Reporting, Non-Snoop Latency Override Value.
2912 **/
2913 UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
2914
2915 /** Offset 0x09B4 - PCIE RP Slot Power Limit Scale
2916 Specifies scale used for slot power limit value. Leave as 0 to set to default.
2917 **/
2918 UINT8 PcieRpSlotPowerLimitScale[24];
2919
2920 /** Offset 0x09CC - PCIE RP Slot Power Limit Value
2921 Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
2922 **/
2923 UINT16 PcieRpSlotPowerLimitValue[24];
2924
2925 /** Offset 0x09FC - PCIE RP Upstream Port Transmiter Preset
2926 Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
2927 **/
2928 UINT8 PcieRpUptp[24];
2929
2930 /** Offset 0x0A14 - PCIE RP Downstream Port Transmiter Preset
2931 Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
2932 **/
2933 UINT8 PcieRpDptp[24];
2934
2935 /** Offset 0x0A2C - PCIE RP Enable Port8xh Decode
2936 This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
2937 1: Enable.
2938 $EN_DIS
2939 **/
2940 UINT8 PcieEnablePort8xhDecode;
2941
2942 /** Offset 0x0A2D - PCIE Port8xh Decode Port Index
2943 The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
2944 **/
2945 UINT8 PchPciePort8xhDecodePortIndex;
2946
2947 /** Offset 0x0A2E - PCH Pm Disable Energy Report
2948 Disable/Enable PCH to CPU enery report feature.
2949 $EN_DIS
2950 **/
2951 UINT8 PchPmDisableEnergyReport;
2952
2953 /** Offset 0x0A2F - PCH Pm Pmc Read Disable
2954 Deprecated
2955 $EN_DIS
2956 **/
2957 UINT8 PchPmPmcReadDisable;
2958
2959 /** Offset 0x0A30 - PCH Sata Test Mode
2960 Allow entrance to the PCH SATA test modes.
2961 $EN_DIS
2962 **/
2963 UINT8 SataTestMode;
2964
2965 /** Offset 0x0A31
2966 **/
2967 UINT8 ReservedFspsTestUpd[15];
2968 } FSP_S_TEST_CONFIG;
2969
2970 /** Fsp S UPD Configuration
2971 **/
2972 typedef struct {
2973
2974 /** Offset 0x0000
2975 **/
2976 FSP_UPD_HEADER FspUpdHeader;
2977
2978 /** Offset 0x0020
2979 **/
2980 FSP_S_CONFIG FspsConfig;
2981
2982 /** Offset 0x0780
2983 **/
2984 FSP_S_TEST_CONFIG FspsTestConfig;
2985
2986 /** Offset 0x0A40
2987 **/
2988 UINT8 UnusedUpdSpace26[470];
2989
2990 /** Offset 0x0C16
2991 **/
2992 UINT16 UpdTerminator;
2993 } FSPS_UPD;
2994
2995 #pragma pack()
2996
2997 #endif
FSP_S_CONFIG::Early8254ClockGatingEnable
UINT8 Early8254ClockGatingEnable
Offset 0x071F - Enable 8254 Static Clock Gating in early POST time Set 8254CGE=1 is required for C11 ...
Definition: FspsUpd.h:1982
FSP_S_TEST_CONFIG::PsysPowerLimit2Power
UINT32 PsysPowerLimit2Power
Offset 0x0878 - Platform PL2 power Platform PL2 power.
Definition: FspsUpd.h:2765
FSP_S_TEST_CONFIG::ThreeCoreRatioLimit
UINT8 ThreeCoreRatioLimit
Offset 0x079E - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2203
FSP_S_CONFIG::TcoIrqEnable
UINT8 TcoIrqEnable
Offset 0x008A - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
Definition: FspsUpd.h:286
FSP_S_CONFIG::PchHdaIDispLinkFrequency
UINT8 PchHdaIDispLinkFrequency
Offset 0x033A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz...
Definition: FspsUpd.h:974
FSP_S_CONFIG::PchLanClkReqNumber
UINT8 PchLanClkReqNumber
Offset 0x0362 - CLKREQ# used by GbE Valid if ClkReqSupported is TRUE.
Definition: FspsUpd.h:1173
FSP_S_TEST_CONFIG::CstateLatencyControl1Irtl
UINT16 CstateLatencyControl1Irtl
Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit...
Definition: FspsUpd.h:2667
FSP_S_CONFIG::PchSkyCamPortBDataTrimValue
UINT16 PchSkyCamPortBDataTrimValue
Offset 0x0312 - Enable SkyCam Port B Data Trim Value Enable/disable Port B Data Trim Value...
Definition: FspsUpd.h:910
FSP_S_CONFIG::PchSkyCamPortACtleCapValue
UINT8 PchSkyCamPortACtleCapValue
Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value Enable/disable PortA Ctle Cap Value.
Definition: FspsUpd.h:855
FSP_S_CONFIG::PchTTLock
UINT8 PchTTLock
Offset 0x06E5 - Thermal Throttle Lock Thermal Throttle Lock.
Definition: FspsUpd.h:1819
FSP_S_TEST_CONFIG::Custom3PowerLimit2
UINT32 Custom3PowerLimit2
Offset 0x0870 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for c...
Definition: FspsUpd.h:2753
FSP_S_CONFIG::WatchDogTimerBios
UINT16 WatchDogTimerBios
Offset 0x015A - BIOS Timer 16 bits Value, Set BIOS watchdog timer.
Definition: FspsUpd.h:447
FSP_S_CONFIG::SlowSlewRateForIa
UINT8 SlowSlewRateForIa
Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configur...
Definition: FspsUpd.h:647
FSP_S_CONFIG::CridEnable
UINT8 CridEnable
Offset 0x0204 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS...
Definition: FspsUpd.h:480
FSP_S_CONFIG::MeUnconfigOnRtcClear
UINT8 MeUnconfigOnRtcClear
Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear Enable(Default): Enable ME Unconfig On Rtc Cl...
Definition: FspsUpd.h:2075
FSP_S_CONFIG::PchSkyCamPortCDCtleCapValue
UINT8 PchSkyCamPortCDCtleCapValue
Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value Enable/disable PortCD Ctle Cap Value...
Definition: FspsUpd.h:865
FSP_S_TEST_CONFIG::PchPmPmcReadDisable
UINT8 PchPmPmcReadDisable
Offset 0x0A2F - PCH Pm Pmc Read Disable Deprecated $EN_DIS.
Definition: FspsUpd.h:2957
FSP_S_CONFIG::PchT2Level
UINT16 PchT2Level
Offset 0x06E0 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
Definition: FspsUpd.h:1794
FSP_S_CONFIG::PchPmWoWlanDeepSxEnable
UINT8 PchPmWoWlanDeepSxEnable
Offset 0x0643 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the D...
Definition: FspsUpd.h:1437
FSP_S_CONFIG::PchHdaDspPpModuleMask
UINT32 PchHdaDspPpModuleMask
Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules Deprecated: Specific pre/post-pr...
Definition: FspsUpd.h:1017
FSP_S_CONFIG::SataSalpSupport
UINT8 SataSalpSupport
Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management...
Definition: FspsUpd.h:200
FSP_S_CONFIG::PchPmWolEnableOverride
UINT8 PchPmWolEnableOverride
Offset 0x0640 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General ...
Definition: FspsUpd.h:1418
FSP_S_CONFIG::PchSkyCamPortDClkTrimValue
UINT8 PchSkyCamPortDClkTrimValue
Offset 0x030F - Enable SkyCam PortD Clk Trim Value Enable/disable PortD Clk Trim Value.
Definition: FspsUpd.h:900
FSP_S_CONFIG::SataP0TDispFinit
UINT8 SataP0TDispFinit
Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch.
Definition: FspsUpd.h:1914
FSP_S_TEST_CONFIG::PsysPowerLimit2
UINT8 PsysPowerLimit2
Offset 0x07BB - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power...
Definition: FspsUpd.h:2372
FSP_S_CONFIG::TTCrossThrottling
UINT8 TTCrossThrottling
Offset 0x06E7 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
Definition: FspsUpd.h:1831
FSP_S_CONFIG::SataRstCpuAttachedStorage
UINT8 SataRstCpuAttachedStorage
Offset 0x0721 - PCH SATA RST CPU attached storage RST CPU attached storage $EN_DIS.
Definition: FspsUpd.h:1994
FSP_S_TEST_CONFIG::NumberOfEntries
UINT8 NumberOfEntries
Offset 0x07AD - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states.
Definition: FspsUpd.h:2296
FSP_S_CONFIG::PchHdaDspEndpointBluetooth
UINT8 PchHdaDspEndpointBluetooth
Offset 0x033F - DSP Bluetooth enablement 0: Disable; 1: Enable.
Definition: FspsUpd.h:1003
FSP_S_TEST_CONFIG::EnergyEfficientTurbo
UINT8 EnergyEfficientTurbo
Offset 0x07CF - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo...
Definition: FspsUpd.h:2481
FSP_S_CONFIG::PchSubSystemVendorId
UINT16 PchSubSystemVendorId
Offset 0x0366 - PCH Sub system vendor ID Default Subsystem Vendor ID of the PCH devices.
Definition: FspsUpd.h:1197
FSP_S_TEST_CONFIG::EdramTestMode
UINT8 EdramTestMode
Offset 0x0786 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should l...
Definition: FspsUpd.h:2120
FSP_S_TEST_CONFIG::CstateLatencyControl2Irtl
UINT16 CstateLatencyControl2Irtl
Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit...
Definition: FspsUpd.h:2672
FSP_S_TEST_CONFIG::PchLockDownBiosInterface
UINT8 PchLockDownBiosInterface
Offset 0x0890 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes ...
Definition: FspsUpd.h:2854
FSP_S_CONFIG::PchPmSlpStrchSusUp
UINT8 PchPmSlpStrchSusUp
Offset 0x0651 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up...
Definition: FspsUpd.h:1485
FSP_S_CONFIG::PchSkyCamPortBCtleEnable
UINT8 PchSkyCamPortBCtleEnable
Offset 0x0304 - Enable SkyCam PortB Ctle Enable/disable PortB Ctle.
Definition: FspsUpd.h:844
FSP_S_TEST_CONFIG::CpuS3ResumeData
UINT32 CpuS3ResumeData
Offset 0x0880 - CpuS3ResumeData Pointer to CPU S3 Resume Data.
Definition: FspsUpd.h:2781
FSP_S_TEST_CONFIG::C1e
UINT8 C1e
Offset 0x07D9 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states.
Definition: FspsUpd.h:2541
FSP_S_TEST_CONFIG::PpmIrmSetting
UINT8 PpmIrmSetting
Offset 0x07E6 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
Definition: FspsUpd.h:2622
FSP_S_CONFIG::PchIshGp7GpioAssign
UINT8 PchIshGp7GpioAssign
Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1144
AZALIA_HEADER
Azalia Header structure.
Definition: FspsUpd.h:46
FSP_S_CONFIG::IslVrCmd
UINT8 IslVrCmd
Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.
Definition: FspsUpd.h:2087
FSP_S_CONFIG::BiosGuardModulePtr
UINT64 BiosGuardModulePtr
Offset 0x0758 - BiosGuardModulePtr BiosGuardModulePtr default values.
Definition: FspsUpd.h:2045
FSP_S_TEST_CONFIG::PowerLimit4
UINT32 PowerLimit4
Offset 0x0854 - Package PL4 power limit Package PL4 power limit.
Definition: FspsUpd.h:2711
FSP_S_CONFIG::SerialIoEnableDebugUartAfterPost
UINT8 SerialIoEnableDebugUartAfterPost
Offset 0x06D7 - Enable Debug UART Controller Enable debug UART controller after post.
Definition: FspsUpd.h:1756
FSP_S_CONFIG::UnusedUpdSpace18
UINT8 UnusedUpdSpace18
Offset 0x065B.
Definition: FspsUpd.h:1542
FSP_S_CONFIG::FastPkgCRampDisableSa
UINT8 FastPkgCRampDisableSa
Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew R...
Definition: FspsUpd.h:740
FSP_S_TEST_CONFIG::SixCoreRatioLimit
UINT8 SixCoreRatioLimit
Offset 0x0885 - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2793
AZALIA_HEADER::RevisionId
UINT8 RevisionId
Revision ID of the codec. 0xFF matches any revision.
Definition: FspsUpd.h:49
FSP_S_TEST_CONFIG::PsysPowerLimit1Time
UINT8 PsysPowerLimit1Time
Offset 0x07BA - PL1 timewindow PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 ...
Definition: FspsUpd.h:2365
FSP_S_CONFIG::PchLanEnable
UINT8 PchLanEnable
Offset 0x00FB - Enable LAN Enable/disable LAN controller.
Definition: FspsUpd.h:366
FSP_S_TEST_CONFIG::Custom1PowerLimit2
UINT32 Custom1PowerLimit2
Offset 0x0860 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for c...
Definition: FspsUpd.h:2729
FSP_S_CONFIG::PchSkyCamPortCTermOvrEnable
UINT8 PchSkyCamPortCTermOvrEnable
Offset 0x02FD - Enable SkyCam PortC Termination override Enable/disable PortC Termination override...
Definition: FspsUpd.h:802
FSP_S_CONFIG::PchIshGp0GpioAssign
UINT8 PchIshGp0GpioAssign
Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1102
FSP_S_TEST_CONFIG::CstateLatencyControl3TimeUnit
UINT8 CstateLatencyControl3TimeUnit
Offset 0x07E3 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid val...
Definition: FspsUpd.h:2604
FSP_S_TEST_CONFIG::BiProcHot
UINT8 BiProcHot
Offset 0x07D1 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; ...
Definition: FspsUpd.h:2493
AUDIO_AZALIA_VERB_TABLE::Header
AZALIA_HEADER Header
AZALIA PCH header.
Definition: FspsUpd.h:59
FSP_S_CONFIG::PchMemoryThrottlingEnable
UINT8 PchMemoryThrottlingEnable
Offset 0x06FB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
Definition: FspsUpd.h:1937
FSP_S_CONFIG::PchLockDownBiosLock
UINT8 PchLockDownBiosLock
Offset 0x0363 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDC...
Definition: FspsUpd.h:1180
FSP_S_CONFIG::PchCrid
UINT8 PchCrid
Offset 0x0365 - PCH Compatibility Revision ID This member describes whether or not the CRID feature o...
Definition: FspsUpd.h:1192
FSP_S_CONFIG::PchCio2Enable
UINT8 PchCio2Enable
Offset 0x0030 - Enable CIO2 Controller Enable/disable SKYCAM CIO2 Controller.
Definition: FspsUpd.h:137
FSP_S_CONFIG::PchHdaVerbTablePtr
UINT32 PchHdaVerbTablePtr
Offset 0x008C - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
Definition: FspsUpd.h:296
FSP_S_TEST_CONFIG::OneCoreRatioLimit
UINT8 OneCoreRatioLimit
Offset 0x079C - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2191
FSP_S_TEST_CONFIG::PkgCStateUnDemotion
UINT8 PkgCStateUnDemotion
Offset 0x07DB - Enable or Disable Package C-State UnDemotion Enable or Disable Package C-State UnDemo...
Definition: FspsUpd.h:2555
FSP_S_TEST_CONFIG::PchHdaResetWaitTimer
UINT16 PchHdaResetWaitTimer
Offset 0x088E - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of ...
Definition: FspsUpd.h:2848
FSP_S_TEST_CONFIG::EnergyEfficientPState
UINT8 EnergyEfficientPState
Offset 0x07CE - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state...
Definition: FspsUpd.h:2474
FSP_S_CONFIG::PchSkyCamPortADataTrimValue
UINT16 PchSkyCamPortADataTrimValue
Offset 0x0310 - Enable SkyCam Port A Data Trim Value Enable/disable Port A Data Trim Value...
Definition: FspsUpd.h:905
FSP_S_CONFIG::PchSkyCamPortCDDataTrimValue
UINT16 PchSkyCamPortCDDataTrimValue
Offset 0x0314 - Enable SkyCam C/D Data Trim Value Enable/disable C/D Data Trim Value.
Definition: FspsUpd.h:915
FSP_S_CONFIG::PchSkyCamPortBTermOvrEnable
UINT8 PchSkyCamPortBTermOvrEnable
Offset 0x02FC - Enable SkyCam PortB Termination override Enable/disable PortB Termination override...
Definition: FspsUpd.h:796
FSP_S_CONFIG::GmmEnable
UINT8 GmmEnable
Offset 0x0219 - Enable or disable GMM device 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:538
FSP_S_CONFIG::PchIoApicBusNumber
UINT8 PchIoApicBusNumber
Offset 0x034A - PCH Io Apic Bus Number Bus/Device/Function used as Requestor / Completer ID...
Definition: FspsUpd.h:1034
FSP_S_CONFIG::PchPmPwrCycDur
UINT8 PchPmPwrCycDur
Offset 0x065A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second...
Definition: FspsUpd.h:1538
FSP_S_CONFIG::SendEcCmd
UINT64 SendEcCmd
Offset 0x0730 - SendEcCmd SendEcCmd function pointer.
Definition: FspsUpd.h:2035
FSP_S_TEST_CONFIG::CdynmaxClampEnable
UINT8 CdynmaxClampEnable
Offset 0x078E - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable Cd...
Definition: FspsUpd.h:2157
FSP_S_TEST_CONFIG::Custom1ConfigTdpControl
UINT8 Custom1ConfigTdpControl
Offset 0x07B0 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2311
FSP_S_CONFIG::PchScsEmmcHs400RxStrobeDll1
UINT8 PchScsEmmcHs400RxStrobeDll1
Offset 0x06C7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)...
Definition: FspsUpd.h:1715
FSP_S_TEST_CONFIG::CstateLatencyControl4Irtl
UINT16 CstateLatencyControl4Irtl
Offset 0x0844 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit...
Definition: FspsUpd.h:2682
FSP_S_CONFIG::PchPmSlpS3MinAssert
UINT8 PchPmSlpS3MinAssert
Offset 0x0646 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy.
Definition: FspsUpd.h:1454
FSP_S_TEST_CONFIG::GtFreqMax
UINT8 GtFreqMax
Offset 0x0790 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz...
Definition: FspsUpd.h:2177
FSP_S_CONFIG::PchSubSystemId
UINT16 PchSubSystemId
Offset 0x0368 - PCH Sub system ID Default Subsystem ID of the PCH devices.
Definition: FspsUpd.h:1202
FSP_S_CONFIG::PchPmSlpS4MinAssert
UINT8 PchPmSlpS4MinAssert
Offset 0x0647 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy.
Definition: FspsUpd.h:1459
FSP_S_CONFIG::DefaultSvid
UINT16 DefaultSvid
Offset 0x0200 - Subsystem Vendor ID for SA devices Subsystem ID that will be programmed to SA devices...
Definition: FspsUpd.h:469
FSP_S_TEST_CONFIG::CstateLatencyControl3Irtl
UINT16 CstateLatencyControl3Irtl
Offset 0x0842 - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit...
Definition: FspsUpd.h:2677
FSP_S_CONFIG::GraphicsConfigPtr
UINT32 GraphicsConfigPtr
Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
Definition: FspsUpd.h:103
FSP_S_TEST_CONFIG::PkgCStateLimit
UINT8 PkgCStateLimit
Offset 0x07DF - Set the Max Pkg Cstate Set the Max Pkg Cstate.
Definition: FspsUpd.h:2580
FSP_S_CONFIG::PchTTEnable
UINT8 PchTTEnable
Offset 0x06E3 - Enable The Thermal Throttle Enable the thermal throttle function. ...
Definition: FspsUpd.h:1806
FSP_S_CONFIG::PchSkyCamPortAClkTrimValue
UINT8 PchSkyCamPortAClkTrimValue
Offset 0x030C - Enable SkyCam PortA Clk Trim Value Enable/disable PortA Clk Trim Value.
Definition: FspsUpd.h:885
FSP_S_CONFIG::PchScsEmmcHs400TuningRequired
UINT8 PchScsEmmcHs400TuningRequired
Offset 0x06C5 - Enable eMMC HS400 Training Determine if HS400 Training is required.
Definition: FspsUpd.h:1704
FSP_S_CONFIG::PchIoApicBdfValid
UINT8 PchIoApicBdfValid
Offset 0x0349 - Enable PCH Io Apic Set to 1 if BDF value is valid.
Definition: FspsUpd.h:1029
FSP_S_CONFIG::ManageabilityMode
UINT8 ManageabilityMode
Offset 0x0156 - Manageability Mode set by Mebx Enable/Disable.
Definition: FspsUpd.h:428
FSP_S_CONFIG::SendVrMbxCmd
UINT8 SendVrMbxCmd
Offset 0x02E2 - Enable VR specific mailbox command VR specific mailbox commands.
Definition: FspsUpd.h:752
FSP_S_CONFIG::SaImguEnable
UINT8 SaImguEnable
Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM) Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM) $EN_DIS.
Definition: FspsUpd.h:532
FSP_S_CONFIG::CdClock
UINT8 CdClock
Offset 0x0216 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz 0:...
Definition: FspsUpd.h:520
FSP_S_CONFIG::PchSkyCamPortBCtleCapValue
UINT8 PchSkyCamPortBCtleCapValue
Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value Enable/disable PortB Ctle Cap Value.
Definition: FspsUpd.h:860
FSP_S_CONFIG::XdciEnable
UINT8 XdciEnable
Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller.
Definition: FspsUpd.h:230
FSP_S_TEST_CONFIG::Custom2PowerLimit1Time
UINT8 Custom2PowerLimit1Time
Offset 0x07B1 - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2316
FSP_S_TEST_CONFIG::DisableD0I3SettingForHeci
UINT8 DisableD0I3SettingForHeci
Offset 0x088C - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disabl...
Definition: FspsUpd.h:2837
FSP_S_CONFIG::PchIoApicDeviceNumber
UINT8 PchIoApicDeviceNumber
Offset 0x034B - PCH Io Apic Device Number Bus/Device/Function used as Requestor / Completer ID...
Definition: FspsUpd.h:1039
FSP_S_CONFIG::PchIoApicFunctionNumber
UINT8 PchIoApicFunctionNumber
Offset 0x034C - PCH Io Apic Function Number Bus/Device/Function used as Requestor / Completer ID...
Definition: FspsUpd.h:1044
FSP_S_CONFIG::SataP1T3M
UINT8 SataP1T3M
Offset 0x06F4 - Port 1 T3 Multipler Port 1 T3 Multipler.
Definition: FspsUpd.h:1898
FSP_S_TEST_CONFIG::DmiIot
UINT8 DmiIot
Offset 0x0788 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Con...
Definition: FspsUpd.h:2133
FSP_S_TEST_CONFIG::Signature
UINT32 Signature
Offset 0x0780.
Definition: FspsUpd.h:2100
FSP_S_TEST_CONFIG::TimedMwait
UINT8 TimedMwait
Offset 0x07DD - Enable or Disable TimedMwait Support.
Definition: FspsUpd.h:2567
FSP_S_TEST_CONFIG::ConfigTdpBios
UINT8 ConfigTdpBios
Offset 0x07B8 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disabl...
Definition: FspsUpd.h:2353
FSP_S_CONFIG::PchDmiTsawEn
UINT8 PchDmiTsawEn
Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable...
Definition: FspsUpd.h:1837
FSP_S_TEST_CONFIG::Custom1PowerLimit1
UINT32 Custom1PowerLimit1
Offset 0x085C - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for...
Definition: FspsUpd.h:2723
FSP_S_CONFIG::AsfEnabled
UINT8 AsfEnabled
Offset 0x0155 - ASF Switch Enable/Disable.
Definition: FspsUpd.h:422
FSP_S_TEST_CONFIG::DmiExtSync
UINT8 DmiExtSync
Offset 0x0787 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS.
Definition: FspsUpd.h:2127
FSP_S_TEST_CONFIG::PchLockDownGlobalSmi
UINT8 PchLockDownGlobalSmi
Offset 0x088D - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bi...
Definition: FspsUpd.h:2843
FSP_S_TEST_CONFIG::FourCoreRatioLimit
UINT8 FourCoreRatioLimit
Offset 0x079F - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2209
FSP_S_CONFIG::PeiGraphicsPeimInit
UINT8 PeiGraphicsPeimInit
Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
Definition: FspsUpd.h:526
FSP_S_CONFIG::MicrocodeRegionBase
UINT32 MicrocodeRegionBase
Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
Definition: FspsUpd.h:183
FSP_S_TEST_CONFIG::PchPmDisableEnergyReport
UINT8 PchPmDisableEnergyReport
Offset 0x0A2E - PCH Pm Disable Energy Report Disable/Enable PCH to CPU enery report feature...
Definition: FspsUpd.h:2951
FSP_S_CONFIG::TcoIrqSelect
UINT8 TcoIrqSelect
Offset 0x0089 - Select TcoIrqSelect TCO IRQ Select.
Definition: FspsUpd.h:280
FSP_S_TEST_CONFIG::Custom1PowerLimit1Time
UINT8 Custom1PowerLimit1Time
Offset 0x07AE - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2301
FSP_S_TEST_CONFIG::VoltageOptimization
UINT8 VoltageOptimization
Offset 0x07CC - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization...
Definition: FspsUpd.h:2461
FSP_S_CONFIG::PchPmWoWlanEnable
UINT8 PchPmWoWlanEnable
Offset 0x0642 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP...
Definition: FspsUpd.h:1430
FSP_S_CONFIG::PchSkyCamPortCDCtleResValue
UINT8 PchSkyCamPortCDCtleResValue
Offset 0x030B - Enable SkyCam PortCD Ctle Res Value Enable/disable PortCD Ctle Res Value...
Definition: FspsUpd.h:880
FSP_S_CONFIG::PchPmDisableDsxAcPresentPulldown
UINT8 PchPmDisableDsxAcPresentPulldown
Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_P...
Definition: FspsUpd.h:1502
FSP_S_CONFIG::PchPmWolOvrWkSts
UINT8 PchPmWolOvrWkSts
Offset 0x0659 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRS...
Definition: FspsUpd.h:1532
FSP_S_TEST_CONFIG::DebugInterfaceLockEnable
UINT8 DebugInterfaceLockEnable
Offset 0x07C3 - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: D...
Definition: FspsUpd.h:2412
FSP_S_CONFIG::SataPwrOptEnable
UINT8 SataPwrOptEnable
Offset 0x065D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side.
Definition: FspsUpd.h:1555
FSP_S_CONFIG::PchSirqMode
UINT8 PchSirqMode
Offset 0x06D9 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode...
Definition: FspsUpd.h:1768
FSP_S_CONFIG::PchIshUart0GpioAssign
UINT8 PchIshUart0GpioAssign
Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1072
FSP_S_TEST_CONFIG::Custom1TurboActivationRatio
UINT8 Custom1TurboActivationRatio
Offset 0x07AF - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1...
Definition: FspsUpd.h:2306
AZALIA_HEADER::SdiNum
UINT8 SdiNum
SDI number, 0xFF matches any SDI.
Definition: FspsUpd.h:50
FSP_S_TEST_CONFIG::PowerLimit2
UINT8 PowerLimit2
Offset 0x07A4 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode.
Definition: FspsUpd.h:2238
FSP_S_CONFIG::PchSkyCamPortCClkTrimValue
UINT8 PchSkyCamPortCClkTrimValue
Offset 0x030E - Enable SkyCam PortC Clk Trim Value Enable/disable PortC Clk Trim Value.
Definition: FspsUpd.h:895
FSP_S_CONFIG::UnusedUpdSpace0
UINT8 UnusedUpdSpace0
Offset 0x0037.
Definition: FspsUpd.h:178
FSP_S_CONFIG::SataRstHddUnlock
UINT8 SataRstHddUnlock
Offset 0x06B8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled...
Definition: FspsUpd.h:1664
FSP_S_TEST_CONFIG::ProcTraceOutputScheme
UINT8 ProcTraceOutputScheme
Offset 0x07C8 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0:...
Definition: FspsUpd.h:2434
FSP_S_CONFIG::SataMode
UINT8 SataMode
Offset 0x0092 - SATA Mode Select SATA controller working mode.
Definition: FspsUpd.h:312
FSP_S_CONFIG::SataRstRaid5
UINT8 SataRstRaid5
Offset 0x06B4 - PCH Sata Rst Raid5 RAID5.
Definition: FspsUpd.h:1641
FSP_S_TEST_CONFIG::RaceToHalt
UINT8 RaceToHalt
Offset 0x07E9 - Race To Halt Enable/Disable Race To Halt feature.
Definition: FspsUpd.h:2643
FSP_S_CONFIG::PchThermalDeviceEnable
UINT8 PchThermalDeviceEnable
Offset 0x06DB - Enable Thermal Device Enable Thermal Device.
Definition: FspsUpd.h:1779
FSP_S_TEST_CONFIG::TStates
UINT8 TStates
Offset 0x07D0 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable...
Definition: FspsUpd.h:2487
FspUpd.h
FSP_S_TEST_CONFIG::CstateLatencyControl2TimeUnit
UINT8 CstateLatencyControl2TimeUnit
Offset 0x07E2 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid val...
Definition: FspsUpd.h:2598
AZALIA_HEADER::DataDwords
UINT16 DataDwords
Number of data DWORDs pointed by the codec data buffer.
Definition: FspsUpd.h:51
FSP_S_TEST_CONFIG::CstateLatencyControl5Irtl
UINT16 CstateLatencyControl5Irtl
Offset 0x0846 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit...
Definition: FspsUpd.h:2687
FSP_S_TEST_CONFIG::SevenCoreRatioLimit
UINT8 SevenCoreRatioLimit
Offset 0x0886 - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2799
FSP_S_TEST_CONFIG::MaxRatio
UINT16 MaxRatio
Offset 0x07EA - Max P-State Ratio Max P-State Ratio , Valid Range 0 to 0x7F.
Definition: FspsUpd.h:2648
FSP_S_CONFIG::UnusedUpdSpace2
UINT8 UnusedUpdSpace2
Offset 0x0090.
Definition: FspsUpd.h:300
FSP_S_TEST_CONFIG::TwoCoreRatioLimit
UINT8 TwoCoreRatioLimit
Offset 0x079D - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2197
FSP_S_TEST_CONFIG::PowerLimit3DutyCycle
UINT8 PowerLimit3DutyCycle
Offset 0x07A7 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100...
Definition: FspsUpd.h:2255
FSP_S_CONFIG::PchPmLanWakeFromDeepSx
UINT8 PchPmLanWakeFromDeepSx
Offset 0x0644 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx...
Definition: FspsUpd.h:1443
FSP_S_CONFIG::SendVrMbxCmd1
UINT8 SendVrMbxCmd1
Offset 0x02E3 - Select VR specific mailbox command to send VR specific mailbox commands.
Definition: FspsUpd.h:759
FSP_S_TEST_CONFIG::ConfigTdpLock
UINT8 ConfigTdpLock
Offset 0x07B7 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0...
Definition: FspsUpd.h:2347
FSP_S_CONFIG::SataThermalSuggestedSetting
UINT8 SataThermalSuggestedSetting
Offset 0x06FA - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting...
Definition: FspsUpd.h:1931
FSP_S_CONFIG::SgxSinitNvsData
UINT8 SgxSinitNvsData
Offset 0x0764 - SgxSinitNvsData SgxSinitNvsData default values.
Definition: FspsUpd.h:2055
FSP_S_CONFIG::WatchDog
UINT8 WatchDog
Offset 0x0154 - WatchDog Timer Switch Enable/Disable.
Definition: FspsUpd.h:416
FSP_S_TEST_CONFIG::ApIdleManner
UINT8 ApIdleManner
Offset 0x07C4 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; ...
Definition: FspsUpd.h:2418
FSP_S_CONFIG::DmiTS0TW
UINT8 DmiTS0TW
Offset 0x06EA - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width.
Definition: FspsUpd.h:1848
FSP_S_CONFIG::PchHdaDspEndpointDmic
UINT8 PchHdaDspEndpointDmic
Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum) 0: Disable; 1: 2ch array; 2: 4ch array; ...
Definition: FspsUpd.h:997
FSP_S_TEST_CONFIG::MachineCheckEnable
UINT8 MachineCheckEnable
Offset 0x07C1 - Enable or Disable initialization of machine check registers Enable or Disable initial...
Definition: FspsUpd.h:2400
FSP_S_CONFIG::EcCmdLock
UINT8 EcCmdLock
Offset 0x072A - EcCmdLock EcCmdLock default values.
Definition: FspsUpd.h:2024
FSP_S_TEST_CONFIG::Custom2PowerLimit2
UINT32 Custom2PowerLimit2
Offset 0x0868 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for c...
Definition: FspsUpd.h:2741
FSPS_UPD
Fsp S UPD Configuration.
Definition: FspsUpd.h:2972
FSP_S_CONFIG::SataEnable
UINT8 SataEnable
Offset 0x0091 - Enable SATA Enable/disable SATA controller.
Definition: FspsUpd.h:306
FSP_S_CONFIG::PchHdaIDispLinkTmode
UINT8 PchHdaIDispLinkTmode
Offset 0x033B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T...
Definition: FspsUpd.h:979
FSP_S_TEST_CONFIG::PowerLimit4Lock
UINT8 PowerLimit4Lock
Offset 0x07A9 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS...
Definition: FspsUpd.h:2267
FSP_S_CONFIG::PchDisableComplianceMode
UINT8 PchDisableComplianceMode
Offset 0x0704 - Disable XHCI Compliance Mode This policy will disable XHCI compliance mode on all por...
Definition: FspsUpd.h:1964
FSP_S_TEST_CONFIG::ProcTraceMemSize
UINT8 ProcTraceMemSize
Offset 0x07CA - Memory region allocation for Processor Trace Memory region allocation for Processor T...
Definition: FspsUpd.h:2451
FSP_S_CONFIG::PchPmLpcClockRun
UINT8 PchPmLpcClockRun
Offset 0x0650 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of...
Definition: FspsUpd.h:1479
FSP_S_TEST_CONFIG::EightCoreRatioLimit
UINT8 EightCoreRatioLimit
Offset 0x0887 - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2805
FSP_S_CONFIG::SataP1T1M
UINT8 SataP1T1M
Offset 0x06F2 - Port 1 T1 Multipler Port 1 T1 Multipler.
Definition: FspsUpd.h:1888
FSP_S_CONFIG::SataP0T3M
UINT8 SataP0T3M
Offset 0x06F0 - Port 0 T3 Multipler Port 0 T3 Multipler.
Definition: FspsUpd.h:1878
FSP_S_TEST_CONFIG::TccOffsetLock
UINT8 TccOffsetLock
Offset 0x07AC - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock ...
Definition: FspsUpd.h:2290
FSP_S_CONFIG::PchScsEmmcHs400DriverStrength
UINT8 PchScsEmmcHs400DriverStrength
Offset 0x06C9 - I/O Driver Strength I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm...
Definition: FspsUpd.h:1725
FSP_S_CONFIG::PchSkyCamPortDTrimEnable
UINT8 PchSkyCamPortDTrimEnable
Offset 0x0302 - Enable SkyCam PortD Clk Trim Enable/disable PortD Clk Trim.
Definition: FspsUpd.h:832
FSP_S_CONFIG::LogoSize
UINT32 LogoSize
Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
Definition: FspsUpd.h:98
FSP_S_CONFIG::NumOfDevIntConfig
UINT8 NumOfDevIntConfig
Offset 0x006F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry...
Definition: FspsUpd.h:246
FSP_S_TEST_CONFIG::Hwp
UINT8 Hwp
Offset 0x07A1 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support.
Definition: FspsUpd.h:2220
FSP_S_CONFIG::AmtSolEnabled
UINT8 AmtSolEnabled
Offset 0x015C - SOL Switch Enable/Disable.
Definition: FspsUpd.h:453
FSP_S_CONFIG::SsicPortEnable
UINT8 SsicPortEnable
Offset 0x006D - Enable XHCI SSIC Enable Enable/disable XHCI SSIC port.
Definition: FspsUpd.h:236
FSP_S_CONFIG::SataRstRaid1
UINT8 SataRstRaid1
Offset 0x06B2 - PCH Sata Rst Raid1 RAID1.
Definition: FspsUpd.h:1629
FSP_S_CONFIG::PchSkyCamPortDTermOvrEnable
UINT8 PchSkyCamPortDTermOvrEnable
Offset 0x02FE - Enable SkyCam PortD Termination override Enable/disable PortD Termination override...
Definition: FspsUpd.h:808
FSP_S_TEST_CONFIG::ProcHotLock
UINT8 ProcHotLock
Offset 0x07E7 - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: ...
Definition: FspsUpd.h:2628
FSP_S_CONFIG::PchHdaDspEndpointI2s
UINT8 PchHdaDspEndpointI2s
Offset 0x0348 - DSP I2S enablement 0: Disable; 1: Enable.
Definition: FspsUpd.h:1023
FSP_S_CONFIG::PchIshPdtUnlock
UINT8 PchIshPdtUnlock
Offset 0x035E - PCH ISH PDT Unlock Msg 0: False; 1: True.
Definition: FspsUpd.h:1150
FSP_S_CONFIG::PchHdaEnable
UINT8 PchHdaEnable
Offset 0x002D - Enable Intel HD Audio (Azalia) Enable/disable Azalia controller.
Definition: FspsUpd.h:115
FSP_S_CONFIG::SataRstOromUiBanner
UINT8 SataRstOromUiBanner
Offset 0x06B6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER.
Definition: FspsUpd.h:1653
FSP_S_TEST_CONFIG::AutoThermalReporting
UINT8 AutoThermalReporting
Offset 0x07D5 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI ...
Definition: FspsUpd.h:2517
FSP_S_CONFIG::ShowSpiController
UINT8 ShowSpiController
Offset 0x0035 - Show SPI controller Enable/disable to show SPI controller.
Definition: FspsUpd.h:167
FSP_S_CONFIG::FwProgress
UINT8 FwProgress
Offset 0x0157 - PET Progress Enable/Disable.
Definition: FspsUpd.h:435
FSP_S_CONFIG::EnableTcoTimer
UINT8 EnableTcoTimer
Offset 0x0728 - Enable TCO timer.
Definition: FspsUpd.h:2014
FSP_S_CONFIG::PchIoApicRangeSelect
UINT8 PchIoApicRangeSelect
Offset 0x034F - PCH Io Apic Range Select Define address bits 19:12 for the IOxAPIC range...
Definition: FspsUpd.h:1060
FSP_S_CONFIG::DevIntConfigPtr
UINT32 DevIntConfigPtr
Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
Definition: FspsUpd.h:251
FSP_S_CONFIG::SciIrqSelect
UINT8 SciIrqSelect
Offset 0x0088 - Select SciIrqSelect SCI IRQ Select.
Definition: FspsUpd.h:275
FSP_S_CONFIG::Heci3Enabled
UINT8 Heci3Enabled
Offset 0x0149 - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not i...
Definition: FspsUpd.h:400
FSP_S_TEST_CONFIG::TccOffsetClamp
UINT8 TccOffsetClamp
Offset 0x07AB - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limi...
Definition: FspsUpd.h:2283
FSP_S_TEST_CONFIG::Custom3TurboActivationRatio
UINT8 Custom3TurboActivationRatio
Offset 0x07B5 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3...
Definition: FspsUpd.h:2336
FSP_S_TEST_CONFIG::MonitorMwaitEnable
UINT8 MonitorMwaitEnable
Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instru...
Definition: FspsUpd.h:2394
FSP_S_CONFIG::PchT0Level
UINT16 PchT0Level
Offset 0x06DC - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
Definition: FspsUpd.h:1784
FSP_S_CONFIG::SpiFlashCfgLockDown
UINT8 SpiFlashCfgLockDown
Offset 0x0036 - Flash Configuration Lock Down Enable/disable flash lock down.
Definition: FspsUpd.h:174
FSPS_UPD::FspsConfig
FSP_S_CONFIG FspsConfig
Offset 0x0020.
Definition: FspsUpd.h:2980
FSP_S_CONFIG::PchIshGp2GpioAssign
UINT8 PchIshGp2GpioAssign
Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1114
FSP_S_CONFIG::PchDmiAspm
UINT8 PchDmiAspm
Offset 0x0316 - Enable DMI ASPM ASPM on PCH side of the DMI Link.
Definition: FspsUpd.h:921
FSP_S_TEST_CONFIG::CstateLatencyControl5TimeUnit
UINT8 CstateLatencyControl5TimeUnit
Offset 0x07E5 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid val...
Definition: FspsUpd.h:2616
FSP_S_CONFIG::MicrocodePatchAddress
UINT64 MicrocodePatchAddress
Offset 0x02F0 - MicrocodePatchAddress Pointer to microcode patch that is suitable for this processor...
Definition: FspsUpd.h:775
FSP_S_CONFIG::PsysOffset
UINT8 PsysOffset
Offset 0x0277 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction...
Definition: FspsUpd.h:627
FSP_S_CONFIG::PchHdaDspFeatureMask
UINT32 PchHdaDspFeatureMask
Offset 0x0340 - Bitmask of supported DSP features [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec ...
Definition: FspsUpd.h:1010
FSP_S_TEST_CONFIG::PowerLimit3Lock
UINT8 PowerLimit3Lock
Offset 0x07A8 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS...
Definition: FspsUpd.h:2261
FSP_S_CONFIG::MeUnconfigIsValid
UINT8 MeUnconfigIsValid
Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid The MeUnconfigOnRtcClear item could be not val...
Definition: FspsUpd.h:2081
FSP_S_CONFIG::SataRstOromUiDelay
UINT8 SataRstOromUiDelay
Offset 0x06B7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PC...
Definition: FspsUpd.h:1658
SiPchNoInt
No Interrupt Pin.
Definition: FspsUpd.h:67
FSP_S_TEST_CONFIG::FiveCoreRatioLimit
UINT8 FiveCoreRatioLimit
Offset 0x0884 - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM t...
Definition: FspsUpd.h:2787
FSP_S_CONFIG::PchHdaIoBufferOwnership
UINT8 PchHdaIoBufferOwnership
Offset 0x002F - Select HDAudio IoBuffer Ownership Indicates the ownership of the I/O buffer between I...
Definition: FspsUpd.h:131
FSP_S_CONFIG::TTSuggestedSetting
UINT8 TTSuggestedSetting
Offset 0x06E6 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting...
Definition: FspsUpd.h:1825
FSP_S_CONFIG::PsysSlope
UINT8 PsysSlope
Offset 0x0276 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction...
Definition: FspsUpd.h:621
FSP_S_CONFIG::PchPmDeepSxPol
UINT8 PchPmDeepSxPol
Offset 0x0645 - PCH Pm Deep Sx Pol Deep Sx Policy.
Definition: FspsUpd.h:1449
FSP_S_CONFIG::PchIoApicEntry24_119
UINT8 PchIoApicEntry24_119
Offset 0x034D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable.
Definition: FspsUpd.h:1050
FSP_S_CONFIG::PchSkyCamPortBClkTrimValue
UINT8 PchSkyCamPortBClkTrimValue
Offset 0x030D - Enable SkyCam PortB Clk Trim Value Enable/disable PortB Clk Trim Value.
Definition: FspsUpd.h:890
FSP_S_TEST_CONFIG::CStatePreWake
UINT8 CStatePreWake
Offset 0x07DC - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake.
Definition: FspsUpd.h:2561
FSP_S_CONFIG::SataRstRaid0
UINT8 SataRstRaid0
Offset 0x06B1 - PCH Sata Rst Raid0 RAID0.
Definition: FspsUpd.h:1623
FSP_S_CONFIG::SgxEpoch1
UINT64 SgxEpoch1
Offset 0x0770 - SgxEpoch1 SgxEpoch1 default values.
Definition: FspsUpd.h:2069
FSP_S_CONFIG::PchLegacyIoLowLatency
UINT8 PchLegacyIoLowLatency
Offset 0x036A - PCH Legacy IO Low Latency Enable todo $EN_DIS.
Definition: FspsUpd.h:1208
FSP_S_CONFIG::PchPmSlpLanLowDc
UINT8 PchPmSlpLanLowDc
Offset 0x0652 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power.
Definition: FspsUpd.h:1491
FSP_S_CONFIG::SataRstRaid10
UINT8 SataRstRaid10
Offset 0x06B3 - PCH Sata Rst Raid10 RAID10.
Definition: FspsUpd.h:1635
FSP_S_TEST_CONFIG::CstCfgCtrIoMwaitRedirection
UINT8 CstCfgCtrIoMwaitRedirection
Offset 0x07DE - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; ...
Definition: FspsUpd.h:2573
FSP_S_CONFIG::PchHdaLinkFrequency
UINT8 PchHdaLinkFrequency
Offset 0x0339 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz...
Definition: FspsUpd.h:969
FSP_S_TEST_CONFIG::PsysPowerLimit1
UINT8 PsysPowerLimit1
Offset 0x07B9 - PL1 Enable value PL1 Enable value to limit average platform power.
Definition: FspsUpd.h:2359
FSP_S_TEST_CONFIG::ThermalMonitor
UINT8 ThermalMonitor
Offset 0x07D6 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: E...
Definition: FspsUpd.h:2523
FSP_S_CONFIG::DmiSuggestedSetting
UINT8 DmiSuggestedSetting
Offset 0x06E9 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative valu...
Definition: FspsUpd.h:1843
FSP_S_CONFIG::PchIshGp6GpioAssign
UINT8 PchIshGp6GpioAssign
Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1138
FSP_S_CONFIG::PchHdaDspEnable
UINT8 PchHdaDspEnable
Offset 0x002E - Enable HD Audio DSP Enable/disable HD Audio DSP feature.
Definition: FspsUpd.h:121
FSP_S_CONFIG::PchPmSlpS0VmEnable
UINT8 PchPmSlpS0VmEnable
Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable Indicates platform has support for VCCPrim_Cor...
Definition: FspsUpd.h:1408
FSP_S_CONFIG::DmiTS1TW
UINT8 DmiTS1TW
Offset 0x06EB - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width.
Definition: FspsUpd.h:1853
FSP_S_CONFIG::AcousticNoiseMitigation
UINT8 AcousticNoiseMitigation
Offset 0x0278 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature...
Definition: FspsUpd.h:633
FSP_S_CONFIG::PchScsEmmcHs400TxDataDll
UINT8 PchScsEmmcHs400TxDataDll
Offset 0x06C8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)...
Definition: FspsUpd.h:1720
FSP_S_TEST_CONFIG::ConfigTdpLevel
UINT8 ConfigTdpLevel
Offset 0x07E8 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nom...
Definition: FspsUpd.h:2635
FSP_S_CONFIG::EcCmdProvisionEav
UINT8 EcCmdProvisionEav
Offset 0x0729 - EcCmdProvisionEav Ephemeral Authorization Value default values.
Definition: FspsUpd.h:2019
FSP_S_CONFIG::PchSkyCamPortATermOvrEnable
UINT8 PchSkyCamPortATermOvrEnable
Offset 0x02FB - Enable SkyCam PortA Termination override Enable/disable PortA Termination override...
Definition: FspsUpd.h:790
FSP_S_CONFIG::BiosGuardAttr
UINT32 BiosGuardAttr
Offset 0x0760 - BiosGuardAttr BiosGuardAttr default values.
Definition: FspsUpd.h:2050
FSPS_UPD::FspUpdHeader
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FspsUpd.h:2976
FSP_S_CONFIG::Device4Enable
UINT8 Device4Enable
Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
Definition: FspsUpd.h:109
FSP_S_CONFIG::PchTTState13Enable
UINT8 PchTTState13Enable
Offset 0x06E4 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 1...
Definition: FspsUpd.h:1813
SI_PCH_DEVICE_INTERRUPT_CONFIG::Irq
UINT8 Irq
IRQ to be set for device.
Definition: FspsUpd.h:80
FSPS_UPD::UpdTerminator
UINT16 UpdTerminator
Offset 0x0C16.
Definition: FspsUpd.h:2992
FSP_S_CONFIG::SlowSlewRateForGt
UINT8 SlowSlewRateForGt
Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configur...
Definition: FspsUpd.h:654
FSP_S_TEST_CONFIG::Custom2TurboActivationRatio
UINT8 Custom2TurboActivationRatio
Offset 0x07B2 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2...
Definition: FspsUpd.h:2321
FSP_S_CONFIG::TurboMode
UINT8 TurboMode
Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode.
Definition: FspsUpd.h:194
FSP_S_CONFIG::PchScsEmmcHs400DllDataValid
UINT8 PchScsEmmcHs400DllDataValid
Offset 0x06C6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid.
Definition: FspsUpd.h:1710
FSP_S_CONFIG::PchHdaPme
UINT8 PchHdaPme
Offset 0x0336 - Enable Pme Enable Azalia wake-on-ring.
Definition: FspsUpd.h:954
FSP_S_TEST_CONFIG::CstateLatencyControl1TimeUnit
UINT8 CstateLatencyControl1TimeUnit
Offset 0x07E1 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid val...
Definition: FspsUpd.h:2592
FSP_S_TEST_CONFIG::ApHandoffManner
UINT8 ApHandoffManner
Offset 0x07C5 - Settings for AP Handoff to OS Settings for AP Handoff to OS; 1: HALT loop; 2: MWAIT l...
Definition: FspsUpd.h:2424
FSP_S_CONFIG::UnusedUpdSpace14
UINT8 UnusedUpdSpace14
Offset 0x02FA.
Definition: FspsUpd.h:784
FSP_S_CONFIG::PchHdaVcType
UINT8 PchHdaVcType
Offset 0x0338 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1.
Definition: FspsUpd.h:964
FSP_S_CONFIG::PchTsmicLock
UINT8 PchTsmicLock
Offset 0x06E2 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip...
Definition: FspsUpd.h:1800
FSP_S_CONFIG::DelayUsbPdoProgramming
UINT8 DelayUsbPdoProgramming
Offset 0x00FC - Delay USB PDO Programming Enable/disable delay of PDO programming for USB from PEI ph...
Definition: FspsUpd.h:373
FSP_S_TEST_CONFIG::PowerLimit3Time
UINT8 PowerLimit3Time
Offset 0x07A6 - Package PL3 time window Package PL3 time window range for this policy in milliseconds...
Definition: FspsUpd.h:2250
FSP_S_CONFIG::PchIshGp5GpioAssign
UINT8 PchIshGp5GpioAssign
Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1132
FSP_S_CONFIG::PchHdaIDispCodecDisconnect
UINT8 PchHdaIDispCodecDisconnect
Offset 0x033D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
Definition: FspsUpd.h:992
FSP_S_CONFIG::WatchDogTimerOs
UINT16 WatchDogTimerOs
Offset 0x0158 - OS Timer 16 bits Value, Set OS watchdog timer.
Definition: FspsUpd.h:441
FSP_S_TEST_CONFIG::PmgCstCfgCtrlLock
UINT8 PmgCstCfgCtrlLock
Offset 0x07D8 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable...
Definition: FspsUpd.h:2535
FSP_S_CONFIG::PchIshGp1GpioAssign
UINT8 PchIshGp1GpioAssign
Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1108
FSP_S_TEST_CONFIG::UnusedUpdSpace22
UINT8 UnusedUpdSpace22
Offset 0x07A0.
Definition: FspsUpd.h:2213
FSP_S_CONFIG::PchHdaDspUaaCompliance
UINT8 PchHdaDspUaaCompliance
Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (...
Definition: FspsUpd.h:986
FSP_S_CONFIG::DmiTS3TW
UINT8 DmiTS3TW
Offset 0x06ED - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width.
Definition: FspsUpd.h:1863
FSP_S_TEST_CONFIG::PowerLimit1Time
UINT8 PowerLimit1Time
Offset 0x07A3 - Package Long duration turbo mode time Package Long duration turbo mode time window in...
Definition: FspsUpd.h:2232
FSP_S_TEST_CONFIG::PchLockDownRtcLock
UINT8 PchLockDownRtcLock
Offset 0x0891 - RTC CMOS RAM LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh...
Definition: FspsUpd.h:2861
FSP_S_TEST_CONFIG::MlcSpatialPrefetcher
UINT8 MlcSpatialPrefetcher
Offset 0x07BF - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0:...
Definition: FspsUpd.h:2388
FSP_S_TEST_CONFIG::Custom2ConfigTdpControl
UINT8 Custom2ConfigTdpControl
Offset 0x07B3 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2326
FSP_S_CONFIG::ScsSdCardEnabled
UINT8 ScsSdCardEnabled
Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller.
Definition: FspsUpd.h:155
FSP_S_CONFIG::EsataSpeedLimit
UINT8 EsataSpeedLimit
Offset 0x065E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
Definition: FspsUpd.h:1561
FSP_S_TEST_CONFIG
Fsp S Test Configuration.
Definition: FspsUpd.h:2096
FSP_S_CONFIG::PchPwrOptEnable
UINT8 PchPwrOptEnable
Offset 0x0317 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side.
Definition: FspsUpd.h:927
FSP_S_CONFIG::PchPcieDeviceOverrideTablePtr
UINT32 PchPcieDeviceOverrideTablePtr
Offset 0x0724 - Pch PCIE device override table pointer The PCIe device table is being used to overrid...
Definition: FspsUpd.h:2006
FSP_S_TEST_CONFIG::HdcControl
UINT8 HdcControl
Offset 0x07A2 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration.
Definition: FspsUpd.h:2226
FSP_S_TEST_CONFIG::Custom3PowerLimit1Time
UINT8 Custom3PowerLimit1Time
Offset 0x07B4 - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2331
FSP_S_CONFIG::PchPmPcieWakeFromDeepSx
UINT8 PchPmPcieWakeFromDeepSx
Offset 0x0641 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx...
Definition: FspsUpd.h:1424
FSP_S_TEST_CONFIG::PsysPowerLimit1Power
UINT32 PsysPowerLimit1Power
Offset 0x0874 - Platform PL1 power Platform PL1 power.
Definition: FspsUpd.h:2759
FSP_S_CONFIG::SataSpeedLimit
UINT8 SataSpeedLimit
Offset 0x065F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: ...
Definition: FspsUpd.h:1566
AUDIO_AZALIA_VERB_TABLE
Audio Azalia Verb Table structure.
Definition: FspsUpd.h:58
FSP_S_CONFIG::MicrocodeRegionSize
UINT32 MicrocodeRegionSize
Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
Definition: FspsUpd.h:188
FSP_S_CONFIG::SataP1T2M
UINT8 SataP1T2M
Offset 0x06F3 - Port 1 T2 Multipler Port 1 T2 Multipler.
Definition: FspsUpd.h:1893
FSP_S_CONFIG::PchLanClkReqSupported
UINT8 PchLanClkReqSupported
Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported 0: Disable; 1: Enable.
Definition: FspsUpd.h:1168
FSP_S_CONFIG::PchIshGp3GpioAssign
UINT8 PchIshGp3GpioAssign
Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1120
FSP_S_CONFIG::SataRstSmartStorage
UINT8 SataRstSmartStorage
Offset 0x06BB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit.
Definition: FspsUpd.h:1683
FSP_S_TEST_CONFIG::TurboPowerLimitLock
UINT8 TurboPowerLimitLock
Offset 0x07A5 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable ...
Definition: FspsUpd.h:2244
FSP_S_CONFIG::PchIshI2c2GpioAssign
UINT8 PchIshI2c2GpioAssign
Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1096
AUDIO_AZALIA_VERB_TABLE::Data
UINT32 * Data
Pointer to the data buffer. Its length is specified in the header.
Definition: FspsUpd.h:60
AZALIA_HEADER::VendorId
UINT16 VendorId
Codec Vendor ID.
Definition: FspsUpd.h:47
FSP_S_CONFIG::PchIoApicId
UINT8 PchIoApicId
Offset 0x034E - PCH Io Apic ID This member determines IOAPIC ID.
Definition: FspsUpd.h:1055
FSP_S_CONFIG::SgxEpoch0
UINT64 SgxEpoch0
Offset 0x0768 - SgxEpoch0 SgxEpoch0 default values.
Definition: FspsUpd.h:2064
FSP_S_TEST_CONFIG::Cx
UINT8 Cx
Offset 0x07D7 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-s...
Definition: FspsUpd.h:2529
FSP_S_CONFIG::SataP1TDispFinit
UINT8 SataP1TDispFinit
Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch.
Definition: FspsUpd.h:1925
FSP_S_CONFIG::PavpEnable
UINT8 PavpEnable
Offset 0x0215 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEn...
Definition: FspsUpd.h:514
FSP_S_TEST_CONFIG::ProcTraceEnable
UINT8 ProcTraceEnable
Offset 0x07C9 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; ...
Definition: FspsUpd.h:2440
FSP_S_CONFIG::FastPkgCRampDisableGt
UINT8 FastPkgCRampDisableGt
Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew R...
Definition: FspsUpd.h:733
FSP_S_CONFIG::PchLanLtrEnable
UINT8 PchLanLtrEnable
Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable.
Definition: FspsUpd.h:1156
FSP_S_TEST_CONFIG::PmSupport
UINT8 PmSupport
Offset 0x078D - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS.
Definition: FspsUpd.h:2151
FSP_S_CONFIG::PchSkyCamPortACtleResValue
UINT8 PchSkyCamPortACtleResValue
Offset 0x0309 - Enable SkyCam PortA Ctle Res Value Enable/disable PortA Ctle Res Value.
Definition: FspsUpd.h:870
FSP_S_CONFIG::PchSirqEnable
UINT8 PchSirqEnable
Offset 0x06D8 - Enable Serial IRQ Determines if enable Serial IRQ.
Definition: FspsUpd.h:1762
FSP_S_CONFIG::UnusedUpdSpace12
UINT8 UnusedUpdSpace12
Offset 0x02DE.
Definition: FspsUpd.h:726
CpuConfigFspData.h
FSP CPU Data Config Block.
FSP_S_CONFIG::PchIshI2c0GpioAssign
UINT8 PchIshI2c0GpioAssign
Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1084
FSP_S_TEST_CONFIG::PchPciePort8xhDecodePortIndex
UINT8 PchPciePort8xhDecodePortIndex
Offset 0x0A2D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh De...
Definition: FspsUpd.h:2945
FSP_S_TEST_CONFIG::SataTestMode
UINT8 SataTestMode
Offset 0x0A30 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes.
Definition: FspsUpd.h:2963
FSP_S_TEST_CONFIG::CstateLatencyControl4TimeUnit
UINT8 CstateLatencyControl4TimeUnit
Offset 0x07E4 - TimeUnit for C-State Latency Control4 TimeUnit for C-State Latency Control4;Valid val...
Definition: FspsUpd.h:2610
FSP_S_CONFIG::LogoPtr
UINT32 LogoPtr
Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
Definition: FspsUpd.h:93
FSP_S_CONFIG::DmiAspm
UINT8 DmiAspm
Offset 0x0205 - DMI ASPM 0=Disable, 2(Default)=L1 0:Disable, 2:L1.
Definition: FspsUpd.h:486
FSP_S_TEST_CONFIG::SgxSinitDataFromTpm
UINT8 SgxSinitDataFromTpm
Offset 0x088A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values.
Definition: FspsUpd.h:2823
FSP_S_CONFIG::PchLanK1OffEnable
UINT8 PchLanK1OffEnable
Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management 0: Disable; 1: Enable...
Definition: FspsUpd.h:1162
FSP_S_CONFIG::UnusedUpdSpace1
UINT8 UnusedUpdSpace1
Offset 0x006E.
Definition: FspsUpd.h:240
FSP_S_CONFIG::PchHdaVerbTableEntryNum
UINT8 PchHdaVerbTableEntryNum
Offset 0x008B - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
Definition: FspsUpd.h:291
FSP_S_CONFIG::SataP0T2M
UINT8 SataP0T2M
Offset 0x06EF - Port 0 T2 Multipler Port 0 T2 Multipler.
Definition: FspsUpd.h:1873
FSP_S_TEST_CONFIG::PchSbAccessUnlock
UINT8 PchSbAccessUnlock
Offset 0x0893 - PCH Psf lock bit The PSF registers will be locked before 3rd party code execution...
Definition: FspsUpd.h:2873
FSP_S_CONFIG::PchLockDownSpiEiss
UINT8 PchLockDownSpiEiss
Offset 0x0364 - Enable LOCKDOWN SPI Eiss Enable InSMM.STS (EISS) in SPI.
Definition: FspsUpd.h:1186
FSP_S_CONFIG::PchSkyCamPortACtleEnable
UINT8 PchSkyCamPortACtleEnable
Offset 0x0303 - Enable SkyCam PortA Ctle Enable/disable PortA Ctle.
Definition: FspsUpd.h:838
FSP_S_TEST_CONFIG::Eist
UINT8 Eist
Offset 0x07CD - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Techno...
Definition: FspsUpd.h:2467
FSP_S_CONFIG::SataP0Tinact
UINT8 SataP0Tinact
Offset 0x06F6 - Port 0 Tinactive Port 0 Tinactive.
Definition: FspsUpd.h:1908
FSP_S_CONFIG::PchPmDisableNativePowerButton
UINT8 PchPmDisableNativePowerButton
Offset 0x0656 - PCH Pm Disable Native Power Button Power button native mode disable.
Definition: FspsUpd.h:1514
FSP_S_CONFIG::SataRstIrrtOnly
UINT8 SataRstIrrtOnly
Offset 0x06BA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports...
Definition: FspsUpd.h:1677
FSP_S_TEST_CONFIG::TccOffsetTimeWindowForRatl
UINT32 TccOffsetTimeWindowForRatl
Offset 0x0858 - Tcc Offset Time Window for RATL Package PL4 power limit.
Definition: FspsUpd.h:2717
FSP_S_TEST_CONFIG::PsysPmax
UINT16 PsysPmax
Offset 0x087C - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax.
Definition: FspsUpd.h:2771
FSP_S_CONFIG::PchSkyCamPortBTrimEnable
UINT8 PchSkyCamPortBTrimEnable
Offset 0x0300 - Enable SkyCam PortB Clk Trim Enable/disable PortB Clk Trim.
Definition: FspsUpd.h:820
FSP_S_TEST_CONFIG::ProcHotResponse
UINT8 ProcHotResponse
Offset 0x07D3 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; ...
Definition: FspsUpd.h:2505
FSP_S_CONFIG::PchPmPmeB0S5Dis
UINT8 PchPmPmeB0S5Dis
Offset 0x0639 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed ...
Definition: FspsUpd.h:1402
SI_PCH_DEVICE_INTERRUPT_CONFIG::Function
UINT8 Function
Device function.
Definition: FspsUpd.h:78
FSP_S_CONFIG::CpuConfig
CPU_CONFIG_FSP_DATA CpuConfig
Offset 0x02E8 - Cpu Configuration Cpu Configuration data.
Definition: FspsUpd.h:769
FSP_S_CONFIG::SataRstLedLocate
UINT8 SataRstLedLocate
Offset 0x06B9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to...
Definition: FspsUpd.h:1671
AZALIA_HEADER::Reserved
UINT32 Reserved
Reserved for future use. Must be set to 0.
Definition: FspsUpd.h:52
FSP_S_TEST_CONFIG::PowerLimit2Power
UINT32 PowerLimit2Power
Offset 0x084C - Package Short duration turbo mode power limit Package Short duration turbo mode power...
Definition: FspsUpd.h:2699
FSP_S_CONFIG::PchIshUart1GpioAssign
UINT8 PchIshUart1GpioAssign
Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1078
FSP_S_CONFIG::SataP0T1M
UINT8 SataP0T1M
Offset 0x06EE - Port 0 T1 Multipler Port 0 T1 Multipler.
Definition: FspsUpd.h:1868
FSP_S_CONFIG::PchPmCapsuleResetType
UINT8 PchPmCapsuleResetType
Offset 0x0655 - PCH Pm Capsule Reset Type Deprecated: Determines type of reset issued during UpdateCa...
Definition: FspsUpd.h:1508
FSP_S_CONFIG::PchIshGp4GpioAssign
UINT8 PchIshGp4GpioAssign
Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1126
FSP_S_CONFIG::PchIshSpiGpioAssign
UINT8 PchIshSpiGpioAssign
Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1066
FSP_S_CONFIG::PcieAllowNoLtrIccPllShutdown
UINT8 PcieAllowNoLtrIccPllShutdown
Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown Allows BIOS to control ICC PLL Shutdown by determi...
Definition: FspsUpd.h:1377
AZALIA_HEADER::DeviceId
UINT16 DeviceId
Codec Device ID.
Definition: FspsUpd.h:48
FSP_S_TEST_CONFIG::PowerLimit3
UINT32 PowerLimit3
Offset 0x0850 - Package PL3 power limit Package PL3 power limit.
Definition: FspsUpd.h:2705
FSP_S_CONFIG::PcieDetectTimeoutMs
UINT16 PcieDetectTimeoutMs
Offset 0x0636 - PCIE Rp Detect Timeout Ms Will wait for link to exit Detect state for enabled ports b...
Definition: FspsUpd.h:1389
FSP_S_TEST_CONFIG::DisableVrThermalAlert
UINT8 DisableVrThermalAlert
Offset 0x07D4 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1:...
Definition: FspsUpd.h:2511
FSP_S_CONFIG::PchIshEnable
UINT8 PchIshEnable
Offset 0x0034 - Enable PCH ISH Controller Enable/disable ISH Controller.
Definition: FspsUpd.h:161
FSP_S_CONFIG::GpioIrqRoute
UINT8 GpioIrqRoute
Offset 0x0087 - Select GPIO IRQ Route GPIO IRQ Select.
Definition: FspsUpd.h:270
FSP_S_CONFIG::DmiTS2TW
UINT8 DmiTS2TW
Offset 0x06EC - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width.
Definition: FspsUpd.h:1858
FSP_S_TEST_CONFIG::PcieEnablePort8xhDecode
UINT8 PcieEnablePort8xhDecode
Offset 0x0A2C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh D...
Definition: FspsUpd.h:2940
FSP_S_CONFIG::PchPmSlpSusMinAssert
UINT8 PchPmSlpSusMinAssert
Offset 0x0648 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. ...
Definition: FspsUpd.h:1464
FSP_S_CONFIG::PchSkyCamPortCTrimEnable
UINT8 PchSkyCamPortCTrimEnable
Offset 0x0301 - Enable SkyCam PortC Clk Trim Enable/disable PortC Clk Trim.
Definition: FspsUpd.h:826
FSP_S_CONFIG::PchSkyCamPortBCtleResValue
UINT8 PchSkyCamPortBCtleResValue
Offset 0x030A - Enable SkyCam PortB Ctle Res Value Enable/disable PortB Ctle Res Value.
Definition: FspsUpd.h:875
FSP_S_TEST_CONFIG::PkgCStateDemotion
UINT8 PkgCStateDemotion
Offset 0x07DA - Enable or Disable Package C-State Demotion Enable or Disable Package C-State Demotion...
Definition: FspsUpd.h:2548
FSP_S_TEST_CONFIG::Custom2PowerLimit1
UINT32 Custom2PowerLimit1
Offset 0x0864 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for...
Definition: FspsUpd.h:2735
FSP_S_CONFIG::SerialIoDebugUartNumber
UINT8 SerialIoDebugUartNumber
Offset 0x06D6 - UART Number For Debug Purpose UART number for debug purpose.
Definition: FspsUpd.h:1751
FSP_S_TEST_CONFIG::PchSbiUnlock
UINT8 PchSbiUnlock
Offset 0x0892 - PCH Sbi lock bit This unlock the SBI lock bit to allow SBI after post time...
Definition: FspsUpd.h:2867
FSP_S_CONFIG::PchPmPwrBtnOverridePeriod
UINT8 PchPmPwrBtnOverridePeriod
Offset 0x0653 - PCH Pm Pwr Btn Override Period PCH power button override period.
Definition: FspsUpd.h:1496
FSP_S_TEST_CONFIG::PowerLimit1
UINT32 PowerLimit1
Offset 0x0848 - Package Long duration turbo mode power limit Package Long duration turbo mode power l...
Definition: FspsUpd.h:2693
FSP_S_CONFIG::PchPmSlpS0Enable
UINT8 PchPmSlpS0Enable
Offset 0x0657 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idl...
Definition: FspsUpd.h:1520
FSP_S_CONFIG::PcieComplianceTestMode
UINT8 PcieComplianceTestMode
Offset 0x0635 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance...
Definition: FspsUpd.h:1383
FSP_S_CONFIG::X2ApicOptOut
UINT8 X2ApicOptOut
Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS...
Definition: FspsUpd.h:544
FSP_S_CONFIG::PchSkyCamPortATrimEnable
UINT8 PchSkyCamPortATrimEnable
Offset 0x02FF - Enable SkyCam PortA Clk Trim Enable/disable PortA Clk Trim.
Definition: FspsUpd.h:814
FSP_S_CONFIG::SataP1TDisp
UINT8 SataP1TDisp
Offset 0x06F5 - Port 1 Tdispatch Port 1 Tdispatch.
Definition: FspsUpd.h:1903
FSP_S_TEST_CONFIG::ChapDeviceEnable
UINT8 ChapDeviceEnable
Offset 0x0784 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disable...
Definition: FspsUpd.h:2106
FSP_S_CONFIG::SataP1Tinact
UINT8 SataP1Tinact
Offset 0x06F8 - Port 1 Tinactive Port 1 Tinactive.
Definition: FspsUpd.h:1919
SI_PCH_DEVICE_INTERRUPT_CONFIG::IntX
UINT8 IntX
Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
Definition: FspsUpd.h:79
FSP_S_TEST_CONFIG::EndOfPostMessage
UINT8 EndOfPostMessage
Offset 0x088B - End of Post message Test, Send End of Post message.
Definition: FspsUpd.h:2830
FSP_S_CONFIG::PcieDisableRootPortClockGating
UINT8 PcieDisableRootPortClockGating
Offset 0x0632 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for...
Definition: FspsUpd.h:1364
FSP_S_CONFIG::PchT1Level
UINT16 PchT1Level
Offset 0x06DE - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
Definition: FspsUpd.h:1789
SI_PCH_INT_PIN
SI_PCH_INT_PIN
Refer to the definition of PCH_INT_PIN.
Definition: FspsUpd.h:66
SI_PCH_DEVICE_INTERRUPT_CONFIG::Device
UINT8 Device
Device number.
Definition: FspsUpd.h:77
SI_PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device...
Definition: FspsUpd.h:76
FSP_S_CONFIG::PchPmSlpAMinAssert
UINT8 PchPmSlpAMinAssert
Offset 0x0649 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy.
Definition: FspsUpd.h:1469
FSP_S_TEST_CONFIG::DebugInterfaceEnable
UINT8 DebugInterfaceEnable
Offset 0x07C2 - Enable or Disable processor debug features Enable or Disable processor debug features...
Definition: FspsUpd.h:2406
FSP_S_CONFIG
Fsp S Configuration.
Definition: FspsUpd.h:88
FSP_S_CONFIG::VrPowerDeliveryDesign
UINT32 VrPowerDeliveryDesign
Offset 0x0290 - CPU VR Power Delivery Design Used to communicate the power delivery design capability...
Definition: FspsUpd.h:678
FSP_S_CONFIG::FastPkgCRampDisableIa
UINT8 FastPkgCRampDisableIa
Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew R...
Definition: FspsUpd.h:640
FSP_S_CONFIG::AmtEnabled
UINT8 AmtEnabled
Offset 0x0153 - AMT Switch Enable/Disable.
Definition: FspsUpd.h:410
FSP_S_TEST_CONFIG::SkipPamLock
UINT8 SkipPamLock
Offset 0x0785 - Skip PAM register lock Enable: PAM register will not be locked by RC...
Definition: FspsUpd.h:2113
FSP_S_TEST_CONFIG::VtdDisable
UINT8 VtdDisable
Offset 0x078F - Disable VT-d 0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled) $EN_DIS...
Definition: FspsUpd.h:2163
FSPS_UPD::FspsTestConfig
FSP_S_TEST_CONFIG FspsTestConfig
Offset 0x0780.
Definition: FspsUpd.h:2984
FSP_S_CONFIG::SataRstOptaneMemory
UINT8 SataRstOptaneMemory
Offset 0x0720 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
Definition: FspsUpd.h:1988
FSP_S_TEST_CONFIG::CpuS3ResumeDataSize
UINT16 CpuS3ResumeDataSize
Offset 0x087E - CpuS3ResumeDataSize Size of CPU S3 Resume Data.
Definition: FspsUpd.h:2776
FSP_S_CONFIG::PchStartFramePulse
UINT8 PchStartFramePulse
Offset 0x06DA - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk...
Definition: FspsUpd.h:1773
FSP_S_TEST_CONFIG::RenderStandby
UINT8 RenderStandby
Offset 0x078C - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS.
Definition: FspsUpd.h:2145
FSP_S_CONFIG::PcieRpFunctionSwap
UINT8 PcieRpFunctionSwap
Offset 0x0638 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root...
Definition: FspsUpd.h:1396
FSP_S_CONFIG::PcieEnablePeerMemoryWrite
UINT8 PcieEnablePeerMemoryWrite
Offset 0x0633 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are en...
Definition: FspsUpd.h:1370
FSP_S_CONFIG::PchPort61hEnable
UINT8 PchPort61hEnable
Offset 0x065C - PCH Port 61h Config Enable/Disable Used for the emulation feature for Port61h read...
Definition: FspsUpd.h:1549
FSP_S_CONFIG::UnusedUpdSpace13
UINT8 UnusedUpdSpace13
Offset 0x02E1.
Definition: FspsUpd.h:744
FSP_S_TEST_CONFIG::Custom3PowerLimit1
UINT32 Custom3PowerLimit1
Offset 0x086C - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for...
Definition: FspsUpd.h:2747
FSP_S_CONFIG::SerialIoGpio
UINT8 SerialIoGpio
Offset 0x06CA - Enable Pch Serial IO GPIO Determines if enable Serial IO GPIO.
Definition: FspsUpd.h:1731
FSP_S_CONFIG::SataRstIrrt
UINT8 SataRstIrrt
Offset 0x06B5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology.
Definition: FspsUpd.h:1647
FSP_S_CONFIG::SataRstRaidAlternateId
UINT8 SataRstRaidAlternateId
Offset 0x06B0 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID.
Definition: FspsUpd.h:1617
FSP_S_CONFIG::PchIshI2c1GpioAssign
UINT8 PchIshI2c1GpioAssign
Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1090
FSP_S_TEST_CONFIG::TccActivationOffset
UINT8 TccActivationOffset
Offset 0x07AA - TCC Activation Offset TCC Activation Offset.
Definition: FspsUpd.h:2275
FSP_S_TEST_CONFIG::Custom3ConfigTdpControl
UINT8 Custom3ConfigTdpControl
Offset 0x07B6 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2341
FSP_S_CONFIG::CpuS3ResumeMtrrData
UINT32 CpuS3ResumeMtrrData
Offset 0x02E4 - CpuS3ResumeMtrrData Pointer to CPU S3 Resume MTRR Data.
Definition: FspsUpd.h:764
FSP_S_CONFIG::PchTemperatureHotLevel
UINT16 PchTemperatureHotLevel
Offset 0x0702 - Thermal Device Temperature Decides the temperature.
Definition: FspsUpd.h:1957
FSP_S_CONFIG::SlowSlewRateForSa
UINT8 SlowSlewRateForSa
Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configur...
Definition: FspsUpd.h:661
FSP_S_CONFIG::PchHdaIoBufferVoltage
UINT8 PchHdaIoBufferVoltage
Offset 0x0337 - IO Buffer Voltage I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V.
Definition: FspsUpd.h:959
FSP_S_TEST_CONFIG::CstateLatencyControl0Irtl
UINT16 CstateLatencyControl0Irtl
Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit...
Definition: FspsUpd.h:2661
FSP_S_TEST_CONFIG::DisableProcHotOut
UINT8 DisableProcHotOut
Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# ...
Definition: FspsUpd.h:2499
FSP_S_CONFIG::PchPmMeWakeSts
UINT8 PchPmMeWakeSts
Offset 0x0658 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) re...
Definition: FspsUpd.h:1526
FSP_S_TEST_CONFIG::MlcStreamerPrefetcher
UINT8 MlcStreamerPrefetcher
Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; ...
Definition: FspsUpd.h:2382
FSP_S_CONFIG::SataP0TDisp
UINT8 SataP0TDisp
Offset 0x06F1 - Port 0 Tdispatch Port 0 Tdispatch.
Definition: FspsUpd.h:1883
FSP_S_CONFIG::DefaultSid
UINT16 DefaultSid
Offset 0x0202 - Subsystem Device ID for SA devices Subsystem ID that will be programmed to SA devices...
Definition: FspsUpd.h:474
FSP_S_CONFIG::ScsEmmcHs400Enabled
UINT8 ScsEmmcHs400Enabled
Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode.
Definition: FspsUpd.h:149
FSP_S_TEST_CONFIG::UnusedUpdSpace25
UINT8 UnusedUpdSpace25
Offset 0x07CB.
Definition: FspsUpd.h:2455
FSP_S_CONFIG::CpuS3ResumeMtrrDataSize
UINT16 CpuS3ResumeMtrrDataSize
Offset 0x02F8 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data.
Definition: FspsUpd.h:780
FSP_S_TEST_CONFIG::ThreeStrikeCounterDisable
UINT8 ThreeStrikeCounterDisable
Offset 0x0888 - Set Three Strike Counter Disable False (default): Three Strike counter will be increm...
Definition: FspsUpd.h:2812
FSP_S_TEST_CONFIG::CstateLatencyControl0TimeUnit
UINT8 CstateLatencyControl0TimeUnit
Offset 0x07E0 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid va...
Definition: FspsUpd.h:2586
FSP_S_CONFIG::PchSkyCamPortCDCtleEnable
UINT8 PchSkyCamPortCDCtleEnable
Offset 0x0305 - Enable SkyCam PortCD Ctle Enable/disable PortCD Ctle.
Definition: FspsUpd.h:850
FSP_S_CONFIG::ScsEmmcEnabled
UINT8 ScsEmmcEnabled
Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller.
Definition: FspsUpd.h:143
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FsptUpd.h File Reference

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FsptUpd.h File Reference
#include <FspUpd.h>
Include dependency graph for FsptUpd.h:
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Classes

struct | FSPT_CORE_UPD
Fsp T Core UPD. More...
struct | FSP_T_CONFIG
Fsp T Configuration. More...
struct | FSPT_UPD
Fsp T UPD Configuration. More...

Detailed Description

Copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FsptUpd.h.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FsptUpd.h Source File

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FsptUpd.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
5
6 Redistribution and use in source and binary forms, with or without modification,
7 are permitted provided that the following conditions are met:
8
9 * Redistributions of source code must retain the above copyright notice, this
10 list of conditions and the following disclaimer.
11 * Redistributions in binary form must reproduce the above copyright notice, this
12 list of conditions and the following disclaimer in the documentation and/or
13 other materials provided with the distribution.
14 * Neither the name of Intel Corporation nor the names of its contributors may
15 be used to endorse or promote products derived from this software without
16 specific prior written permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 THE POSSIBILITY OF SUCH DAMAGE.
29
30 This file is automatically generated. Please do NOT modify !!!
31
32 **/
33
34 #ifndef __FSPTUPD_H__
35 #define __FSPTUPD_H__
36
37 #include <FspUpd.h>
38
39 #pragma pack(1)
40
41
42 /** Fsp T Core UPD
43 **/
44 typedef struct {
45
46 /** Offset 0x0020
47 **/
48 UINT32 MicrocodeRegionBase;
49
50 /** Offset 0x0024
51 **/
52 UINT32 MicrocodeRegionSize;
53
54 /** Offset 0x0028
55 **/
56 UINT32 CodeRegionBase;
57
58 /** Offset 0x002C
59 **/
60 UINT32 CodeRegionSize;
61
62 /** Offset 0x0030
63 **/
64 UINT8 Reserved[16];
65 } FSPT_CORE_UPD;
66
67 /** Fsp T Configuration
68 **/
69 typedef struct {
70
71 /** Offset 0x0040 - PcdSerialIoUartDebugEnable
72 Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
73 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
74 **/
75 UINT8 PcdSerialIoUartDebugEnable;
76
77 /** Offset 0x0041 - PcdSerialIoUartNumber
78 Select SerialIo Uart Controller for debug.
79 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
80 **/
81 UINT8 PcdSerialIoUartNumber;
82
83 /** Offset 0x0042
84 **/
85 UINT8 UnusedUpdSpace0[2];
86
87 /** Offset 0x0044
88 **/
89 UINT32 PcdSerialIoUartInputClock;
90
91 /** Offset 0x0048 - Pci Express Base Address
92 Base address to be programmed for Pci Express
93 **/
94 UINT64 PcdPciExpressBaseAddress;
95
96 /** Offset 0x0050 - Pci Express Region Length
97 Region Length to be programmed for Pci Express
98 **/
99 UINT32 PcdPciExpressRegionLength;
100
101 /** Offset 0x0054
102 **/
103 UINT8 ReservedFsptUpd1[12];
104 } FSP_T_CONFIG;
105
106 /** Fsp T UPD Configuration
107 **/
108 typedef struct {
109
110 /** Offset 0x0000
111 **/
112 FSP_UPD_HEADER FspUpdHeader;
113
114 /** Offset 0x0020
115 **/
116 FSPT_CORE_UPD FsptCoreUpd;
117
118 /** Offset 0x0040
119 **/
120 FSP_T_CONFIG FsptConfig;
121
122 /** Offset 0x0060
123 **/
124 UINT8 UnusedUpdSpace1[6];
125
126 /** Offset 0x0066
127 **/
128 UINT16 UpdTerminator;
129 } FSPT_UPD;
130
131 #pragma pack()
132
133 #endif
FSPT_CORE_UPD::CodeRegionBase
UINT32 CodeRegionBase
Offset 0x0028.
Definition: FsptUpd.h:56
FSPT_UPD::FsptCoreUpd
FSPT_CORE_UPD FsptCoreUpd
Offset 0x0020.
Definition: FsptUpd.h:116
FSPT_UPD::FsptConfig
FSP_T_CONFIG FsptConfig
Offset 0x0040.
Definition: FsptUpd.h:120
FSP_T_CONFIG::PcdPciExpressRegionLength
UINT32 PcdPciExpressRegionLength
Offset 0x0050 - Pci Express Region Length Region Length to be programmed for Pci Express.
Definition: FsptUpd.h:99
FSP_T_CONFIG::PcdSerialIoUartDebugEnable
UINT8 PcdSerialIoUartDebugEnable
Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializi...
Definition: FsptUpd.h:75
FSPT_CORE_UPD::CodeRegionSize
UINT32 CodeRegionSize
Offset 0x002C.
Definition: FsptUpd.h:60
FspUpd.h
FSP_T_CONFIG::PcdPciExpressBaseAddress
UINT64 PcdPciExpressBaseAddress
Offset 0x0048 - Pci Express Base Address Base address to be programmed for Pci Express.
Definition: FsptUpd.h:94
FSP_T_CONFIG::PcdSerialIoUartNumber
UINT8 PcdSerialIoUartNumber
Offset 0x0041 - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug.
Definition: FsptUpd.h:81
FSPT_UPD::UpdTerminator
UINT16 UpdTerminator
Offset 0x0066.
Definition: FsptUpd.h:128
FSPT_UPD
Fsp T UPD Configuration.
Definition: FsptUpd.h:108
FSP_T_CONFIG::PcdSerialIoUartInputClock
UINT32 PcdSerialIoUartInputClock
Offset 0x0044.
Definition: FsptUpd.h:89
FSPT_UPD::FspUpdHeader
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FsptUpd.h:112
FSPT_CORE_UPD::MicrocodeRegionSize
UINT32 MicrocodeRegionSize
Offset 0x0024.
Definition: FsptUpd.h:52
FSP_T_CONFIG
Fsp T Configuration.
Definition: FsptUpd.h:69
FSPT_CORE_UPD::MicrocodeRegionBase
UINT32 MicrocodeRegionBase
Offset 0x0020.
Definition: FsptUpd.h:48
FSPT_CORE_UPD
Fsp T Core UPD.
Definition: FsptUpd.h:44
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FspUpd.h File Reference

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FspUpd.h File Reference
#include <FspEas.h>
Include dependency graph for FspUpd.h:
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Detailed Description

Copyright
Copyright (c) 2018, Intel Corporation. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FspUpd.h.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: FspUpd.h Source File

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FspUpd.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
5
6 Redistribution and use in source and binary forms, with or without modification,
7 are permitted provided that the following conditions are met:
8
9 * Redistributions of source code must retain the above copyright notice, this
10 list of conditions and the following disclaimer.
11 * Redistributions in binary form must reproduce the above copyright notice, this
12 list of conditions and the following disclaimer in the documentation and/or
13 other materials provided with the distribution.
14 * Neither the name of Intel Corporation nor the names of its contributors may
15 be used to endorse or promote products derived from this software without
16 specific prior written permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 THE POSSIBILITY OF SUCH DAMAGE.
29
30 This file is automatically generated. Please do NOT modify !!!
31
32 **/
33
34 #ifndef __FSPUPD_H__
35 #define __FSPUPD_H__
36
37 #include <FspEas.h>
38
39 #pragma pack(1)
40
41 #define FSPT_UPD_SIGNATURE 0x545F4450554C424B /* 'KBLUPD_T' */
42
43 #define FSPM_UPD_SIGNATURE 0x4D5F4450554C424B /* 'KBLUPD_M' */
44
45 #define FSPS_UPD_SIGNATURE 0x535F4450554C424B /* 'KBLUPD_S' */
46
47 #pragma pack()
48
49 #endif
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: GpioConfig.h File Reference

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Classes | Macros | Typedefs | Enumerations
GpioConfig.h File Reference

Header file for GpioConfig structure used by GPIO library. More...

Go to the source code of this file.

Classes

struct GPIO_CONFIG
GPIO configuration structure used for pin programming. More...

Macros

#define | B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F
Mask for GPIO_INT_CONFIG for interrupt source.
#define | B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0
Mask for GPIO_INT_CONFIG for interrupt type.
#define | B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F
Mask for GPIO_ELECTRICAL_CONFIG for termination value.
#define | B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60
Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting.
#define | B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3
Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock.
#define | B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5
Mask for GPIO_LOCK_CONFIG for Pad Output Lock.
#define | B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3
Mask for GPIO_OTHER_CONFIG for RxRaw1 setting.

Typedefs

typedef UINT32 | GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
typedef UINT32 | GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.

Enumerations

enum | GPIO_HARDWARE_DEFAULT
enum | GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad. More...
enum | GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers. More...
enum | GPIO_DIRECTION
GPIO Direction. More...
enum | GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled. More...
enum | GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled. More...
enum | GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings. More...
enum | GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8. More...
enum | GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock. More...
enum | GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings: More...

Detailed Description

Header file for GpioConfig structure used by GPIO library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioConfig.h.

Enumeration Type Documentation

enum GPIO_DIRECTION

GPIO Direction.

Enumerator
GpioDirDefault | Leave pad direction setting unmodified.
GpioDirInOut | Set pad for both output and input.
GpioDirInInvOut | Set pad for both output and input with inversion.
GpioDirIn | Set pad for input only.
GpioDirInInv | Set pad for input with inversion.
GpioDirOut | Set pad for output only.
GpioDirNone | Disable both output and input.

Definition at line 167 of file GpioConfig.h.

enum GPIO_ELECTRICAL_CONFIG

GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.

Enumerator
GpioTermDefault | Leave termination setting unmodified.
GpioTermNone | none
GpioTermWpd5K | 5kOhm weak pull-down
GpioTermWpd20K | 20kOhm weak pull-down
GpioTermWpu1K | 1kOhm weak pull-up
GpioTermWpu2K | 2kOhm weak pull-up
GpioTermWpu5K | 5kOhm weak pull-up
GpioTermWpu20K | 20kOhm weak pull-up
GpioTermWpu1K2K | 1kOhm & 2kOhm weak pull-up
GpioTermNative | Native function controls pads termination This setting is applicable only to some native modes. Please check EDS to determine which native functionality can control pads termination
GpioNoTolerance1v8 | Disable 1.8V pad tolerance.
GpioTolerance1v8 | Enable 1.8V pad tolerance.

Definition at line 296 of file GpioConfig.h.

enum GPIO_HARDWARE_DEFAULT
Enumerator
GpioHardwareDefault

Leave setting unmodified.

Definition at line 118 of file GpioConfig.h.

enum GPIO_HOSTSW_OWN

Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.

Depending on chosen ownership some GPIO Interrupt status register get updated and other masked. Please refer to EDS for HOSTSW_OWN register description.

Enumerator
GpioHostOwnDefault | Leave ownership value unmodified.
GpioHostOwnAcpi | Set HOST ownership to ACPI. Use this setting if pad is not going to be used by GPIO OS driver. If GPIO is configured to generate SCI/SMI/NMI then this setting must be used for interrupts to work
GpioHostOwnGpio | Set HOST ownership to GPIO Driver mode. Use this setting only if GPIO pad should be controlled by GPIO OS Driver. GPIO OS Driver will be able to control the pad if appropriate entry in ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)

Definition at line 146 of file GpioConfig.h.

enum GPIO_INT_CONFIG

GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled.

GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in EDS for details on this settings. Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge to describe an interrupt e.g. GpioIntApic | GpioIntLevel If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. Not all GPIO are capable of generating an SMI or NMI interrupt. When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this interrupt cannot be shared and its IRQn number is not configurable. Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). This type of GPIO Driver interrupt doesn't have any additional routing setting required to be set by BIOS. Interrupt is handled by GPIO OS Driver.

Enumerator
GpioIntDefault | Leave value of interrupt routing unmodified.
GpioIntDis | Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
GpioIntNmi | Enable NMI interrupt only.
GpioIntSmi | Enable SMI interrupt only.
GpioIntSci | Enable SCI interrupt only.
GpioIntApic | Enable IOxAPIC interrupt only.
GpioIntLevel | Set interrupt as level triggered.
GpioIntEdge | Set interrupt as edge triggered (type of edge depends on input inversion)
GpioIntLvlEdgDis | Disable interrupt trigger.
GpioIntBothEdge | Set interrupt as both edge triggered.

Definition at line 207 of file GpioConfig.h.

enum GPIO_LOCK_CONFIG

GPIO LockConfiguration Set GPIO configuration lock and output state lock.

GpioLockPadConfig and GpioLockOutputState can be OR'ed. Lock settings reset is in Powergood domain. Care must be taken when using this setting as fields it locks may be reset by a different signal and can be controllable by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides functions which allow to unlock a GPIO pad.

Enumerator
GpioLockDefault | Leave lock setting unmodified.
GpioPadConfigLock | Lock Pad Configuration.
GpioOutputStateLock | Lock GPIO pad output value.

Definition at line 329 of file GpioConfig.h.

enum GPIO_OTHER_CONFIG

Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings:

  • RX raw override to '1' - allows to override input value to '1' This setting is applicable only if in input mode (both in GPIO and native usage). The override takes place at the internal pad state directly from buffer and before the RXINV.
Enumerator
GpioRxRaw1Default | Use default input override value.
GpioRxRaw1Dis | Don't override input.
GpioRxRaw1En | Override input to '1'.

Definition at line 346 of file GpioConfig.h.

enum GPIO_OUTPUT_STATE

GPIO Output State This field is relevant only if output is enabled.

Enumerator
GpioOutDefault | Leave output value unmodified.
GpioOutLow | Set output to low.
GpioOutHigh | Set output to high.

Definition at line 181 of file GpioConfig.h.

enum GPIO_PAD_MODE

GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.

If GPIO is set to one of NativeX modes then following settings are not applicable and can be skipped:

  • Interrupt related settings
  • Host Software Ownership
  • Output/Input enabling/disabling
  • Output lock

Definition at line 132 of file GpioConfig.h.

enum GPIO_RESET_CONFIG

GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings.

Refer to EDS for settings that are controllable by PadRstCfg.

Enumerator
GpioResetDefault

Leave value of pad reset unmodified.

GpioResetPwrGood

Deprecated settings.

Maintained only for compatibility.GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")

GpioResetDeep

Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")

GpioResetNormal

GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )

GpioResetResume

GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )

GpioResumeReset

New GPIO reset configuration options.

Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad setting will reset on:

  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
GpioHostDeepReset

Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:

  • Warm/Cold/Global reset
  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
GpioPlatformReset

Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:

  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition
  • G3
GpioDswReset

Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings will reset on:

  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition

Definition at line 229 of file GpioConfig.h.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: GpioConfig.h Source File

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GpioConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for GpioConfig structure used by GPIO library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GPIO_CONFIG_H_
36 #define _GPIO_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 ///
41 /// For any GpioPad usage in code use GPIO_PAD type
42 ///
43 typedef UINT32 GPIO_PAD;
44
45
46 ///
47 /// For any GpioGroup usage in code use GPIO_GROUP type
48 ///
49 typedef UINT32 GPIO_GROUP;
50
51 /**
52 GPIO configuration structure used for pin programming.
53 Structure contains fields that can be used to configure pad.
54 **/
55 typedef struct {
56 /**
57 Pad Mode
58 Pad can be set as GPIO or one of its native functions.
59 When in native mode setting Direction (except Inversion), OutputState,
60 InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
61 Refer to definition of GPIO_PAD_MODE.
62 Refer to EDS for each native mode according to the pad.
63 **/
64 UINT32 PadMode : 5;
65 /**
66 Host Software Pad Ownership
67 Set pad to ACPI mode or GPIO Driver Mode.
68 Refer to definition of GPIO_HOSTSW_OWN.
69 **/
70 UINT32 HostSoftPadOwn : 2;
71 /**
72 GPIO Direction
73 Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
74 Refer to definition of GPIO_DIRECTION for supported settings.
75 **/
76 UINT32 Direction : 6;
77 /**
78 Output State
79 Set Pad output value.
80 Refer to definition of GPIO_OUTPUT_STATE for supported settings.
81 This setting takes place when output is enabled.
82 **/
83 UINT32 OutputState : 2;
84 /**
85 GPIO Interrupt Configuration
86 Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
87 This setting is applicable only if GPIO is in GpioMode with input enabled.
88 Refer to definition of GPIO_INT_CONFIG for supported settings.
89 **/
90 UINT32 InterruptConfig : 9;
91 /**
92 GPIO Power Configuration.
93 This setting controls Pad Reset Configuration.
94 Refer to definition of GPIO_RESET_CONFIG for supported settings.
95 **/
96 UINT32 PowerConfig : 8;
97 /**
98 GPIO Electrical Configuration
99 This setting controls pads termination and voltage tolerance.
100 Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
101 **/
102 UINT32 ElectricalConfig : 9;
103 /**
104 GPIO Lock Configuration
105 This setting controls pads lock.
106 Refer to definition of GPIO_LOCK_CONFIG for supported settings.
107 **/
108 UINT32 LockConfig : 4;
109 /**
110 Additional GPIO configuration
111 Refer to definition of GPIO_OTHER_CONFIG for supported settings.
112 **/
113 UINT32 OtherSettings : 2;
114 UINT32 RsvdBits : 17; ///< Reserved bits for future extension
115 } GPIO_CONFIG;
116
117
118 typedef enum {
119 GpioHardwareDefault = 0x0 ///< Leave setting unmodified
120 } GPIO_HARDWARE_DEFAULT;
121
122 /**
123 GPIO Pad Mode
124 Refer to GPIO documentation on native functions available for certain pad.
125 If GPIO is set to one of NativeX modes then following settings are not applicable
126 and can be skipped:
127 - Interrupt related settings
128 - Host Software Ownership
129 - Output/Input enabling/disabling
130 - Output lock
131 **/
132 typedef enum {
133 GpioPadModeGpio = 0x1,
134 GpioPadModeNative1 = 0x3,
135 GpioPadModeNative2 = 0x5,
136 GpioPadModeNative3 = 0x7,
137 GpioPadModeNative4 = 0x9
138 } GPIO_PAD_MODE;
139
140 /**
141 Host Software Pad Ownership modes
142 This setting affects GPIO interrupt status registers. Depending on chosen ownership
143 some GPIO Interrupt status register get updated and other masked.
144 Please refer to EDS for HOSTSW_OWN register description.
145 **/
146 typedef enum {
147 GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
148 /**
149 Set HOST ownership to ACPI.
150 Use this setting if pad is not going to be used by GPIO OS driver.
151 If GPIO is configured to generate SCI/SMI/NMI then this setting must be
152 used for interrupts to work
153 **/
154 GpioHostOwnAcpi = 0x1,
155 /**
156 Set HOST ownership to GPIO Driver mode.
157 Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
158 GPIO OS Driver will be able to control the pad if appropriate entry in
159 ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
160 **/
161 GpioHostOwnGpio = 0x3
162 } GPIO_HOSTSW_OWN;
163
164 ///
165 /// GPIO Direction
166 ///
167 typedef enum {
168 GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
169 GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
170 GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
171 GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
172 GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
173 GpioDirOut = 0x5, ///< Set pad for output only
174 GpioDirNone = 0x7 ///< Disable both output and input
175 } GPIO_DIRECTION;
176
177 /**
178 GPIO Output State
179 This field is relevant only if output is enabled
180 **/
181 typedef enum {
182 GpioOutDefault = 0x0, ///< Leave output value unmodified
183 GpioOutLow = 0x1, ///< Set output to low
184 GpioOutHigh = 0x3 ///< Set output to high
185 } GPIO_OUTPUT_STATE;
186
187 /**
188 GPIO interrupt configuration
189 This setting is applicable only if pad is in GPIO mode and has input enabled.
190 GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
191 and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
192 EDS for details on this settings.
193 Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
194 to describe an interrupt e.g. GpioIntApic | GpioIntLevel
195 If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
196 If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
197 Not all GPIO are capable of generating an SMI or NMI interrupt.
198 When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
199 interrupt cannot be shared and its IRQn number is not configurable.
200 Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
201 If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
202 exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
203 This type of GPIO Driver interrupt doesn't have any additional routing setting
204 required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
205 **/
206
207 typedef enum {
208 GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
209 GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
210 GpioIntNmi = 0x3, ///< Enable NMI interrupt only
211 GpioIntSmi = 0x5, ///< Enable SMI interrupt only
212 GpioIntSci = 0x9, ///< Enable SCI interrupt only
213 GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
214 GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
215 GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
216 GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
217 GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
218 } GPIO_INT_CONFIG;
219
220 #define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
221 #define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
222
223 /**
224 GPIO Power Configuration
225 GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
226 be used to reset certain GPIO settings.
227 Refer to EDS for settings that are controllable by PadRstCfg.
228 **/
229 typedef enum {
230
231
232 GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
233 ///
234 /// Deprecated settings. Maintained only for compatibility.
235 ///
236 GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
237 GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
238 GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
239 GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
240
241 ///
242 /// New GPIO reset configuration options
243 ///
244 /**
245 Resume Reset (RSMRST)
246 GPP: PadRstCfg = 00b = "Powergood"
247 GPD: PadRstCfg = 11b = "Resume Reset"
248 Pad setting will reset on:
249 - DeepSx transition
250 - G3
251 Pad settings will not reset on:
252 - S3/S4/S5 transition
253 - Warm/Cold/Global reset
254 **/
255 GpioResumeReset = 0x01,
256 /**
257 Host Deep Reset
258 PadRstCfg = 01b = "Deep GPIO Reset"
259 Pad settings will reset on:
260 - Warm/Cold/Global reset
261 - DeepSx transition
262 - G3
263 Pad settings will not reset on:
264 - S3/S4/S5 transition
265 **/
266 GpioHostDeepReset = 0x03,
267 /**
268 Platform Reset (PLTRST)
269 PadRstCfg = 10b = "GPIO Reset"
270 Pad settings will reset on:
271 - S3/S4/S5 transition
272 - Warm/Cold/Global reset
273 - DeepSx transition
274 - G3
275 **/
276 GpioPlatformReset = 0x05,
277 /**
278 Deep Sleep Well Reset (DSW_PWROK)
279 GPP: not applicable
280 GPD: PadRstCfg = 00b = "Powergood"
281 Pad settings will reset on:
282 - G3
283 Pad settings will not reset on:
284 - S3/S4/S5 transition
285 - Warm/Cold/Global reset
286 - DeepSx transition
287 **/
288 GpioDswReset = 0x07
289 } GPIO_RESET_CONFIG;
290
291 /**
292 GPIO Electrical Configuration
293 Set GPIO termination and Pad Tolerance (applicable only for some pads)
294 Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
295 **/
296 typedef enum {
297 GpioTermDefault = 0x0, ///< Leave termination setting unmodified
298 GpioTermNone = 0x1, ///< none
299 GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
300 GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
301 GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
302 GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
303 GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
304 GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
305 GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
306 /**
307 Native function controls pads termination
308 This setting is applicable only to some native modes.
309 Please check EDS to determine which native functionality
310 can control pads termination
311 **/
312 GpioTermNative = 0x1F,
313 GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
314 GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
315 } GPIO_ELECTRICAL_CONFIG;
316
317 #define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
318 #define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
319
320 /**
321 GPIO LockConfiguration
322 Set GPIO configuration lock and output state lock.
323 GpioLockPadConfig and GpioLockOutputState can be OR'ed.
324 Lock settings reset is in Powergood domain. Care must be taken when using this setting
325 as fields it locks may be reset by a different signal and can be controllable
326 by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
327 functions which allow to unlock a GPIO pad.
328 **/
329 typedef enum {
330 GpioLockDefault = 0x0, ///< Leave lock setting unmodified
331 GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
332 GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
333 } GPIO_LOCK_CONFIG;
334
335 #define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
336 #define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
337
338 /**
339 Other GPIO Configuration
340 GPIO_OTHER_CONFIG is used for less often settings and for future extensions
341 Supported settings:
342 - RX raw override to '1' - allows to override input value to '1'
343 This setting is applicable only if in input mode (both in GPIO and native usage).
344 The override takes place at the internal pad state directly from buffer and before the RXINV.
345 **/
346 typedef enum {
347 GpioRxRaw1Default = 0x0, ///< Use default input override value
348 GpioRxRaw1Dis = 0x1, ///< Don't override input
349 GpioRxRaw1En = 0x3 ///< Override input to '1'
350 } GPIO_OTHER_CONFIG;
351
352 #define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
353
354 #pragma pack(pop)
355
356 #endif //_GPIO_CONFIG_H_
GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:300
GpioResetDefault
Leave value of pad reset unmodified.
Definition: GpioConfig.h:232
GPIO_RESET_CONFIG
GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings.
Definition: GpioConfig.h:229
GpioOutputStateLock
Lock GPIO pad output value.
Definition: GpioConfig.h:332
GPIO_OUTPUT_STATE
GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled.
Definition: GpioConfig.h:181
GPIO_CONFIG
GPIO configuration structure used for pin programming.
Definition: GpioConfig.h:55
GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:213
GpioRxRaw1Dis
Don't override input.
Definition: GpioConfig.h:348
GpioTolerance1v8
Enable 1.8V pad tolerance.
Definition: GpioConfig.h:314
GPIO_HARDWARE_DEFAULT
GPIO_HARDWARE_DEFAULT
Definition: GpioConfig.h:118
GpioNoTolerance1v8
Disable 1.8V pad tolerance.
Definition: GpioConfig.h:313
GpioTermWpd5K
5kOhm weak pull-down
Definition: GpioConfig.h:299
GpioOutLow
Set output to low.
Definition: GpioConfig.h:183
GpioTermDefault
Leave termination setting unmodified.
Definition: GpioConfig.h:297
GPIO_DIRECTION
GPIO_DIRECTION
GPIO Direction.
Definition: GpioConfig.h:167
GpioDirInInvOut
Set pad for both output and input with inversion.
Definition: GpioConfig.h:170
GpioHardwareDefault
Leave setting unmodified.
Definition: GpioConfig.h:119
GpioLockDefault
Leave lock setting unmodified.
Definition: GpioConfig.h:330
GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:288
GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:173
GpioIntDefault
Leave value of interrupt routing unmodified.
Definition: GpioConfig.h:208
GpioTermWpu2K
2kOhm weak pull-up
Definition: GpioConfig.h:302
GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:154
GpioTermNative
Native function controls pads termination This setting is applicable only to some native modes...
Definition: GpioConfig.h:312
GpioResetPwrGood
Deprecated settings.
Definition: GpioConfig.h:236
GPIO_OTHER_CONFIG
GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions ...
Definition: GpioConfig.h:346
GpioResetDeep
Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
Definition: GpioConfig.h:237
GpioDirDefault
Leave pad direction setting unmodified.
Definition: GpioConfig.h:168
GPIO_ELECTRICAL_CONFIG
GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) ...
Definition: GpioConfig.h:296
GpioTermWpu1K
1kOhm weak pull-up
Definition: GpioConfig.h:301
GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:209
GpioRxRaw1Default
Use default input override value.
Definition: GpioConfig.h:347
GpioResumeReset
New GPIO reset configuration options.
Definition: GpioConfig.h:255
GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:174
GpioDirInOut
Set pad for both output and input.
Definition: GpioConfig.h:169
GPIO_HOSTSW_OWN
GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.
Definition: GpioConfig.h:146
GPIO_LOCK_CONFIG
GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock.
Definition: GpioConfig.h:329
GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:215
GpioOutHigh
Set output to high.
Definition: GpioConfig.h:184
GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:214
GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:304
GpioPadConfigLock
Lock Pad Configuration.
Definition: GpioConfig.h:331
GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:182
GpioResetResume
GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
Definition: GpioConfig.h:239
GpioIntBothEdge
Set interrupt as both edge triggered.
Definition: GpioConfig.h:217
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:43
GPIO_INT_CONFIG
GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input ena...
Definition: GpioConfig.h:207
GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:172
GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on: ...
Definition: GpioConfig.h:276
GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:171
GpioRxRaw1En
Override input to '1'.
Definition: GpioConfig.h:349
GpioIntNmi
Enable NMI interrupt only.
Definition: GpioConfig.h:210
GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:216
GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:212
GpioTermWpu1K2K
1kOhm & 2kOhm weak pull-up
Definition: GpioConfig.h:305
GpioTermNone
none
Definition: GpioConfig.h:298
GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:161
GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:211
GpioTermWpu5K
5kOhm weak pull-up
Definition: GpioConfig.h:303
GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:266
GPIO_PAD_MODE
GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad...
Definition: GpioConfig.h:132
GpioHostOwnDefault
Leave ownership value unmodified.
Definition: GpioConfig.h:147
GpioResetNormal
GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
Definition: GpioConfig.h:238
GPIO_GROUP
UINT32 GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.
Definition: GpioConfig.h:49
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: GpioSampleDef.h File Reference

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GpioSampleDef.h File Reference
#include <FsptUpd.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
Include dependency graph for GpioSampleDef.h:

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Copyright
Copyright (c) 2015, Intel Corporation. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file GpioSampleDef.h.


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GpioSampleDef.h
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1 /** @file
2 @copyright
3 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31 **/
32
33 #ifndef __GPIOCONFIG_H__
34 #define __GPIOCONFIG_H__
35 #include <FsptUpd.h>
36 #include <FspmUpd.h>
37 #include <FspsUpd.h>
38
39 /*
40 SKL LP GPIO pins
41 Use below for functions from PCH GPIO Lib which
42 require GpioPad as argument. Encoding used here
43 has all information required by library functions
44 */
45 #define GPIO_SKL_LP_GPP_A0 0x02000000
46 #define GPIO_SKL_LP_GPP_A1 0x02000001
47 #define GPIO_SKL_LP_GPP_A2 0x02000002
48 #define GPIO_SKL_LP_GPP_A3 0x02000003
49 #define GPIO_SKL_LP_GPP_A4 0x02000004
50 #define GPIO_SKL_LP_GPP_A5 0x02000005
51 #define GPIO_SKL_LP_GPP_A6 0x02000006
52 #define GPIO_SKL_LP_GPP_A7 0x02000007
53 #define GPIO_SKL_LP_GPP_A8 0x02000008
54 #define GPIO_SKL_LP_GPP_A9 0x02000009
55 #define GPIO_SKL_LP_GPP_A10 0x0200000A
56 #define GPIO_SKL_LP_GPP_A11 0x0200000B
57 #define GPIO_SKL_LP_GPP_A12 0x0200000C
58 #define GPIO_SKL_LP_GPP_A13 0x0200000D
59 #define GPIO_SKL_LP_GPP_A14 0x0200000E
60 #define GPIO_SKL_LP_GPP_A15 0x0200000F
61 #define GPIO_SKL_LP_GPP_A16 0x02000010
62 #define GPIO_SKL_LP_GPP_A17 0x02000011
63 #define GPIO_SKL_LP_GPP_A18 0x02000012
64 #define GPIO_SKL_LP_GPP_A19 0x02000013
65 #define GPIO_SKL_LP_GPP_A20 0x02000014
66 #define GPIO_SKL_LP_GPP_A21 0x02000015
67 #define GPIO_SKL_LP_GPP_A22 0x02000016
68 #define GPIO_SKL_LP_GPP_A23 0x02000017
69 #define GPIO_SKL_LP_GPP_B0 0x02010000
70 #define GPIO_SKL_LP_GPP_B1 0x02010001
71 #define GPIO_SKL_LP_GPP_B2 0x02010002
72 #define GPIO_SKL_LP_GPP_B3 0x02010003
73 #define GPIO_SKL_LP_GPP_B4 0x02010004
74 #define GPIO_SKL_LP_GPP_B5 0x02010005
75 #define GPIO_SKL_LP_GPP_B6 0x02010006
76 #define GPIO_SKL_LP_GPP_B7 0x02010007
77 #define GPIO_SKL_LP_GPP_B8 0x02010008
78 #define GPIO_SKL_LP_GPP_B9 0x02010009
79 #define GPIO_SKL_LP_GPP_B10 0x0201000A
80 #define GPIO_SKL_LP_GPP_B11 0x0201000B
81 #define GPIO_SKL_LP_GPP_B12 0x0201000C
82 #define GPIO_SKL_LP_GPP_B13 0x0201000D
83 #define GPIO_SKL_LP_GPP_B14 0x0201000E
84 #define GPIO_SKL_LP_GPP_B15 0x0201000F
85 #define GPIO_SKL_LP_GPP_B16 0x02010010
86 #define GPIO_SKL_LP_GPP_B17 0x02010011
87 #define GPIO_SKL_LP_GPP_B18 0x02010012
88 #define GPIO_SKL_LP_GPP_B19 0x02010013
89 #define GPIO_SKL_LP_GPP_B20 0x02010014
90 #define GPIO_SKL_LP_GPP_B21 0x02010015
91 #define GPIO_SKL_LP_GPP_B22 0x02010016
92 #define GPIO_SKL_LP_GPP_B23 0x02010017
93 #define GPIO_SKL_LP_GPP_C0 0x02020000
94 #define GPIO_SKL_LP_GPP_C1 0x02020001
95 #define GPIO_SKL_LP_GPP_C2 0x02020002
96 #define GPIO_SKL_LP_GPP_C3 0x02020003
97 #define GPIO_SKL_LP_GPP_C4 0x02020004
98 #define GPIO_SKL_LP_GPP_C5 0x02020005
99 #define GPIO_SKL_LP_GPP_C6 0x02020006
100 #define GPIO_SKL_LP_GPP_C7 0x02020007
101 #define GPIO_SKL_LP_GPP_C8 0x02020008
102 #define GPIO_SKL_LP_GPP_C9 0x02020009
103 #define GPIO_SKL_LP_GPP_C10 0x0202000A
104 #define GPIO_SKL_LP_GPP_C11 0x0202000B
105 #define GPIO_SKL_LP_GPP_C12 0x0202000C
106 #define GPIO_SKL_LP_GPP_C13 0x0202000D
107 #define GPIO_SKL_LP_GPP_C14 0x0202000E
108 #define GPIO_SKL_LP_GPP_C15 0x0202000F
109 #define GPIO_SKL_LP_GPP_C16 0x02020010
110 #define GPIO_SKL_LP_GPP_C17 0x02020011
111 #define GPIO_SKL_LP_GPP_C18 0x02020012
112 #define GPIO_SKL_LP_GPP_C19 0x02020013
113 #define GPIO_SKL_LP_GPP_C20 0x02020014
114 #define GPIO_SKL_LP_GPP_C21 0x02020015
115 #define GPIO_SKL_LP_GPP_C22 0x02020016
116 #define GPIO_SKL_LP_GPP_C23 0x02020017
117 #define GPIO_SKL_LP_GPP_D0 0x02030000
118 #define GPIO_SKL_LP_GPP_D1 0x02030001
119 #define GPIO_SKL_LP_GPP_D2 0x02030002
120 #define GPIO_SKL_LP_GPP_D3 0x02030003
121 #define GPIO_SKL_LP_GPP_D4 0x02030004
122 #define GPIO_SKL_LP_GPP_D5 0x02030005
123 #define GPIO_SKL_LP_GPP_D6 0x02030006
124 #define GPIO_SKL_LP_GPP_D7 0x02030007
125 #define GPIO_SKL_LP_GPP_D8 0x02030008
126 #define GPIO_SKL_LP_GPP_D9 0x02030009
127 #define GPIO_SKL_LP_GPP_D10 0x0203000A
128 #define GPIO_SKL_LP_GPP_D11 0x0203000B
129 #define GPIO_SKL_LP_GPP_D12 0x0203000C
130 #define GPIO_SKL_LP_GPP_D13 0x0203000D
131 #define GPIO_SKL_LP_GPP_D14 0x0203000E
132 #define GPIO_SKL_LP_GPP_D15 0x0203000F
133 #define GPIO_SKL_LP_GPP_D16 0x02030010
134 #define GPIO_SKL_LP_GPP_D17 0x02030011
135 #define GPIO_SKL_LP_GPP_D18 0x02030012
136 #define GPIO_SKL_LP_GPP_D19 0x02030013
137 #define GPIO_SKL_LP_GPP_D20 0x02030014
138 #define GPIO_SKL_LP_GPP_D21 0x02030015
139 #define GPIO_SKL_LP_GPP_D22 0x02030016
140 #define GPIO_SKL_LP_GPP_D23 0x02030017
141 #define GPIO_SKL_LP_GPP_E0 0x02040000
142 #define GPIO_SKL_LP_GPP_E1 0x02040001
143 #define GPIO_SKL_LP_GPP_E2 0x02040002
144 #define GPIO_SKL_LP_GPP_E3 0x02040003
145 #define GPIO_SKL_LP_GPP_E4 0x02040004
146 #define GPIO_SKL_LP_GPP_E5 0x02040005
147 #define GPIO_SKL_LP_GPP_E6 0x02040006
148 #define GPIO_SKL_LP_GPP_E7 0x02040007
149 #define GPIO_SKL_LP_GPP_E8 0x02040008
150 #define GPIO_SKL_LP_GPP_E9 0x02040009
151 #define GPIO_SKL_LP_GPP_E10 0x0204000A
152 #define GPIO_SKL_LP_GPP_E11 0x0204000B
153 #define GPIO_SKL_LP_GPP_E12 0x0204000C
154 #define GPIO_SKL_LP_GPP_E13 0x0204000D
155 #define GPIO_SKL_LP_GPP_E14 0x0204000E
156 #define GPIO_SKL_LP_GPP_E15 0x0204000F
157 #define GPIO_SKL_LP_GPP_E16 0x02040010
158 #define GPIO_SKL_LP_GPP_E17 0x02040011
159 #define GPIO_SKL_LP_GPP_E18 0x02040012
160 #define GPIO_SKL_LP_GPP_E19 0x02040013
161 #define GPIO_SKL_LP_GPP_E20 0x02040014
162 #define GPIO_SKL_LP_GPP_E21 0x02040015
163 #define GPIO_SKL_LP_GPP_E22 0x02040016
164 #define GPIO_SKL_LP_GPP_E23 0x02040017
165 #define GPIO_SKL_LP_GPP_F0 0x02050000
166 #define GPIO_SKL_LP_GPP_F1 0x02050001
167 #define GPIO_SKL_LP_GPP_F2 0x02050002
168 #define GPIO_SKL_LP_GPP_F3 0x02050003
169 #define GPIO_SKL_LP_GPP_F4 0x02050004
170 #define GPIO_SKL_LP_GPP_F5 0x02050005
171 #define GPIO_SKL_LP_GPP_F6 0x02050006
172 #define GPIO_SKL_LP_GPP_F7 0x02050007
173 #define GPIO_SKL_LP_GPP_F8 0x02050008
174 #define GPIO_SKL_LP_GPP_F9 0x02050009
175 #define GPIO_SKL_LP_GPP_F10 0x0205000A
176 #define GPIO_SKL_LP_GPP_F11 0x0205000B
177 #define GPIO_SKL_LP_GPP_F12 0x0205000C
178 #define GPIO_SKL_LP_GPP_F13 0x0205000D
179 #define GPIO_SKL_LP_GPP_F14 0x0205000E
180 #define GPIO_SKL_LP_GPP_F15 0x0205000F
181 #define GPIO_SKL_LP_GPP_F16 0x02050010
182 #define GPIO_SKL_LP_GPP_F17 0x02050011
183 #define GPIO_SKL_LP_GPP_F18 0x02050012
184 #define GPIO_SKL_LP_GPP_F19 0x02050013
185 #define GPIO_SKL_LP_GPP_F20 0x02050014
186 #define GPIO_SKL_LP_GPP_F21 0x02050015
187 #define GPIO_SKL_LP_GPP_F22 0x02050016
188 #define GPIO_SKL_LP_GPP_F23 0x02050017
189 #define GPIO_SKL_LP_GPP_G0 0x02060000
190 #define GPIO_SKL_LP_GPP_G1 0x02060001
191 #define GPIO_SKL_LP_GPP_G2 0x02060002
192 #define GPIO_SKL_LP_GPP_G3 0x02060003
193 #define GPIO_SKL_LP_GPP_G4 0x02060004
194 #define GPIO_SKL_LP_GPP_G5 0x02060005
195 #define GPIO_SKL_LP_GPP_G6 0x02060006
196 #define GPIO_SKL_LP_GPP_G7 0x02060007
197 #define GPIO_SKL_LP_GPD0 0x02070000
198 #define GPIO_SKL_LP_GPD1 0x02070001
199 #define GPIO_SKL_LP_GPD2 0x02070002
200 #define GPIO_SKL_LP_GPD3 0x02070003
201 #define GPIO_SKL_LP_GPD4 0x02070004
202 #define GPIO_SKL_LP_GPD5 0x02070005
203 #define GPIO_SKL_LP_GPD6 0x02070006
204 #define GPIO_SKL_LP_GPD7 0x02070007
205 #define GPIO_SKL_LP_GPD8 0x02070008
206 #define GPIO_SKL_LP_GPD9 0x02070009
207 #define GPIO_SKL_LP_GPD10 0x0207000A
208 #define GPIO_SKL_LP_GPD11 0x0207000B
209
210 #define END_OF_GPIO_TABLE 0xFFFFFFFF
211
212 //Sample GPIO Table
213
214 static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
215 {
216 //skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
217 //skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
218 //skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
219 //skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
220 //skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
221 //skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
222 //skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
223 //skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
224 {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
225 //skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
226 {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
227 {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
228 {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
229 {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
230 //skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
231 {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
232 {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
233 {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
234 {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
235 {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
236 {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
237 {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
238 {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
239 {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
240 {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
241 {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
242 {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
243 {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
244 {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
245 {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
246 // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
247 // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
248 // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
249 // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
250 // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
251 {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
252 {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
253 {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
254 {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
255 {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
256 {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
257 {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
258 {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
259 {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
260 {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
261 {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
262 {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
263 {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
264 {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
265 {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
266 {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
267 {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
268 {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
269 {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
270 {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
271 {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
272 {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
273 {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
274 {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
275 {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
276 {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
277 {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
278 {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
279 {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
280 {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
281 {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
282 {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
283 {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
284 {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
285 {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
286 {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
287 {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
288 {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
289 {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
290 {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
291 {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
292 {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
293 {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
294 {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
295 {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
296 {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
297 {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
298 {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
299 {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
300 {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
301 {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
302 {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
303 {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
304 {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
305 {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
306 {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_1
307 {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
308 {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_DATA_0
309 {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
310 {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
311 {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
312 {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
313 {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
314 {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
315 {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
316 {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
317 {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
318 {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
319 {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
320 {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
321 {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
322 {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
323 {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
324 {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
325 {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
326 {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
327 {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
328 {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
329 {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
330 {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
331 {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
332 {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
333 {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
334 {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
335 {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
336 {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
337 {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
338 {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
339 {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
340 {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
341 {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
342 {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
343 {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
344 {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
345 {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
346 {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
347 {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
348 {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
349 {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
350 {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
351 {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
352 {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
353 {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
354 {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
355 {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
356 {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
357 {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
358 {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
359 {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
360 {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
361 {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
362 {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
363 {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
364 {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
365 {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
366 {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
367 {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
368 {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
369 {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
370 {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
371 {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
372 {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
373 {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
374 {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
375 {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
376 {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
377 {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
378 {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
379 {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
380 };
381
382 #endif //_GPIO_CONFIG_H_
GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:300
GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:213
GpioTolerance1v8
Enable 1.8V pad tolerance.
Definition: GpioConfig.h:314
GpioOutLow
Set output to low.
Definition: GpioConfig.h:183
GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:288
GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:173
GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:154
FspsUpd.h
GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:209
GpioResumeReset
New GPIO reset configuration options.
Definition: GpioConfig.h:255
GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:174
GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:215
GpioOutHigh
Set output to high.
Definition: GpioConfig.h:184
GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:214
GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:304
GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:182
FspmUpd.h
GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:172
FsptUpd.h
GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on: ...
Definition: GpioConfig.h:276
GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:171
GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:216
GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:212
GpioTermNone
none
Definition: GpioConfig.h:298
GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:161
GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:211
GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:266
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: MemInfoHob.h File Reference

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MemInfoHob.h File Reference

This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs. More...

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Classes

struct | DIMM_INFO
Memory SMBIOS & OC Memory Data Hob. More...
struct | MEMORY_PLATFORM_DATA
Memory Platform Data Hob. More...

Macros

#define | WARM_BOOT 2
Host reset states from MRC.
#define | MAX_SPD_SAVE 29
Defines taken from MRC so avoid having to include MrcInterface.h.

Detailed Description

This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MemInfoHob.h.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: MemInfoHob.h Source File

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MemInfoHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions required for creation of
3 Memory S3 Save data, Memory Info data and Memory Platform
4 data hobs.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 1999 - 2018 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
31 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
32 the terms of your license agreement with Intel or your vendor. This file may
33 be modified by the user, subject to additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37 #ifndef _MEM_INFO_HOB_H_
38 #define _MEM_INFO_HOB_H_
39
40 #pragma pack (push, 1)
41
42 extern EFI_GUID gSiMemoryS3DataGuid;
43 extern EFI_GUID gSiMemoryInfoDataGuid;
44 extern EFI_GUID gSiMemoryPlatformDataGuid;
45
46 #define MAX_NODE 1
47 #define MAX_CH 2
48 #define MAX_DIMM 2
49
50 ///
51 /// Host reset states from MRC.
52 ///
53 #define WARM_BOOT 2
54
55 #define R_MC_CHNL_RANK_PRESENT 0x7C
56 #define B_RANK0_PRS BIT0
57 #define B_RANK1_PRS BIT1
58 #define B_RANK2_PRS BIT4
59 #define B_RANK3_PRS BIT5
60
61 // @todo remove and use the MdePkg\Include\Pi\PiHob.h
62 #if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
63 #ifndef __HOB__H__
64 typedef struct _EFI_HOB_GENERIC_HEADER {
65 UINT16 HobType;
66 UINT16 HobLength;
67 UINT32 Reserved;
68 } EFI_HOB_GENERIC_HEADER;
69
70 typedef struct _EFI_HOB_GUID_TYPE {
71 EFI_HOB_GENERIC_HEADER Header;
72 EFI_GUID Name;
73 ///
74 /// Guid specific data goes here
75 ///
76 } EFI_HOB_GUID_TYPE;
77 #endif
78 #endif
79
80 ///
81 /// Defines taken from MRC so avoid having to include MrcInterface.h
82 ///
83
84 //
85 // Matches MAX_SPD_SAVE define in MRC
86 //
87 #ifndef MAX_SPD_SAVE
88 #define MAX_SPD_SAVE 29
89 #endif
90
91 //
92 // MRC version description.
93 //
94 typedef struct {
95 UINT8 Major; ///< Major version number
96 UINT8 Minor; ///< Minor version number
97 UINT8 Rev; ///< Revision number
98 UINT8 Build; ///< Build number
99 } SiMrcVersion;
100
101 //
102 // Matches MrcDimmSts enum in MRC
103 //
104 #ifndef DIMM_ENABLED
105 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
106 #endif
107 #ifndef DIMM_DISABLED
108 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
109 #endif
110 #ifndef DIMM_PRESENT
111 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
112 #endif
113 #ifndef DIMM_NOT_PRESENT
114 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
115 #endif
116
117 //
118 // Matches MrcBootMode enum in MRC
119 //
120 #ifndef bmCold
121 #define bmCold 0 // Cold boot
122 #endif
123 #ifndef bmWarm
124 #define bmWarm 1 // Warm boot
125 #endif
126 #ifndef bmS3
127 #define bmS3 2 // S3 resume
128 #endif
129 #ifndef bmFast
130 #define bmFast 3 // Fast boot
131 #endif
132
133 //
134 // Matches MrcDdrType enum in MRC
135 //
136 #ifndef MRC_DDR_TYPE_DDR4
137 #define MRC_DDR_TYPE_DDR4 0
138 #endif
139 #ifndef MRC_DDR_TYPE_DDR3
140 #define MRC_DDR_TYPE_DDR3 1
141 #endif
142 #ifndef MRC_DDR_TYPE_LPDDR3
143 #define MRC_DDR_TYPE_LPDDR3 2
144 #endif
145 #ifndef MRC_DDR_TYPE_UNKNOWN
146 #define MRC_DDR_TYPE_UNKNOWN 3
147 #endif
148
149 #define MAX_PROFILE_NUM 4 // number of memory profiles supported
150 #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
151
152 //
153 // DIMM timings
154 //
155 typedef struct {
156 UINT32 tCK; ///< Memory cycle time, in femtoseconds.
157 UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
158 UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
159 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
160 UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
161 UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
162 UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
163 UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
164 UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
165 UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
166 UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
167 UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
168 UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
169 UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
170 UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
171 UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
172 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
173 UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
174 UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
175 UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
176 } MRC_CH_TIMING;
177
178 typedef struct {
179 UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
180 UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
181 UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
182 UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
183 } MRC_TA_TIMING;
184
185 ///
186 /// Memory SMBIOS & OC Memory Data Hob
187 ///
188 typedef struct {
189 UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
190 UINT8 DimmId;
191 UINT32 DimmCapacity; ///< DIMM size in MBytes.
192 UINT16 MfgId;
193 UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
194 UINT8 RankInDimm; ///< The number of ranks in this DIMM.
195 UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
196 UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
197 UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
198 UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
199 } DIMM_INFO;
200
201 typedef struct {
202 UINT8 Status; ///< Indicates whether this channel should be used.
203 UINT8 ChannelId;
204 UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
205 MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
206 DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
207 MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
208 MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
209 MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
210 MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
211 } CHANNEL_INFO;
212
213 typedef struct {
214 UINT8 Status; ///< Indicates whether this controller should be used.
215 UINT16 DeviceId; ///< The PCI device id of this memory controller.
216 UINT8 RevisionId; ///< The PCI revision id of this memory controller.
217 UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
218 CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
219 MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings
220 MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings
221 MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings
222 MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
223 } CONTROLLER_INFO;
224
225 typedef struct {
226 UINT8 Revision;
227 UINT16 DataWidth; ///< Data width, in bits, of this memory device
228 /** As defined in SMBIOS 3.0 spec
229 Section 7.18.2 and Table 75
230 **/
231 UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
232 UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
233 UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
234 /** As defined in SMBIOS 3.0 spec
235 Section 7.17.3 and Table 72
236 **/
237 UINT8 ErrorCorrectionType;
238
239 SiMrcVersion Version;
240 BOOLEAN EccSupport;
241 UINT8 MemoryProfile;
242 UINT32 TotalPhysicalMemorySize;
243 UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
244 UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
245 UINT8 Ratio;
246 UINT8 RefClk;
247 UINT32 VddVoltage[MAX_PROFILE_NUM];
248 CONTROLLER_INFO Controller[MAX_NODE];
249 } MEMORY_INFO_DATA_HOB;
250
251 /**
252 Memory Platform Data Hob
253
254 <b>Revision 1:</b>
255 - Initial version.
256 <b>Revision 2:</b>
257 - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
258 **/
259 typedef struct {
260 UINT8 Revision;
261 UINT8 Reserved[3];
262 UINT32 BootMode;
263 UINT32 TsegSize;
264 UINT32 TsegBase;
265 UINT32 PrmrrSize;
266 UINT32 PrmrrBase;
267 UINT32 GttBase;
268 UINT32 MmioSize;
269 UINT32 PciEBaseAddress;
270 } MEMORY_PLATFORM_DATA;
271
272 typedef struct {
273 EFI_HOB_GUID_TYPE EfiHobGuidType;
274 MEMORY_PLATFORM_DATA Data;
275 UINT8 *Buffer;
276 } MEMORY_PLATFORM_DATA_HOB;
277
278 #pragma pack (pop)
279
280 #endif // _MEM_INFO_HOB_H_
DIMM_INFO::Status
UINT8 Status
See MrcDimmStatus for the definition of this field.
Definition: MemInfoHob.h:189
DIMM_INFO::SpdDramDeviceType
UINT8 SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:195
DIMM_INFO::SpdModuleMemoryBusWidth
UINT8 SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:197
DIMM_INFO::DimmCapacity
UINT32 DimmCapacity
DIMM size in MBytes.
Definition: MemInfoHob.h:191
DIMM_INFO
Memory SMBIOS & OC Memory Data Hob.
Definition: MemInfoHob.h:188
MEMORY_PLATFORM_DATA
Memory Platform Data Hob.
Definition: MemInfoHob.h:259
DIMM_INFO::SpdModuleType
UINT8 SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:196
MAX_SPD_SAVE
#define MAX_SPD_SAVE
Defines taken from MRC so avoid having to include MrcInterface.h.
Definition: MemInfoHob.h:88
DIMM_INFO::RankInDimm
UINT8 RankInDimm
The number of ranks in this DIMM.
Definition: MemInfoHob.h:194
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: SmbiosCacheInfoHob.h File Reference

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SmbiosCacheInfoHob.h File Reference

Header file for SMBIOS Cache Info HOB. More...

#include <Uefi.h>
#include <Pi/PiHob.h>
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Classes

struct SMBIOS_CACHE_INFO
SMBIOS Cache Info HOB Structure. More...

Detailed Description

Header file for SMBIOS Cache Info HOB.

Copyright
Copyright (c) 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 (DSP0134) http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf

Definition in file SmbiosCacheInfoHob.h.


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SmbiosCacheInfoHob.h
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1 /** @file
2 Header file for SMBIOS Cache Info HOB
3 @copyright
4 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License which accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 @par Specification Reference:
15 System Management BIOS (SMBIOS) Reference Specification v3.0.0
16 dated 2015-Feb-12 (DSP0134)
17 http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf
18 **/
19
20 #ifndef _SMBIOS_CACHE_INFO_HOB_H_
21 #define _SMBIOS_CACHE_INFO_HOB_H_
22
23 #include <Uefi.h>
24 #include <Pi/PiHob.h>
25
26 extern EFI_GUID gSmbiosCacheInfoHobGuid;
27
28 #pragma pack(1)
29 ///
30 /// SMBIOS Cache Info HOB Structure
31 ///
32 typedef struct {
33 UINT16 ProcessorSocketNumber;
34 UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
35 UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
36 UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
37 UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
38 UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
39 UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
40 UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
41 UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
42 UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
43 UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
44 UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
45 /**
46 String Buffer - each string terminated by NULL "0x00"
47 String buffer terminated by double NULL "0x0000"
48 **/
49 } SMBIOS_CACHE_INFO;
50 #pragma pack()
51
52 #endif // _SMBIOS_CACHE_INFO_HOB_H_
SMBIOS_CACHE_INFO::CurrentSramType
UINT16 CurrentSramType
Format defined in SMBIOS Spec v3.0 Section7.8.2.
Definition: SmbiosCacheInfoHob.h:40
SMBIOS_CACHE_INFO::SupportedSramType
UINT16 SupportedSramType
Format defined in SMBIOS Spec v3.0 Section7.8.2.
Definition: SmbiosCacheInfoHob.h:39
SMBIOS_CACHE_INFO::Associativity
UINT8 Associativity
ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5.
Definition: SmbiosCacheInfoHob.h:44
SMBIOS_CACHE_INFO::SocketDesignationStrIndex
UINT8 SocketDesignationStrIndex
String Index in the string Buffer. Example "L1-CACHE".
Definition: SmbiosCacheInfoHob.h:35
SMBIOS_CACHE_INFO::CacheSpeed
UINT8 CacheSpeed
Cache Speed in nanoseconds. 0 if speed is unknown.
Definition: SmbiosCacheInfoHob.h:41
SMBIOS_CACHE_INFO::SystemCacheType
UINT8 SystemCacheType
ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4.
Definition: SmbiosCacheInfoHob.h:43
SMBIOS_CACHE_INFO::ErrorCorrectionType
UINT8 ErrorCorrectionType
ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3.
Definition: SmbiosCacheInfoHob.h:42
SMBIOS_CACHE_INFO
SMBIOS Cache Info HOB Structure.
Definition: SmbiosCacheInfoHob.h:32
SMBIOS_CACHE_INFO::MaxCacheSize
UINT16 MaxCacheSize
Format defined in SMBIOS Spec v3.0 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:37
SMBIOS_CACHE_INFO::InstalledSize
UINT16 InstalledSize
Format defined in SMBIOS Spec v3.0 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:38
SMBIOS_CACHE_INFO::NumberOfCacheLevels
UINT16 NumberOfCacheLevels
Based on Number of Cache Types L1/L2/L3.
Definition: SmbiosCacheInfoHob.h:34
SMBIOS_CACHE_INFO::CacheConfiguration
UINT16 CacheConfiguration
Format defined in SMBIOS Spec v3.0 Section7.8 Table36.
Definition: SmbiosCacheInfoHob.h:36
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: SmbiosProcessorInfoHob.h File Reference

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SmbiosProcessorInfoHob.h File Reference

Header file for SMBIOS Processor Info HOB. More...

#include <Uefi.h>
#include <Pi/PiHob.h>
Include dependency graph for SmbiosProcessorInfoHob.h:

Go to the source code of this file.

Classes

struct SMBIOS_PROCESSOR_INFO
SMBIOS Processor Info HOB Structure. More...

Detailed Description

Header file for SMBIOS Processor Info HOB.

Copyright
Copyright (c) 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 (DSP0134) http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf

Definition in file SmbiosProcessorInfoHob.h.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: SmbiosProcessorInfoHob.h Source File

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SmbiosProcessorInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for SMBIOS Processor Info HOB
3 @copyright
4 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License which accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 @par Specification Reference:
15 System Management BIOS (SMBIOS) Reference Specification v3.0.0
16 dated 2015-Feb-12 (DSP0134)
17 http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf
18 **/
19
20 #ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
21 #define _SMBIOS_PROCESSOR_INFO_HOB_H_
22
23 #include <Uefi.h>
24 #include <Pi/PiHob.h>
25
26 extern EFI_GUID gSmbiosProcessorInfoHobGuid;
27
28 #pragma pack(1)
29 ///
30 /// SMBIOS Processor Info HOB Structure
31 ///
32 typedef struct {
33 UINT16 TotalNumberOfSockets;
34 UINT16 CurrentSocketNumber;
35 UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
36 /** This info is used for both ProcessorFamily and ProcessorFamily2 fields
37 See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
38 **/
39 UINT16 ProcessorFamily;
40 UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
41 UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
42 UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
43 UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
44 UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
45 UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
46 UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
47 UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
48 /** This info is used for both CoreCount & CoreCount2 fields
49 See detailed description in SMBIOS Spec v3.0 Section 7.5.6
50 **/
51 UINT16 CoreCount;
52 /** This info is used for both CoreEnabled & CoreEnabled2 fields
53 See detailed description in SMBIOS Spec v3.0 Section 7.5.7
54 **/
55 UINT16 EnabledCoreCount;
56 /** This info is used for both ThreadCount & ThreadCount2 fields
57 See detailed description in SMBIOS Spec v3.0 Section 7.5.8
58 **/
59 UINT16 ThreadCount;
60 UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
61 /**
62 String Buffer - each string terminated by NULL "0x00"
63 String buffer terminated by double NULL "0x0000"
64 **/
65 } SMBIOS_PROCESSOR_INFO;
66 #pragma pack()
67
68 #endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
SMBIOS_PROCESSOR_INFO::CoreCount
UINT16 CoreCount
This info is used for both CoreCount & CoreCount2 fields See detailed description in SMBIOS Spec v3...
Definition: SmbiosProcessorInfoHob.h:51
SMBIOS_PROCESSOR_INFO::ProcessorManufacturerStrIndex
UINT8 ProcessorManufacturerStrIndex
Index of the String in the String Buffer.
Definition: SmbiosProcessorInfoHob.h:40
SMBIOS_PROCESSOR_INFO::EnabledCoreCount
UINT16 EnabledCoreCount
This info is used for both CoreEnabled & CoreEnabled2 fields See detailed description in SMBIOS Spec ...
Definition: SmbiosProcessorInfoHob.h:55
SMBIOS_PROCESSOR_INFO::Status
UINT8 Status
Format defined in the SMBIOS Spec v3.0 Table 21.
Definition: SmbiosProcessorInfoHob.h:46
SMBIOS_PROCESSOR_INFO::Voltage
UINT8 Voltage
Format defined in SMBIOS Spec v3.0 Section 7.5.4.
Definition: SmbiosProcessorInfoHob.h:43
SMBIOS_PROCESSOR_INFO::ProcessorType
UINT8 ProcessorType
ENUM defined in SMBIOS Spec v3.0 Section 7.5.1.
Definition: SmbiosProcessorInfoHob.h:35
SMBIOS_PROCESSOR_INFO::ProcessorVersionStrIndex
UINT8 ProcessorVersionStrIndex
Index of the String in the String Buffer.
Definition: SmbiosProcessorInfoHob.h:42
SMBIOS_PROCESSOR_INFO::ProcessorFamily
UINT16 ProcessorFamily
This info is used for both ProcessorFamily and ProcessorFamily2 fields See ENUM defined in SMBIOS Spe...
Definition: SmbiosProcessorInfoHob.h:39
SMBIOS_PROCESSOR_INFO::ProcessorUpgrade
UINT8 ProcessorUpgrade
ENUM defined in SMBIOS Spec v3.0 Section 7.5.5.
Definition: SmbiosProcessorInfoHob.h:47
SMBIOS_PROCESSOR_INFO::ThreadCount
UINT16 ThreadCount
This info is used for both ThreadCount & ThreadCount2 fields See detailed description in SMBIOS Spec ...
Definition: SmbiosProcessorInfoHob.h:59
SMBIOS_PROCESSOR_INFO::CurrentSpeedInMHz
UINT16 CurrentSpeedInMHz
Snapshot of current processor speed during boot.
Definition: SmbiosProcessorInfoHob.h:45
SMBIOS_PROCESSOR_INFO::ProcessorId
UINT64 ProcessorId
ENUM defined in SMBIOS Spec v3.0 Section 7.5.3.
Definition: SmbiosProcessorInfoHob.h:41
SMBIOS_PROCESSOR_INFO
SMBIOS Processor Info HOB Structure.
Definition: SmbiosProcessorInfoHob.h:32
SMBIOS_PROCESSOR_INFO::ProcessorCharacteristics
UINT16 ProcessorCharacteristics
Format defined in SMBIOS Spec v3.0 Section 7.5.9.
Definition: SmbiosProcessorInfoHob.h:60
SMBIOS_PROCESSOR_INFO::ExternalClockInMHz
UINT16 ExternalClockInMHz
External Clock Frequency. Set to 0 if unknown.
Definition: SmbiosProcessorInfoHob.h:44
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

  • File List
  • File Members
  • All
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • b
  • g
  • m
  • s
  • w
Here is a list of all documented file members with links to the documentation:

- b -

  • B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK : GpioConfig.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h

- g -

  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_GROUP : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioNoTolerance1v8 : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateLock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDeep : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResetNormal : GpioConfig.h
  • GpioResetPwrGood : GpioConfig.h
  • GpioResetResume : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h
  • GpioTolerance1v8 : GpioConfig.h

- m -

  • MAX_SPD_SAVE : MemInfoHob.h

- s -

  • SI_PCH_INT_PIN : FspsUpd.h
  • SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG : FspsUpd.h
  • SiPchNoInt : FspsUpd.h

- w -

  • WARM_BOOT : MemInfoHob.h
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

  • File List
  • File Members
  • All
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • GPIO_GROUP : GpioConfig.h
  • GPIO_PAD : GpioConfig.h
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

  • File List
  • File Members
  • All
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • SI_PCH_INT_PIN : FspsUpd.h
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

  • File List
  • File Members
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  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • g
  • s

- g -

  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioNoTolerance1v8 : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateLock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDeep : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResetNormal : GpioConfig.h
  • GpioResetPwrGood : GpioConfig.h
  • GpioResetResume : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h
  • GpioTolerance1v8 : GpioConfig.h

- s -

  • SiPchNoInt : FspsUpd.h
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

  • File List
  • File Members
  • All
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK : GpioConfig.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • MAX_SPD_SAVE : MemInfoHob.h
  • SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG : FspsUpd.h
  • WARM_BOOT : MemInfoHob.h
Generated on Thu Jun 28 2018 21:44:50 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Include -> ConfigBlock Relation

  • Include

Include → ConfigBlock Relation

File in Include | Includes file in Include/ConfigBlock
FspsUpd.h | CpuConfigFspData.h


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

directory ConfigBlock

Files

file | FspmUpd.h [code]
file | FspsUpd.h [code]
file | FsptUpd.h [code]
file | FspUpd.h [code]
file | GpioConfig.h [code]
Header file for GpioConfig structure used by GPIO library.
file | GpioSampleDef.h [code]
file | MemInfoHob.h [code]
This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs.
file | SmbiosCacheInfoHob.h [code]
Header file for SMBIOS Cache Info HOB.
file | SmbiosProcessorInfoHob.h [code]
Header file for SMBIOS Processor Info HOB.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

  • Include
  • ConfigBlock
ConfigBlock Directory Reference
Directory dependency graph for ConfigBlock:

Files

file CpuConfigFspData.h [code]
FSP CPU Data Config Block.


Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

1 /*! Invisible class because of truncation */
2 class Invisible { };
3
4 /*! Truncated class, inheritance relation is hidden */
5 class Truncated : public Invisible { };
6
7 /* Class not documented with doxygen comments */
8 class Undocumented { };
9
10 /*! Class that is inherited using public inheritance */
11 class PublicBase : public Truncated { };
12
13 /*! A template class */
14 template<class T> class Templ { };
15
16 /*! Class that is inherited using protected inheritance */
17 class ProtectedBase { };
18
19 /*! Class that is inherited using private inheritance */
20 class PrivateBase { };
21
22 /*! Class that is used by the Inherited class */
23 class Used { };
24
25 /*! Super class that inherits a number of other classes */
26 class Inherited : public PublicBase,
27 protected ProtectedBase,
28 private PrivateBase,
29 public Undocumented,
30 public Templ<int>
31 {
32 private:
33 Used *m_usedClass;
34 };

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
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  • A box with a gray border denotes an undocumented struct or class.
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Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: Related Pages

Related Pages
Here is a list of all related documentation pages:
FSP OVERVIEW

FSP Overview

2.1 Technical Overview

The Intel® Firmware Support Package (FSP) provides chipset and processor initialization in a format that can easily be incorporated into many existing boot loaders
FSP INTEGRATION

3 FSP Integration

FSP OUTPUT

4 FSP Output

The FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon
FSP POSTCODE

5 FSP PostCode

The FSP outputs 16 bit postcode to indicate which API and in which module the execution is happening