CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: INTRODUCTION

CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
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INTRODUCTION

1 Introduction

1.1 Purpose

The purpose of this document is to describe the steps required to integrate the Intel® Firmware Support Package (FSP) into a boot loader solution. It supports CoffeeLake platforms with CoffeeLake processor and CoffeeLake Platform Controller Hub (PCH).

1.2 Intended Audience

This document is targeted at all platform and system developers who need to consume FSP binaries in their boot loader solutions. This includes, but is not limited to: system BIOS developers, boot loader developers, system integrators, as well as end users.

1.3 Related Documents

  • Platform Initialization (PI) Specification v1.4 located at http://www.uefi.org/specifications
  • Intel® Firmware Support Package: External Architecture Specification (EAS) v2.0 located at http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf
  • Boot Setting File Specification (BSF) v1.0 https://firmware.intel.com/sites/default/files/BSF_1_0.pdf
  • Binary Configuration Tool for Intel® Firmware Support Package available at http://www.intel.com/fsp

1.4 Acronyms and Terminology

Acronym | Definition
BCT | Binary Configuration Tool
BSF | Boot Setting File
BSP | Boot Strap Processor
BWG | BIOS Writer's Guide
CAR | Cache As Ram
CRB | Customer Reference Board
FIT | Firmware Interface Table
FSP | Firmware Support Package
FSP API | Firmware Support Package Interface
FW | Firmware
PCH | Platform Controller Hub
PMC | Power Management Controller
SBSP | System BSP
SMI | System Management Interrupt
SMM | System Management Mode
SPI | Serial Peripheral Interface
TSEG | Memory Reserved at the Top of Memory to be used as SMRAM
UPD | Updatable Product Data
IED | Intel Enhanced Debug
GTT | Graphics Translation Table
BDSM | Base Data Of Stolen Memory
PMRR | Protected Memory Range Reporting
IOT | Internal Observation Trace
MOT | Memory Observation Trace
DPR | DMA Protected Range
REMAP | Remapped Memory Area
TOLUD | Top of Low Usable Memory
TOUUD | Top of Upper Usable Memory
Generated on Wed Aug 22 2018 17:48:56 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP OVERVIEW

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FSP OVERVIEW

FSP Overview

2.1 Technical Overview

The Intel® Firmware Support Package (FSP) provides chipset and processor initialization in a format that can easily be incorporated into many existing boot loaders.

The FSP will perform the necessary initialization steps as documented in the BWG including initialization of the CPU, memory controller, chipset and certain bus interfaces, if necessary.

FSP is not a stand-alone boot loader; therefore it needs to be integrated into a host boot loader to carry out other boot loader functions, such as: initializing non-Intel components, conducting bus enumeration, and discovering devices in the system and all industry standard initialization.

The FSP binary can be integrated easily into many different boot loaders, such as Coreboot, EDKII etc. and also into the embedded OS directly.

Below are some required steps for the integration:

  • Customizing The static FSP configuration parameters are part of the FSP binary and can be customized by external tools that will be provided by Intel.
  • Rebasing The FSP is not Position Independent Code (PIC) and the whole FSP has to be rebased if it is placed at a location which is different from the preferred address during build process.
  • Placing Once the FSP binary is ready for integration, the boot loader build process needs to be modified to place this FSP binary at the specific rebasing location identified above.
  • Interfacing The boot loader needs to add code to setup the operating environment for the FSP, call the FSP with correct parameters and parse the FSP output to retrieve the necessary information returned by the FSP.

2.2 FSP Distribution Package

  • The FSP distribution package contains the following:
    • FSP Binary
    • FSP Integration Guide
    • BSF Configuration File
    • Data Structure Header File
  • The FSP configuration utility called BCT is available as a separate package. It can be downloaded from link mentioned in Section 1.3.

2.2.1 Package Layout

  • Docs (Auto generated)
    • CoffeeLake_FSP_Integration_Guide.pdf
    • CoffeeLake_FSP_Integration_Guide.chm
  • Include
    • FsptUpd.h, FspmUpd.h and FspsUpd.h (FSP UPD structure and related definitions)
    • GpioSampleDef.h (Sample enum definitions for Gpio table)
  • CoffeeLakeFspBinPkg.dec (EDKII declaration file for package)
  • Fsp.bsf (BSF file for configuring the data using BCT tool)
  • Fsp.fd (FSP Binary)
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP INTEGRATION

FSP INTEGRATION

3 FSP Integration

3.1 Assumptions Used in this Document

The FSP for the CoffeeLake platform is built with a preferred base address given by PcdFspAreaBaseAddress and so the reference code provided in the document assumes that the FSP is placed at this base address during the final boot loader build. Users may rebase the FSP binary at a different location with Intel's Binary Configuration Tool (BCT) before integrating to the boot loader.

For other assumptions and conventions, please refer section 8 in the FSP External Architecture Specification version 2.0.

3.2 Boot Flow

Please refer Chapter 7 in the FSP External Architecture Specification version 2.0 for Boot flow chart.

3.3 FSP INFO Header

The FSP has an Information Header that provides critical information that is required by the bootloader to successfully interface with the FSP. The structure of the FSP Information Header is documented in the FSP External Architecture Specification version 2.0 with a HeaderRevision of 3.

3.4 FSP Image ID and Revision

FSP information header contains an Image ID field and an Image Revision field that provide the identification and revision information of the FSP binary. It is important to verify these fields while integrating the FSP as API parameters could change over different FSP IDs and revisions. All the FSP FV segments(FSP-T, FSP-M and FSP-S) must have same FSP Image ID and revision number, using FV segments with different revision numbers in a single FSP image is not valid. The FSP API parameters documented in this integration guide are applicable for the Image ID and Revision specified as below.

The FSP ImageId string in the FSP information header is given by PcdFspImageIdString and the ImageRevision field is given by SiliconInitVersionMajor|Minor|FspVersionRevision|FspVersionBuild (Ex:0x07020110).

3.5 FSP Global Data

FSP uses some amount of TempRam area to store FSP global data which contains some critical data like pointers to FSP information headers and UPD configuration regions, FSP/Bootloader stack pointers required for stack switching etc. HPET Timer register(2) PcdGlobalDataPointerAddress is reserved to store address of this global data, and hence boot loader should not use this register for any other purpose. If TempRAM initialization is done by boot loader, then HPET has to be initialized to the base so that access to the register will work fine.

3.6 FSP APIs

This release of the CoffeeLake FSP supports the all APIs required by the FSP External Architecture Specification version 2.0. The FSP information header contains the address offset for these APIs. Register usage is described in the FSP External Architecture Specification version 2.0. Any usage not described by the specification is described in the individual sections below.

The below sections will highlight any changes that are specific to this FSP release.

3.6.1 TempRamInit API

Please refer Chapter 8.5 in the FSP External Architecture Specification version 2.0 for complete details including the prototype, parameters and return value details for this API.

TempRamInit does basic early initialization primarily setting up temporary RAM using cache. It returns ECX pointing to beginning of temporary memory and EDX pointing to end of temporary memory + 1. The total temporary ram currently available is given by PcdTemporaryRamSize starting from the base address of PcdTemporaryRamBase. Out of total temporary memory avaiable, last PcdFspReservedBufferSize bytes of space reserved by FSP for TempRamInit if temporary RAM initialization is done by FSP and remaining space from TemporaryRamBase(ECX) to TemporaryRamBase+TemporaryRamSize-FspReservedBufferSize (EDX) is avaiable for both bootloader and FSP binary.

TempRamInit** also sets up the code caching of the region passed CodeCacheBase and CodeCacheLength, which are input parameters to TempRamInitApi. if 0 is passed in for CodeCacheBase, the base used will be 4 GB - 1 - length to be code cached instead of starting from CodeCacheBase.

Note
: when programming MTRR CodeCacheLength will be reduced, if SKU LLC size is smaller than the requested.

It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. If more than microcode update for the CPU is present, the microcode update with the latest revision is loaded.

FSPT_UPD.MicrocodeRegionBase** and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. If a region is passed, then if a newer microcode update revision is in the region, it will be loaded by the FSP.

MTRRs are programmed to the default values to have the following memory map:

Memory range | Cache Attribute
0xFEF00000 - 0x00040000 | Write back
CodeCacheBase - CodeCacheLength | Write protect

3.6.2 FspMemoryInit API

Please refer to Chapter 8.6 in the FSP external Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

The FspmUpdPtr is pointer to FSPM_UPD structure which is described in header file FspmUpd.h.

Boot Loader must pass valid CAR region for FSP stack use through FSPM_UPD.FspmArchUpd.StackBase and FSPM_UPD.FspmArchUpd.StackSize UPDs.

The minimum FSP stack size required for this revision of FSP is 160KB, stack base is 0xFEF17F00 by default.

The base address of HECI device (Bus 0, Device 22, Function 0) is required to be initialized prior to perform FspMemoryInit flow. The default address is programmed to 0xFED1A000.

Calculate memory map determining memory regions TSEG, IED, GTT, BDSM, ME stolen, Uncore PMRR, IOT, MOT, DPR, REMAP, TOLUD, TOUUD. Programming will be done at a different time.

3.6.3 TempRamExit API

Please refer to Chapter 8.7 in the FSP external Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

If Boot Loader initializes the Temporary RAM (CAR) and skip calling TempRamInit API, it is expected that bootloader must skip calling this API and bootloader will tear down the temporary memory area setup in the cache and bring the cache to normal mode of operation.

This revision of FSP doesn't have any fields/structure to pass as parameter for this API. Pass Null for TempRamExitParamPtr.

At the end of TempRamExit the original code and data caching are disabled. FSP will reconfigure all MTRRs as described in the table below for performance optimization.

Memory range | Cache Attribute
0x00000000 - 0x0009FFFF | Write back
0x000C0000 - Top of Low Memory | Write back
0xFF000000 - 0xFFFFFFFF (Flash region) | Write protect
Todo:
program 0x1000000000 - Top of High Memory | Write back

If the boot loader wish to reconfigure the MTRRs differently, it can be overridden immediately after this API call.

3.6.4 FspSiliconInit API

Please refer to Chapter 8.8 in the FSP external Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

The FspsUpdPtr is pointer to FSPS_UPD structure which is described in header file FspsUpd.h.

It is expected that boot loader will program MTRRs for SBSP as needed after TempRamExit but before entering FspSiliconInit. If MTRRs are not programmed properly, the boot performance might be impacted.

The region of 0x5_8000 - 0x5_8FFF is used by FspSilicionInit for starting APs. If this data is important to bootloader, then bootloader needs to preserve it before calling FspSilicionInit.

It is a requirement for bootloader to have Firmware Interface Table (FIT), which contains pointers to each microcode. The microcode is loaded for all cores before reset vector. If more than one microcode update for the CPU is present, the latest revision is loaded.

MicrocodeRegionBase and MicrocodeRegionLength are both input parameters to TempRamInit and UPD for SiliconInit API. UPD has priority and will be searched for a later revision than TempRamInit. If MicrocodeRegionBase and MicrocodeRegionLength values are 0, FSP will not attempt to update the microcode. If a microcode region is passed, and if a later revision of microcode is present in this region, FSP will load it.

FSP initializes PCH audio including selecting HD Audio verb table and initializes Codec.

PCH required initialization is done for the following HECI, USB, HSIO, Integrated Sensor Hub, Camera, PCI Express, Vt-d.

FSP initializes CPU features: XD, VMX, AES, IED, HDC, x(2)Apic, Intel® Processor Trace, Three strike counter, Machine check, Cache pre-fetchers, Core PMRR, Power management.

Initializes HECI, DMI, Internal Graphics. Publish EFI_PEI_GRAPHICS_INFO_HOB during normal boot but this HOB will not be published during S3 resume as FSP will not launch the PEI Graphics PEIM during S3 resume.

Programs SA Bars: MchBar, DmiBar, EpBar, GdxcBar, EDRAM (if supported). Please refer to section 2.8 (MemoryMap) for the corresponding Bar values. GttMmadr (0xDF000000) and GmAdr(0xC0000000) are temporarily programmed and cleared after use in FSP.

3.6.5 NotifyPhase API

Please refer Chapter 8.9 in the FSP External Architecture Specification version 2.0 for the prototype, parameters and return value details for this API.

3.6.5.1 PostPciEnumeration Notification

This phase EnumInitPhaseAfterPciEnumeration is to be called after PCI enumeration but before execution of third party code such as option ROMs. Currently, nothing is done in this phase, but in the future updates, programming may be done in this phase.

3.6.5.2 ReadyToBoot Notification

This phase EnumInitPhaseReadyToBoot is to be called before giving control to boot. It includes some final initialization steps recommended by the BWG, including power management settings, Send ME Message EOP (End of Post).

3.6.5.3 EndOfFirmware Notification

This phase EnumInitEndOfFirmware is to be called before the firmware/preboot environment transfers management of all system resources to the OS or next level execution environment. It includes final locking of chipset registers

3.7 Memory Map

Below diagram represents the memory map allocated by FSP including the FSP specific regions.

System Memory Map

/**

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP PORTING RECOMMENDATION

FSP PORTING RECOMMENDATION

4 FSP Porting Recommendation

Here listed some notes or recommendation when porting with FSP.

4.1 Locking PAM register

FSP 2.0 introduced EndOfFirmware Notify phase callback which is a recommended place for locking PAM registers so FSP by default implemented this way. If it is still too early to lock PAM registers then the PAM locking code inside FSP can be disabled by UPD -> FSP_S_TEST_CONFIG -> SkipPamLock or SA policy -> _SI_PREMEM_POLICY_STRUCT -> SA_MISC_PEI_CONFIG -> SkipPamLock, and platform or wrapper code should do the PAM locking right before booting OS (so do it outside FSP instead) by programming one PCI config space register as below.

This PAM locking step has to been applied in all boot paths including S3 resume. To lock PAM regsiter:

MmioOr32 (B0: D0: F0: Register 0x80, BIT0)

4.2 Locking SMRAM register

Since SMRAM locking is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation, the FSP code by default will not lock it. The platform or FSP Wrapper code should lock SMRAM by below programming step before any 3rd partiy OpRom execution (and should be locked in S3 resume right before OS waking vector).

PciOr8 (B0: D0: F0: Register 0x88, BIT4); Note: it must be programmed by CF8/CFC Standard PCI access mechanism. (MMIO access will not work)

4.3 Locking SMI register

Global SMI bit is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation after SMM configuration. FSP by default will not lock it. Boot loader is responsible for locking below regsiters after SMM configuration. Set AcpiBase + 0x30[0] to 1b to enable global SMI. Set PMC PCI offset A0h[4] = 1b to lock SMI.

4.4 Verify below settings are correct for your platforms

PMC PciCfgSpace is not PCI compliant.FSP will hide the PMC controller to avoid external software or OS from corrupting the BAR addresses. FSP will program the PMC controller IO and MMIO BAR's with below addresses. Please use this addrerss in the wrapper code instead of reading from PMC controller.

Register | Values
ABASE | 0x1800
PWRMBASE | 0xFE000000
PCIEXBAR_BASE_ADDRESS | 0xE0000000
Note
:
  • Boot Loader can use different value for PCIEXBAR_BASE_ADDRESS either by modifying the UPD (under FSP-T) or by overriding the PCIEXBAR (B0:D0:F0:R60h) before calling FspMemoryInit Api.
  • Boot Loader should avoid using conflicting address when reprogramming PCIEXBAR_BASE_ADDRESS than the recommended one.

4.5 FSP_STATUS_RESET_REQUIRED

As per FSP External Architecture Specification version 2.0, Any reset required in the FSP flow will be reported as return status FSP_STATUS_RESET_REQUIREDx by the API.It is the bootloader responsibility to reset the system according to the reset type requested.

Below table specifies the return status returned by FSP API and the requested reset type.

FSP_STATUS_RESET_REQUIRED Code | Reset Type requested
0x40000001 | Cold Reset
0x40000002 | Warm Reset
0x40000003 | Global Reset - Puts the system to Global reset through Heci or Full Reset through PCH
0x40000004 | Reserved
0x40000005 | Reserved
0x40000006 | Reserved
0x40000007 | Reserved
0x40000008 | Reserved
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: UPD PORTING GUIDE

UPD PORTING GUIDE

5 UPD porting guide

UPD porting guide:

UPD | Dependency | Description | Value
EnableSgx | CoffeeLake Platform | Temporary workaround | 2
PchTraceHubMode | CoffeeLake Pch A0 | BIOS workaround for TraceHub power gating issue on PCH A0 | 2
PchTraceHubMemReg0Size | CoffeeLake Pch A0 | BIOS workaround for TraceHub power gating issue on PCH A0 | 3
PchTraceHubMemReg1Size | CoffeeLake Pch A0 | BIOS workaround for TraceHub power gating issue on PCH A0 | 3
CstateLatencyControl1Irtl | Server platform | Server platform should has different setting | 0x6B
PchPcieHsioRxSetCtleEnable | Board design | Different board requires different value | tune
PchPcieHsioRxSetCtle | Board design | Different board requires different value | tune
PchSataHsioRxGen3EqBoostMagEnable | Board design | Different board requires different value | tune
PchSataHsioRxGen3EqBoostMag | Board design | Different board requires different value | tune
PchSataHsioTxGen1DownscaleAmpEnable | Board design | Different board requires different value | tune
PchSataHsioTxGen1DownscaleAmp | Board design | Different board requires different value | tune
PchSataHsioTxGen2DownscaleAmpEnable | Board design | Different board requires different value | tune
PchSataHsioTxGen2DownscaleAmp | Board design | Different board requires different value | tune
PchNumRsvdSmbusAddresses | Board design | Different board requires different value | tune
RsvdSmbusAddressTablePtr | Board design | Different board requires different value | tune
BiosSize | Board design | Different board requires different value | tune
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP OUTPUT

FSP OUTPUT

6 FSP Output

The FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon.

Please refer to the Platform Initialization (PI) Specification - Volume 3: Shared Architectural Elements specification for PI Architectural HOBs. Please refer Chapter 9 in the FSP External Architecture Specification version 2.0 for details about FSP Architectural HOBs.

Below section describe the HOBs not covered in the above two specifications.

6.1 SMRAM Resource Descriptor HOB

The FSP will report the system SMRAM T-SEG range through a generic resource HOB if T-SEG is enabled. The owner field of the HOB identifies the owner as T-SEG.

#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }

6.2 SMBIOS INFO HOB

The FSP will report the SMBIOS through a HOB with below GUID. This information can be consumed by the bootloader to produce the SMBIOS tables. These structures are included as part of MemInfoHob.h , SmbiosCacheInfoHob.h, SmbiosProcessorInfoHob.h & FirmwareVersionInfoHob.h

#define SI_MEMORY_INFO_DATA_HOB_GUID \
{ 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } };
typedef struct {
MrcDimmStatus Status; ///< See MrcDimmStatus for the definition of this field.
UINT8 DimmId;
UINT32 DimmCapacity; ///< DIMM size in MBytes.
UINT16 MfgId;
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE_DATA]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
} DIMM_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this channel should be used.
UINT8 ChannelId;
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
MRC_CH_TIMING Timing[MAX_PROFILE]; ///< The channel timing values.
DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
} CHANNEL_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this controller should be used.
UINT16 DeviceId; ///< The PCI device id of this memory controller.
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
} CONTROLLER_INFO;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
UINT8 Revision;
UINT16 DataWidth;
/// As defined in SMBIOS 3.0 spec
/// Section 7.18.2 and Table 75
UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
/// As defined in SMBIOS 3.0 spec
/// Section 7.17.3 and Table 72
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
UINT32 FreqMax;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
BOOLEAN XmpProfileEnable;
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE];
CONTROLLER_INFO Controller[MAX_NODE];
} MEMORY_INFO_DATA_HOB;
#define SI_MEMORY_PLATFORM_DATA_HOB \
{ 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
typedef struct {
UINT8 Revision;
UINT8 Reserved[3];
UINT32 BootMode;
UINT32 TsegSize;
UINT32 TsegBase;
UINT32 PrmrrSize;
UINT32 PrmrrBase;
UINT32 GttBase;
UINT32 MmioSize;
UINT32 PciEBaseAddress;
} MEMORY_PLATFORM_DATA;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
MEMORY_PLATFORM_DATA Data;
UINT8 *Buffer;
} MEMORY_PLATFORM_DATA_HOB;
#define SMBIOS_CACHE_INFO_HOB_GUID \
{ 0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7} }
///
/// SMBIOS Cache Info HOB Structure
///
typedef struct {
UINT16 ProcessorSocketNumber;
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
///String Buffer - each string terminated by NULL "0x00"
///String buffer terminated by double NULL "0x0000"
} SMBIOS_CACHE_INFO;
#define SMBIOS_PROCESSOR_INFO_HOB_GUID \
{ 0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71} }
///
/// SMBIOS Processor Info HOB Structure
///
typedef struct {
UINT16 TotalNumberOfSockets;
UINT16 CurrentSocketNumber;
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
///This info is used for both ProcessorFamily and ProcessorFamily2 fields
///See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
UINT16 ProcessorFamily;
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
///This info is used for both CoreCount & CoreCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.6
UINT16 CoreCount;
///This info is used for both CoreEnabled & CoreEnabled2 fields
///See detailed description in SMBIOS Spec v3.0 Section 7.5.7
UINT16 EnabledCoreCount;
///This info is used for both ThreadCount & ThreadCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.8
UINT16 ThreadCount;
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
/// String Buffer - each string terminated by NULL "0x00"
/// String buffer terminated by double NULL "0x0000"
} SMBIOS_PROCESSOR_INFO;
#define SMBIOS_FIRMWARE_VERSION_INFO_HOB_GUID \
{ 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}
///
/// Firmware Version Structure
///
typedef struct {
UINT8 MajorVersion;
UINT8 MinorVersion;
UINT8 Revision;
UINT16 BuildNumber;
} FIRMWARE_VERSION;
///
/// Firmware Version Information Structure
///
typedef struct {
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
} FIRMWARE_VERSION_INFO;
///
/// The Smbios structure header.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Handle;
} SMBIOS_STRUCTURE;
///
/// Firmware Version Information HOB Structure
///
typedef struct {
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
UINT8 Count; ///< Offset 28 Number of FVI elements included.
///
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
///
} FIRMWARE_VERSION_INFO_HOB;

6.3 CHIPSETINIT INFO HOB

The FSP will report the ChipsetInit CRC through a HOB with below GUID. This information can be consumed by the bootloader to check if ChipsetInit CRC is matched between BIOS and ME. These structures are included as part of FspsUpd.h

#define CHIPSETINIT_INFO_HOB_GUID \
{ 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
///
/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
///
typedef struct {
UINT8 Revision;
UINT8 Rsvd[3];
UINT16 MeChipInitCrc;
UINT16 BiosChipInitCrc;
} CHIPSET_INIT_INFO;

6.4 HOB USAGE INFO HOB

The FSP will report the Hob memory usage through a HOB with below GUID. This information can be consumed by the bootloader to check how many the temporary ram left.

#define HOB_USAGE_DATA_HOB_GUID \
{0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
typedef struct {
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
UINTN FreeMemory;
} HOB_USAGE_DATA_HOB;
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP POSTCODE

FSP POSTCODE

7 FSP PostCode

The FSP outputs 16 bit postcode to indicate which API and in which module the execution is happening.

Bit Range | Description
Bit15 - Bit12 (X) | used to indicate the phase/api under which the code is executing
Bit11 - Bit8 (Y) | used to indicate the module
Bit7 (ZZ bit 7) | reserved for error
Bit6 - Bit0 (ZZ) | individual codes

7.1 PostCode Info

Below diagram represents the 16 bit PostCode usage in FSP.

7.1.1 TempRamInit API Status Codes (0xFxxx)

PostCode | Module | Description
0x0000 | FSP | TempRamInit API Entry (The change in upper byte is due to not enabling of the Port81 early in the boot)
0x007F | FSP | TempRamInit API Exit

7.1.2 FspMemoryInit API Status Codes (0xDxxx)

PostCode | Module | Description
0xD800 | FSP | FspMemoryInit API Entry
0xD87F | FSP | FSpMemoryInit API Exit
0xDA00 | SA | Pre-Mem SaInit Entry
0xDA02 | SA | OverrideDev0Did Start
0xDA04 | SA | OverrideDev2Did Start
0xDA06 | SA | Programming SA Bars
0xDA08 | SA | Install SA HOBs
0xDA0A | SA | Reporting SA PCIe code version
0xDA0C | SA | SaSvInit Start
0xDA10 | SA | Initializing DMI
0xDA15 | SA | Initialize TCSS PreMem
0xDA1F | SA | Initializing DMI/OPI Max PayLoad Size
0xDA20 | SA | Initializing SwitchableGraphics
0xDA30 | SA | Initializing SA PCIe
0xDA3F | SA | Programming PEG credit values Start
0xDA40 | SA | Initializing DMI Tc/Vc mapping
0xDA42 | SA | CheckOffboardPcieVga
0xDA44 | SA | CheckAndInitializePegVga
0xDA50 | SA | Initializing Graphics
0xDA52 | SA | Initializing System Agent Overclocking
0xDA7F | SA | Pre-Mem SaInit Exit
0xDB00 | PCH | Pre-Mem PchInit Entry
0xDB02 | PCH | Pre-Mem Disable PCH fused controllers
0xDB15 | PCH | Pre-Mem SMBUS configuration
0xDB48 | PCH | Pre-Mem PchOnPolicyInstalled Entry
0xDB49 | PCH | Pre-Mem Program HSIO
0xDB4A | PCH | Pre-Mem DCI configuration
0xDB4C | PCH | Pre-Mem Host DCI enabled
0xDB4D | PCH | Pre-Mem Trace Hub - Early configuration
0xDB4E | PCH | Pre-Mem Trace Hub - Device disabled
0xDB4F | PCH | Pre-Mem TraceHub - Programming MSR
0xDB50 | PCH | Pre-Mem Trace Hub - Power gating configuration
0xDB51 | PCH | Pre-Mem Trace Hub - Power gating Trace Hub device and locking HSWPGCR1 register
0xDB52 | PCH | Pre-Mem Initialize HPET timer
0xDB55 | PCH | Pre-Mem PchOnPolicyInstalled Exit
0xDB7F | PCH | Pre-Mem PchInit Exit
0xDC00 | CPU | CPU Pre-Mem Entry
0xDC0F | CPU | CpuAddPreMemConfigBlocks Done
0xDC20 | CPU | CpuOnPolicyInstalled Start
0xDC2F | CPU | XmmInit Start
0xDC3F | CPU | TxtInit Start
0xDC4F | CPU | Init CPU Straps
0xDC5F | CPU | Init Overclocking
0xDC6F | CPU | CPU Pre-Mem Exit
0x**55 | SA | MRC_MEM_INIT_DONE
0x**D5 | SA | MRC_MEM_INIT_DONE_WITH_ERRORS
0xDD00 | SA | MRC_INITIALIZATION_START
0xDD10 | SA | MRC_CMD_PLOT_2D
0xDD1B | SA | MRC_FAST_BOOT_PERMITTED
0xDD1C | SA | MRC_RESTORE_NON_TRAINING
0xDD1D | SA | MRC_PRINT_INPUT_PARAMS
0xDD1E | SA | MRC_SET_OVERRIDES_PSPD
0xDD20 | SA | MRC_SPD_PROCESSING
0xDD21 | SA | MRC_SET_OVERRIDES
0xDD22 | SA | MRC_MC_CAPABILITY
0xDD23 | SA | MRC_MC_CONFIG
0xDD24 | SA | MRC_MC_MEMORY_MAP
0xDD25 | SA | MRC_JEDEC_INIT_LPDDR3
0xDD26 | SA | MRC_RESET_SEQUENCE
0xDD27 | SA | MRC_PRE_TRAINING
0xDD28 | SA | MRC_EARLY_COMMAND
0xDD29 | SA | MRC_SENSE_AMP_OFFSET
0xDD2A | SA | MRC_READ_MPR
0xDD2B | SA | MRC_RECEIVE_ENABLE
0xDD2C | SA | MRC_JEDEC_WRITE_LEVELING
0xDD2D | SA | MRC_LPDDR_LATENCY_SET_B
0xDD2E | SA | MRC_WRITE_TIMING_1D
0xDD2F | SA | MRC_READ_TIMING_1D
0xDD30 | SA | MRC_DIMM_ODT
0xDD31 | SA | MRC_EARLY_WRITE_TIMING_2D
0xDD32 | SA | MRC_WRITE_DS
0xDD33 | SA | MRC_WRITE_EQ
0xDD34 | SA | MRC_EARLY_READ_TIMING_2D
0xDD35 | SA | MRC_READ_ODT
0xDD36 | SA | MRC_READ_EQ
0xDD37 | SA | MRC_READ_AMP_POWER
0xDD38 | SA | MRC_WRITE_TIMING_2D
0xDD39 | SA | MRC_READ_TIMING_2D
0xDD3A | SA | MRC_CMD_VREF
0xDD3B | SA | MRC_WRITE_VREF_2D
0xDD3C | SA | MRC_READ_VREF_2D
0xDD3D | SA | MRC_POST_TRAINING
0xDD3E | SA | MRC_LATE_COMMAND
0xDD3F | SA | MRC_ROUND_TRIP_LAT
0xDD40 | SA | MRC_TURN_AROUND
0xDD41 | SA | MRC_CMP_OPT
0xDD42 | SA | MRC_SAVE_MC_VALUES
0xDD43 | SA | MRC_RESTORE_TRAINING
0xDD44 | SA | MRC_RMT_TOOL
0xDD45 | SA | MRC_WRITE_SR
0xDD46 | SA | MRC_DIMM_RON
0xDD47 | SA | MRC_RCVEN_TIMING_1D
0xDD48 | SA | MRC_MR_FILL
0xDD49 | SA | MRC_PWR_MTR
0xDD4A | SA | MRC_DDR4_MAPPING
0xDD4B | SA | MRC_WRITE_VOLTAGE_1D
0xDD4C | SA | MRC_EARLY_RDMPR_TIMING_2D
0xDD4D | SA | MRC_FORCE_OLTM
0xDD50 | SA | MRC_MC_ACTIVATE
0xDD51 | SA | MRC_RH_PREVENTION
0xDD52 | SA | MRC_GET_MRC_DATA
0xDD53 | SA | Reserved
0xDD58 | SA | MRC_RETRAIN_CHECK
0xDD5A | SA | MRC_SA_GV_SWITCH
0xDD5B | SA | MRC_ALIAS_CHECK
0xDD5C | SA | MRC_ECC_CLEAN_START
0xDD5D | SA | MRC_DONE
0xDD5F | SA | MRC_CPGC_MEMORY_TEST
0xDD60 | SA | MRC_TXT_ALIAS_CHECK
0xDD61 | SA | MRC_ENG_PERF_GAIN
0xDD68 | SA | MRC_MEMORY_TEST
0xDD69 | SA | MRC_FILL_RMT_STRUCTURE
0xDD70 | SA | MRC_SELF_REFRESH_EXIT
0xDD71 | SA | MRC_NORMAL_MODE
0xDD7D | SA | MRC_SSA_PRE_STOP_POINT
0xDD7F | SA | MRC_SSA_STOP_POINT, MRC_INITIALIZATION_END
0xDD90 | SA | MRC_CMD_PLOT_2D_ERROR
0xDD9B | SA | MRC_FAST_BOOT_PERMITTED_ERROR
0xDD9C | SA | MRC_RESTORE_NON_TRAINING_ERROR
0xDD9D | SA | MRC_PRINT_INPUT_PARAMS_ERROR
0xDD9E | SA | MRC_SET_OVERRIDES_PSPD_ERROR
0xDDA0 | SA | MRC_SPD_PROCESSING_ERROR
0xDDA1 | SA | MRC_SET_OVERRIDES_ERROR
0xDDA2 | SA | MRC_MC_CAPABILITY_ERROR
0xDDA3 | SA | MRC_MC_CONFIG_ERROR
0xDDA4 | SA | MRC_MC_MEMORY_MAP_ERROR
0xDDA5 | SA | MRC_JEDEC_INIT_LPDDR3_ERROR
0xDDA6 | SA | MRC_RESET_ERROR
0xDDA7 | SA | MRC_PRE_TRAINING_ERROR
0xDDA8 | SA | MRC_EARLY_COMMAND_ERROR
0xDDA9 | SA | MRC_SENSE_AMP_OFFSET_ERROR
0xDDAA | SA | MRC_READ_MPR_ERROR
0xDDAB | SA | MRC_RECEIVE_ENABLE_ERROR
0xDDAC | SA | MRC_JEDEC_WRITE_LEVELING_ERROR
0xDDAD | SA | MRC_LPDDR_LATENCY_SET_B_ERROR
0xDDAE | SA | MRC_WRITE_TIMING_1D_ERROR
0xDDAF | SA | MRC_READ_TIMING_1D_ERROR
0xDDB0 | SA | MRC_DIMM_ODT_ERROR
0xDDB1 | SA | MRC_EARLY_WRITE_TIMING_ERROR
0xDDB2 | SA | MRC_WRITE_DS_ERROR
0xDDB3 | SA | MRC_WRITE_EQ_ERROR
0xDDB4 | SA | MRC_EARLY_READ_TIMING_ERROR
0xDDB5 | SA | MRC_READ_ODT_ERROR
0xDDB6 | SA | MRC_READ_EQ_ERROR
0xDDB7 | SA | MRC_READ_AMP_POWER_ERROR
0xDDB8 | SA | MRC_WRITE_TIMING_2D_ERROR
0xDDB9 | SA | MRC_READ_TIMING_2D_ERROR
0xDDBA | SA | MRC_CMD_VREF_ERROR
0xDDBB | SA | MRC_WRITE_VREF_2D_ERROR
0xDDBC | SA | MRC_READ_VREF_2D_ERROR
0xDDBD | SA | MRC_POST_TRAINING_ERROR
0xDDBE | SA | MRC_LATE_COMMAND_ERROR
0xDDBF | SA | MRC_ROUND_TRIP_LAT_ERROR
0xDDC0 | SA | MRC_TURN_AROUND_ERROR
0xDDC1 | SA | MRC_CMP_OPT_ERROR
0xDDC2 | SA | MRC_SAVE_MC_VALUES_ERROR
0xDDC3 | SA | MRC_RESTORE_TRAINING_ERROR
0xDDC4 | SA | MRC_RMT_TOOL_ERROR
0xDDC5 | SA | MRC_WRITE_SR_ERROR
0xDDC6 | SA | MRC_DIMM_RON_ERROR
0xDDC7 | SA | MRC_RCVEN_TIMING_1D_ERROR
0xDDC8 | SA | MRC_MR_FILL_ERROR
0xDDC9 | SA | MRC_PWR_MTR_ERROR
0xDDCA | SA | MRC_DDR4_MAPPING_ERROR
0xDDCB | SA | MRC_WRITE_VOLTAGE_1D_ERROR
0xDDCC | SA | MRC_EARLY_RDMPR_TIMING_2D_ERROR
0xDDCD | SA | MRC_FORCE_OLTM_ERROR
0xDDD0 | SA | MRC_MC_ACTIVATE_ERROR
0xDDD1 | SA | MRC_RH_PREVENTION_ERROR
0xDDD2 | SA | MRC_GET_MRC_DATA_ERROR
0xDDD3 | SA | Reserved
0xDDD8 | SA | MRC_RETRAIN_CHECK_ERROR
0xDDDA | SA | MRC_SA_GV_SWITCH_ERROR
0xDDDB | SA | MRC_ALIAS_CHECK_ERROR
0xDDDC | SA | MRC_ECC_CLEAN_ERROR
0xDDDD | SA | MRC_DONE_WITH_ERROR
0xDDDF | SA | MRC_CPGC_MEMORY_TEST_ERROR
0xDDE0 | SA | MRC_TXT_ALIAS_CHECK_ERROR
0xDDE1 | SA | MRC_ENG_PERF_GAIN_ERROR
0xDDE8 | SA | MRC_MEMORY_TEST_ERROR
0xDDE9 | SA | MRC_FILL_RMT_STRUCTURE_ERROR
0xDDF0 | SA | MRC_SELF_REFRESH_EXIT_ERROR
0xDDF1 | SA | MRC_MRC_NORMAL_MODE_ERROR
0xDDFD | SA | MRC_SSA_PRE_STOP_POINT_ERROR
0xDDFE | SA | MRC_NO_MEMORY_DETECTED

7.1.3 TempRamExit API Status Codes (0xBxxx)

PostCode | Module | Description
0xB800 | FSP | TempRamExit API Entry
0xB87F | FSP | TempRamExit API Exit

7.1.4 FspSiliconInit API Status Codes (0x9xxx)

PostCode | Module | Description
0x9800 | FSP | FspSiliconInit API Entry
0x987F | FSP | FspSiliconInit API Exit
0x9A00 | SA | PostMem SaInit Entry
0x9A01 | SA | DeviceConfigure Start
0x9A02 | SA | UpdateSaHobPostMem Start
0x9A03 | SA | Initializing Pei Display
0x9A04 | SA | PeiGraphicsNotifyCallback Entry
0x9A05 | SA | CallPpiAndFillFrameBuffer
0x9A06 | SA | GraphicsPpiInit
0x9A07 | SA | GraphicsPpiGetMode
0x9A08 | SA | FillFrameBufferAndShowLogo
0x9A0F | SA | PeiGraphicsNotifyCallback Exit
0x9A14 | SA | Initializing SA IPU device
0x9A16 | SA | Initializing SA GNA device
0x9A1A | SA | SaProgramLlcWays Start
0x9A20 | SA | Initializing PciExpressInitPostMem
0x9A22 | SA | Initializing ConfigureNorthIntelTraceHub
0x9A30 | SA | Initializing Vtd
0x9A31 | SA | Initializing TCSS
0x9A32 | SA | Initializing Pavp
0x9A34 | SA | PeiInstallSmmAccessPpi Start
0x9A36 | SA | EdramWa Start
0x9A4F | SA | Post-Mem SaInit Exit
0x9A50 | SA | SaSecurityLock Start
0x9A5F | SA | SaSecurityLock End
0x9A60 | SA | SaSResetComplete Entry
0x9A61 | SA | Set BIOS_RESET_CPL to indicate all configurations complete
0x9A62 | SA | SaSvInit2 Start
0x9A63 | SA | GraphicsPmInit Start
0x9A64 | SA | SaPciPrint Start
0x9A6F | SA | SaSResetComplete Exit
0x9A70 | SA | SaS3ResumeAtEndOfPei Callback Entry
0x9A7F | SA | SaS3ResumeAtEndOfPei Callback Exit
0x9B00 | PCH | Post-Mem PchInit Entry
0x9B03 | PCH | Post-Mem Tune the USB 2.0 high-speed signals quality
0x9B04 | PCH | Post-Mem Tune the USB 3.0 signals quality
0x9B05 | PCH | Post-Mem Configure PCH xHCI
0x9B06 | PCH | Post-Mem Performs configuration of PCH xHCI SSIC
0x9B07 | PCH | Post-Mem Configure PCH xHCI after init
0x9B08 | PCH | Post-Mem Configures PCH USB device (xDCI)
0x9B0A | PCH | Post-Mem DMI/OP-DMI configuration
0x9B0B | PCH | Post-Mem Initialize P2SB controller
0x9B0C | PCH | Post-Mem IOAPIC initialization
0x9B0D | PCH | Post-Mem PCH devices interrupt configuration
0x9B0E | PCH | Post-Mem HD Audio initizalization
0x9B0F | PCH | Post-Mem HD Audio Codec enumeration
0x9B10 | PCH | Post-Mem HD Audio Codec not detected
0x9B13 | PCH | Post-Mem SCS initizalization
0x9B14 | PCH | Post-Mem ISH initizalization
0x9B15 | PCH | Post-Mem Configure SMBUS power management
0x9B16 | PCH | Post-Mem Reserved
0x9B17 | PCH | Post-Mem Performing global reset
0x9B18 | PCH | Post-Mem Reserved
0x9B19 | PCH | Post-Mem Reserved
0x9B40 | PCH | Post-Mem OnEndOfPEI Entry
0x9B41 | PCH | Post-Mem Initialize Thermal controller
0x9B42 | PCH | Post-Mem Configure Memory Throttling
0x9B47 | PCH | Post-Mem OnEndOfPEI Exit
0x9B4D | PCH | Post-Mem Trace Hub - Memory configuration
0x9B4E | PCH | Post-Mem Trace Hub - MSC0 configured
0x9B4F | PCH | Post-Mem Trace Hub - MSC1 configured
0x9B7F | PCH | Post-Mem PchInit Exit
0x9C00 | CPU | CPU Post-Mem Entry
0x9C09 | CPU | CpuAddConfigBlocks Done
0x9C0A | CPU | SetCpuStrapAndEarlyPowerOnConfig Start
0x9C13 | CPU | SetCpuStrapAndEarlyPowerOnConfig Reset
0x9C14 | CPU | SetCpuStrapAndEarlyPowerOnConfig Done
0x9C15 | CPU | CpuInit Start
0x9C16 | CPU | SgxInitializationPrePatchLoad Start
0x9C17 | CPU | CollectProcessorFeature Start
0x9C18 | CPU | ProgramProcessorFeature Start
0x9C19 | CPU | ProgramProcessorFeature Done
0x9C20 | CPU | CpuInitPreResetCpl Start
0x9C21 | CPU | ProcessorsPrefetcherInitialization Start
0x9C22 | CPU | InitRatl Start
0x9C23 | CPU | ConfigureSvidVrs Start
0x9C24 | CPU | ConfigurePidSettings Start
0x9C25 | CPU | SetBootFrequency Start
0x9C26 | CPU | CpuOcInitPreMem Start
0x9C27 | CPU | CpuOcInit Reset
0x9C28 | CPU | BiosGuardInit Start
0x9C29 | CPU | BiosGuardInit Reset
0x9C3F | CPU | CpuInitPreResetCpl Done
0x9C42 | CPU | SgxActivation Start
0x9C43 | CPU | InitializeCpuDataHob Start
0x9C44 | CPU | InitializeCpuDataHob Done
0x9C4F | CPU | CpuInit Done
0x9C50 | CPU | S3InitializeCpu Start
0x9C55 | CPU | MpRendezvousProcedure Start
0x9C56 | CPU | MpRendezvousProcedure Done
0x9C69 | CPU | S3InitializeCpu Done
0x9C6A | CPU | CpuPowerMgmtInit Start
0x9C71 | CPU | InitPpm
0x9C7F | CPU | CPU Post-Mem Exit
0x9C80 | CPU | ReloadMicrocodePatch Start
0x9C81 | CPU | ReloadMicrocodePatch Done
0x9C82 | CPU | ApSafePostMicrocodePatchInit Start
0x9C83 | CPU | ApSafePostMicrocodePatchInit Done

7.1.5 NotifyPhase API Status Codes (0x6xxx)

PostCode | Module | Description
0x6800 | FSP | NotifyPhase API Entry
0x687F | FSP | NotifyPhase API Exit
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Todo List

Todo List
Page FSP INTEGRATION
program 0x1000000000 - Top of High Memory | Write back
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Deprecated List

Deprecated List
Member FSP_S_CONFIG::SkipMpInit
SkipMpInit has been moved to FspmUpd $EN_DIS
Member FSP_S_TEST_CONFIG::DebugInterfaceEnable
Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class List

  • Class List
  • Class Index
  • Class Members
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C AUDIO_AZALIA_VERB_TABLE | Audio Azalia Verb Table structure
C AZALIA_HEADER | Azalia Header structure
C CHIPSET_INIT_INFO | The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC
C DIMM_INFO | Memory SMBIOS & OC Memory Data Hob
C FIRMWARE_VERSION | Firmware Version Structure
C FIRMWARE_VERSION_INFO | Firmware Version Information Structure
C FIRMWARE_VERSION_INFO_HOB | Firmware Version Information HOB Structure
C FSP_M_CONFIG | Fsp M Configuration
C FSP_M_TEST_CONFIG | Fsp M Test Configuration
C FSP_S_CONFIG | Fsp S Configuration
C FSP_S_TEST_CONFIG | Fsp S Test Configuration
C FSP_T_CONFIG | Fsp T Configuration
C FSPM_UPD | Fsp M UPD Configuration
C FSPS_UPD | Fsp S UPD Configuration
C FSPT_CORE_UPD | Fsp T Core UPD
C FSPT_UPD | Fsp T UPD Configuration
C GPIO_CONFIG | GPIO configuration structure used for pin programming
C HOB_USAGE_DATA_HOB | Hob Usage Data Hob
C MEMORY_PLATFORM_DATA | Memory Platform Data Hob
C SI_PCH_DEVICE_INTERRUPT_CONFIG | The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device
C SMBIOS_CACHE_INFO | SMBIOS Cache Info HOB Structure
C SMBIOS_PROCESSOR_INFO | SMBIOS Processor Info HOB Structure
C SMBIOS_STRUCTURE | The Smbios structure header


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: AUDIO_AZALIA_VERB_TABLE Struct Reference

  • Class Index
  • Class Members
Public Attributes | List of all members
AUDIO_AZALIA_VERB_TABLE Struct Reference

Audio Azalia Verb Table structure. More...

#include <FspsUpd.h>

Collaboration diagram for AUDIO_AZALIA_VERB_TABLE:
[legend]

Public Attributes

AZALIA_HEADER Header
AZALIA PCH header.
UINT32 * Data
Pointer to the data buffer. Its length is specified in the header.

Detailed Description

Audio Azalia Verb Table structure.

Definition at line 56 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: AZALIA_HEADER Struct Reference

Public Attributes | List of all members
AZALIA_HEADER Struct Reference

Azalia Header structure. More...

#include <FspsUpd.h>

Public Attributes

UINT16 | VendorId
Codec Vendor ID.
UINT16 | DeviceId
Codec Device ID.
UINT8 | RevisionId
Revision ID of the codec. 0xFF matches any revision.
UINT8 | SdiNum
SDI number, 0xFF matches any SDI.
UINT16 | DataDwords
Number of data DWORDs pointed by the codec data buffer.
UINT32 | Reserved
Reserved for future use. Must be set to 0.

Detailed Description

Azalia Header structure.

Definition at line 44 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: CHIPSET_INIT_INFO Struct Reference

Public Attributes | List of all members
CHIPSET_INIT_INFO Struct Reference

The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. More...

#include <FspmUpd.h>

Public Attributes

UINT8 | Revision
Chipset Init Info Revision.
UINT8 | Rsvd [3]
Reserved.
UINT16 | MeChipInitCrc
16 bit CRC value of MeChipInit Table
UINT16 | BiosChipInitCrc
16 bit CRC value of PchChipInit Table

Detailed Description

The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.

Definition at line 46 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: DIMM_INFO Struct Reference

Public Attributes | List of all members
DIMM_INFO Struct Reference

Memory SMBIOS & OC Memory Data Hob. More...

#include <MemInfoHob.h>

Public Attributes

UINT8 | Status
See MrcDimmStatus for the definition of this field.
UINT32 | DimmCapacity
DIMM size in MBytes.
UINT8 | ModulePartNum [20]
Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes.
UINT8 | RankInDimm
The number of ranks in this DIMM.
UINT8 | SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 | SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 | SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 | SpdSave [MAX_SPD_SAVE]
Save SPD Manufacturing information needed for SMBIOS structure creation.
UINT16 | Speed
The maximum capable speed of the device, in MHz.

Detailed Description

Memory SMBIOS & OC Memory Data Hob.

Definition at line 175 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FIRMWARE_VERSION Struct Reference

List of all members
FIRMWARE_VERSION Struct Reference

Firmware Version Structure. More...

#include <FirmwareVersionInfoHob.h>

Detailed Description

Firmware Version Structure.

Definition at line 28 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FIRMWARE_VERSION_INFO Struct Reference

Public Attributes | List of all members
FIRMWARE_VERSION_INFO Struct Reference

Firmware Version Information Structure. More...

#include <FirmwareVersionInfoHob.h>

Collaboration diagram for FIRMWARE_VERSION_INFO:
[legend]

Public Attributes

UINT8 | ComponentNameIndex
Offset 0 Index of Component Name.
UINT8 | VersionStringIndex
Offset 1 Index of Version String.
FIRMWARE_VERSION Version
Offset 2-6 Firmware version.

Detailed Description

Firmware Version Information Structure.

Definition at line 38 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FIRMWARE_VERSION_INFO_HOB Struct Reference

Public Attributes | List of all members
FIRMWARE_VERSION_INFO_HOB Struct Reference

Firmware Version Information HOB Structure. More...

#include <FirmwareVersionInfoHob.h>

Collaboration diagram for FIRMWARE_VERSION_INFO_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE | Header
Offset 0-23 The header of FVI HOB.
SMBIOS_STRUCTURE SmbiosData
Offset 24-27 The SMBIOS header of FVI HOB.
UINT8 | Count
Offset 28 Number of FVI elements included. More...

Detailed Description

Firmware Version Information HOB Structure.

Definition at line 58 of file FirmwareVersionInfoHob.h.

Member Data Documentation

UINT8 FIRMWARE_VERSION_INFO_HOB::Count

Offset 28 Number of FVI elements included.

Definition at line 61 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_M_CONFIG Struct Reference

Public Attributes | List of all members
FSP_M_CONFIG Struct Reference

Fsp M Configuration. More...

#include <FspmUpd.h>

Public Attributes

UINT64 | PlatformMemorySize
Offset 0x0040 - Platform Reserved Memory Size The minimum platform memory size required to pass control into DXE.
UINT32 | MemorySpdPtr00
Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00.
UINT32 | MemorySpdPtr01
Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00.
UINT32 | MemorySpdPtr10
Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00.
UINT32 | MemorySpdPtr11
Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00.
UINT16 | MemorySpdDataLen
Offset 0x0058 - SPD Data Length Length of SPD Data 0x100:256 Bytes, 0x200:512 Bytes.
UINT8 | DqByteMapCh0 [12]
Offset 0x005A - Dq Byte Map CH0 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent.
UINT8 | DqByteMapCh1 [12]
Offset 0x0066 - Dq Byte Map CH1 Dq byte mapping between CPU and DRAM, Channel 1: board-dependent.
UINT8 | DqsMapCpu2DramCh0 [8]
Offset 0x0072 - Dqs Map CPU to DRAM CH 0 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent.
UINT8 | DqsMapCpu2DramCh1 [8]
Offset 0x007A - Dqs Map CPU to DRAM CH 1 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent.
UINT16 | RcompResistor [3]
Offset 0x0082 - RcompResister settings Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. More...
UINT16 | RcompTarget [5]
Offset 0x0088 - RcompTarget settings RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment. More...
UINT8 | DqPinsInterleaved
Offset 0x0092 - Dqs Pins Interleaved Setting Indicates DqPinsInterleaved setting: board-dependent $EN_DIS.
UINT8 | CaVrefConfig
Offset 0x0093 - VREF_CA CA Vref routing: board-dependent 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 2:VREF_CA to CH_A and VREF_DQ_B to CH_B.
UINT8 | SmramMask
Offset 0x0094 - Smram Mask The SMM Regions AB-SEG and/or H-SEG reserved 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both.
UINT8 | MrcFastBoot
Offset 0x0095 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC $EN_DIS.
UINT8 | RmtPerTask
Offset 0x0096 - Rank Margin Tool per Task This option enables the user to execute Rank Margin Tool per major training step in the MRC. More...
UINT8 | TrainTrace
Offset 0x0097 - Training Trace This option enables the trained state tracing feature in MRC. More...
UINT32 | IedSize
Offset 0x0098 - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied 0 : Disable, 0x400000 : Enable.
UINT32 | TsegSize
Offset 0x009C - Tseg Size Size of SMRAM memory reserved. More...
UINT16 | MmioSize
Offset 0x00A0 - MMIO Size Size of MMIO space reserved for devices. More...
UINT8 | ProbelessTrace
Offset 0x00A2 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable. More...
UINT8 | GdxcIotSize
Offset 0x00A3 - GDXC IOT SIZE Size of IOT and MOT is in 8 MB chunks.
UINT8 | GdxcMotSize
Offset 0x00A4 - GDXC MOT SIZE Size of IOT and MOT is in 8 MB chunks.
UINT8 | SmbusEnable
Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller. More...
UINT8 | SpdAddressTable [4]
Offset 0x00A6 - Spd Address Tabl Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. More...
UINT8 | PlatformDebugConsent
Offset 0x00AA - Platform Debug Consent To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. More...
UINT8 | DciUsb3TypecUfpDbg
Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. More...
UINT8 | PchTraceHubMode
Offset 0x00AC - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. More...
UINT8 | PchTraceHubMemReg0Size
Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. More...
UINT8 | PchTraceHubMemReg1Size
Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. More...
UINT8 | PchPreMemRsvd [9]
Offset 0x00AF - PchPreMemRsvd Reserved for PCH Pre-Mem Reserved $EN_DIS.
UINT8 | IgdDvmt50PreAlloc
Offset 0x00B8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. More...
UINT8 | InternalGfx
Offset 0x00B9 - Internal Graphics Enable/disable internal graphics. More...
UINT8 | ApertureSize
Offset 0x00BA - Aperture Size Select the Aperture Size. More...
UINT8 | UserBd
Offset 0x00BB - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server.
UINT8 | SaGv
Offset 0x00BC - SA GV System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. More...
UINT8 | UnusedUpdSpace0
Offset 0x00BD.
UINT16 | DdrFreqLimit
Offset 0x00BE - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. More...
UINT16 | FreqSaGvLow
Offset 0x00C0 - Low Frequency SAGV Low Frequency Selections in Mhz. More...
UINT16 | FreqSaGvMid
Offset 0x00C2 - Mid Frequency SAGV Mid Frequency Selections in Mhz. More...
UINT8 | RMT
Offset 0x00C4 - Rank Margin Tool Enable/disable Rank Margin Tool. More...
UINT8 | DisableDimmChannel0
Offset 0x00C5 - Channel A DIMM Control Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. More...
UINT8 | DisableDimmChannel1
Offset 0x00C6 - Channel B DIMM Control Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. More...
UINT8 | ScramblerSupport
Offset 0x00C7 - Scrambler Support This option enables data scrambling in memory. More...
UINT8 | SkipMpInit
Offset 0x00C8 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. More...
UINT8 | UnusedUpdSpace1 [15]
Offset 0x00C9.
UINT8 | SpdProfileSelected
Offset 0x00D8 - SPD Profile Selected Select DIMM timing profile. More...
UINT8 | RefClk
Offset 0x00D9 - Memory Reference Clock 100MHz, 133MHz. More...
UINT16 | VddVoltage
Offset 0x00DA - Memory Voltage Memory Voltage Override (Vddq). More...
UINT8 | Ratio
Offset 0x00DC - Memory Ratio Automatic or the frequency will equal ratio times reference clock. More...
UINT8 | OddRatioMode
Offset 0x00DD - QCLK Odd Ratio Adds 133 or 100 MHz to QCLK frequency, depending on RefClk $EN_DIS.
UINT8 | tCL
Offset 0x00DE - tCL CAS Latency, 0: AUTO, max: 31.
UINT8 | tCWL
Offset 0x00DF - tCWL Min CAS Write Latency Delay Time, 0: AUTO, max: 34.
UINT8 | tRCDtRP
Offset 0x00E0 - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63.
UINT8 | tRRD
Offset 0x00E1 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 15.
UINT16 | tFAW
Offset 0x00E2 - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63.
UINT16 | tRAS
Offset 0x00E4 - tRAS RAS Active Time, 0: AUTO, max: 64.
UINT16 | tREFI
Offset 0x00E6 - tREFI Refresh Interval, 0: AUTO, max: 65535.
UINT16 | tRFC
Offset 0x00E8 - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 1023.
UINT8 | tRTP
Offset 0x00EA - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. More...
UINT8 | tWR
Offset 0x00EB - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, 34:34, 40:40.
UINT8 | tWTR
Offset 0x00EC - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28.
UINT8 | NModeSupport
Offset 0x00ED - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N.
UINT8 | DllBwEn0
Offset 0x00EE - DllBwEn[0] DllBwEn[0], for 1067 (0..7)
UINT8 | DllBwEn1
Offset 0x00EF - DllBwEn[1] DllBwEn[1], for 1333 (0..7)
UINT8 | DllBwEn2
Offset 0x00F0 - DllBwEn[2] DllBwEn[2], for 1600 (0..7)
UINT8 | DllBwEn3
Offset 0x00F1 - DllBwEn[3] DllBwEn[3], for 1867 and up (0..7)
UINT8 | IsvtIoPort
Offset 0x00F2 - ISVT IO Port Address ISVT IO Port Address. More...
UINT8 | CpuTraceHubMode
Offset 0x00F3 - CPU Trace Hub Mode Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. More...
UINT8 | CpuTraceHubMemReg0Size
Offset 0x00F4 - CPU Trace Hub Memory Region 0 CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. More...
UINT8 | CpuTraceHubMemReg1Size
Offset 0x00F5 - CPU Trace Hub Memory Region 1 CPU Trace Hub Memory Region 1. More...
UINT8 | PeciC10Reset
Offset 0x00F6 - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command. More...
UINT8 | PeciSxReset
Offset 0x00F7 - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. More...
UINT8 | UnusedUpdSpace2 [4]
Offset 0x00F8.
UINT8 | PchHdaEnable
Offset 0x00FC - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_DIS.
UINT8 | PchIshEnable
Offset 0x00FD - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller $EN_DIS.
UINT8 | HeciTimeouts
Offset 0x00FE - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS.
UINT8 | UnusedUpdSpace3
Offset 0x00FF.
UINT32 | Heci1BarAddress
Offset 0x0100 - HECI1 BAR address BAR address of HECI1.
UINT32 | Heci2BarAddress
Offset 0x0104 - HECI2 BAR address BAR address of HECI2.
UINT32 | Heci3BarAddress
Offset 0x0108 - HECI3 BAR address BAR address of HECI3.
UINT16 | SgDelayAfterPwrEn
Offset 0x010C - SG dGPU Power Delay SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds.
UINT16 | SgDelayAfterHoldReset
Offset 0x010E - SG dGPU Reset Delay SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds.
UINT16 | MmioSizeAdjustment
Offset 0x0110 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size.
UINT8 | DmiGen3ProgramStaticEq
Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Static Presets. More...
UINT8 | Peg0Enable
Offset 0x0113 - Enable/Disable PEG 0 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO.
UINT8 | Peg1Enable
Offset 0x0114 - Enable/Disable PEG 1 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO.
UINT8 | Peg2Enable
Offset 0x0115 - Enable/Disable PEG 2 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO.
UINT8 | Peg3Enable
Offset 0x0116 - Enable/Disable PEG 3 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable, 1:Enable, 2:AUTO.
UINT8 | Peg0MaxLinkSpeed
Offset 0x0117 - PEG 0 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | Peg1MaxLinkSpeed
Offset 0x0118 - PEG 1 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | Peg2MaxLinkSpeed
Offset 0x0119 - PEG 2 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | Peg3MaxLinkSpeed
Offset 0x011A - PEG 3 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | Peg0MaxLinkWidth
Offset 0x011B - PEG 0 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8.
UINT8 | Peg1MaxLinkWidth
Offset 0x011C - PEG 1 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4 0:Auto, 1:x1, 2:x2, 3:x4.
UINT8 | Peg2MaxLinkWidth
Offset 0x011D - PEG 2 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
UINT8 | Peg3MaxLinkWidth
Offset 0x011E - PEG 3 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
UINT8 | Peg0PowerDownUnusedLanes
Offset 0x011F - Power down unused lanes on PEG 0 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 | Peg1PowerDownUnusedLanes
Offset 0x0120 - Power down unused lanes on PEG 1 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 | Peg2PowerDownUnusedLanes
Offset 0x0121 - Power down unused lanes on PEG 2 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 | Peg3PowerDownUnusedLanes
Offset 0x0122 - Power down unused lanes on PEG 3 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 | InitPcieAspmAfterOprom
Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM programming will happen in relation to the Oprom. More...
UINT8 | PegDisableSpreadSpectrumClocking
Offset 0x0124 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking. More...
UINT8 | UnusedUpdSpace4 [3]
Offset 0x0125.
UINT8 | DmiGen3RootPortPreset [8]
Offset 0x0128 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. More...
UINT8 | DmiGen3EndPointPreset [8]
Offset 0x0130 - DMI Gen3 End port preset values per lane Used for programming DMI Gen3 preset values per lane. More...
UINT8 | DmiGen3EndPointHint [8]
Offset 0x0138 - DMI Gen3 End port Hint values per lane Used for programming DMI Gen3 Hint values per lane. More...
UINT8 | DmiGen3RxCtlePeaking [4]
Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control Range: 0-15, 0 is default for each bundle, must be specified based upon platform design.
UINT8 | TvbRatioClipping
Offset 0x0144 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled. More...
UINT8 | TvbVoltageOptimization
Offset 0x0145 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default). More...
UINT8 | UnusedUpdSpace5 [2]
Offset 0x0146.
UINT8 | PegGen3RxCtlePeaking [10]
Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control Range: 0-15, 12 is default for each bundle, must be specified based upon platform design.
UINT32 | PegDataPtr
Offset 0x0152 - Memory data pointer for saved preset search results The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots. More...
UINT8 | PegGpioData [28]
Offset 0x0156 - PEG PERST# GPIO information The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary.
UINT8 | PegRootPortHPE [4]
Offset 0x0172 - PCIe Hot Plug Enable/Disable per port 0(Default): Disable, 1: Enable.
UINT8 | DmiDeEmphasis
Offset 0x0176 - DeEmphasis control for DMI DeEmphasis control for DMI. More...
UINT8 | PrimaryDisplay
Offset 0x0177 - Selection of the primary display device 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics.
UINT16 | GttSize
Offset 0x0178 - Selection of iGFX GTT Memory size 1=2MB, 2=4MB, 3=8MB, Default is 3 1:2MB, 2:4MB, 3:8MB.
UINT32 | GmAdr
Offset 0x017A - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize). More...
UINT32 | GttMmAdr
Offset 0x017E - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). More...
UINT8 | PsmiRegionSize
Offset 0x0182 - Selection of PSMI Region size 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB.
UINT8 | SaRtd3Pcie0Gpio [24]
Offset 0x0183 - Switchable Graphics GPIO information for PEG 0 Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs.
UINT8 | SaRtd3Pcie1Gpio [24]
Offset 0x019B - Switchable Graphics GPIO information for PEG 1 Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs.
UINT8 | SaRtd3Pcie2Gpio [24]
Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2 Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs.
UINT8 | SaRtd3Pcie3Gpio [24]
Offset 0x01CB - Switchable Graphics GPIO information for PEG 3 Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs.
UINT8 | TxtImplemented
Offset 0x01E3 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. More...
UINT8 | SaOcSupport
Offset 0x01E4 - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport $EN_DIS.
UINT8 | GtVoltageMode
Offset 0x01E5 - GT slice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
UINT8 | GtMaxOcRatio
Offset 0x01E6 - Maximum GTs turbo ratio override 0(Default)=Minimal/Auto, 60=Maximum.
UINT16 | GtVoltageOffset
Offset 0x01E7 - The voltage offset applied to GT slice 0(Default)=Minimal, 1000=Maximum.
UINT16 | GtVoltageOverride
Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 | GtExtraTurboVoltage
Offset 0x01EB - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 | SaVoltageOffset
Offset 0x01ED - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum.
UINT8 | RootPortIndex
Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU Root port Index number to indicate which PCIe root port has dGPU.
UINT8 | RealtimeMemoryTiming
Offset 0x01F0 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled. More...
UINT8 | SaIpuEnable
Offset 0x01F1 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU $EN_DIS.
UINT8 | SaIpuImrConfiguration
Offset 0x01F2 - IPU IMR Configuration 0:IPU Camera, 1:IPU Gen Default is 0 0:IPU Camera, 1:IPU Gen.
UINT8 | GtPsmiSupport
Offset 0x01F3 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE. More...
UINT8 | GtusVoltageMode
Offset 0x01F4 - GT unslice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
UINT16 | GtusVoltageOffset
Offset 0x01F5 - voltage offset applied to GT unslice 0(Default)=Minimal, 2000=Maximum.
UINT16 | GtusVoltageOverride
Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 | GtusExtraTurboVoltage
Offset 0x01F9 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
UINT8 | GtusMaxOcRatio
Offset 0x01FB - Maximum GTus turbo ratio override 0(Default)=Minimal, 60=Maximum.
UINT8 | SaPreMemProductionRsvd [4]
Offset 0x01FC - SaPreMemProductionRsvd Reserved for SA Pre-Mem Production $EN_DIS.
UINT8 | BistOnReset
Offset 0x0200 - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable. More...
UINT8 | SkipStopPbet
Offset 0x0201 - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_DIS.
UINT8 | EnableC6Dram
Offset 0x0202 - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature. More...
UINT8 | OcSupport
Offset 0x0203 - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS.
UINT8 | OcLock
Offset 0x0204 - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. More...
UINT8 | CoreMaxOcRatio
Offset 0x0205 - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit. More...
UINT8 | CoreVoltageMode
Offset 0x0206 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override. More...
UINT8 | DisableMtrrProgram
Offset 0x0207 - Program Cache Attributes Program Cache Attributes; 0: Program; 1: Disable Program. More...
UINT8 | RingMaxOcRatio
Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. More...
UINT8 | HyperThreading
Offset 0x0209 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable $EN_DIS.
UINT8 | CpuRatio
Offset 0x020A - CPU ratio value CPU ratio value. More...
UINT8 | BootFrequency
Offset 0x020B - Boot frequency Sets the boot frequency starting from reset vector. More...
UINT8 | ActiveCoreCount
Offset 0x020C - Number of active cores Number of active cores(Depends on Number of cores). More...
UINT8 | FClkFrequency
Offset 0x020D - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). More...
UINT8 | JtagC10PowerGateDisable
Offset 0x020E - Set JTAG power in C10 and deeper power states False: JTAG is power gated in C10 state. More...
UINT8 | VmxEnable
Offset 0x020F - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. More...
UINT8 | Avx2RatioOffset
Offset 0x0210 - AVX2 Ratio Offset 0(Default)= No Offset. More...
UINT8 | Avx3RatioOffset
Offset 0x0211 - AVX3 Ratio Offset 0(Default)= No Offset. More...
UINT8 | BclkAdaptiveVoltage
Offset 0x0212 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. More...
UINT8 | CorePllVoltageOffset
Offset 0x0213 - Core PLL voltage offset Core PLL voltage offset. More...
UINT16 | CoreVoltageOverride
Offset 0x0214 - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies. More...
UINT16 | CoreVoltageAdaptive
Offset 0x0216 - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. More...
UINT16 | CoreVoltageOffset
Offset 0x0218 - Core Turbo voltage Offset The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000.
UINT8 | RingDownBin
Offset 0x021A - Ring Downbin Ring Downbin enable/disable. More...
UINT8 | RingVoltageMode
Offset 0x021B - Ring voltage mode Ring voltage mode; 0: Adaptive; 1: Override. More...
UINT16 | RingVoltageOverride
Offset 0x021C - Ring voltage override The ring voltage override which is applied to the entire range of cpu ring frequencies. More...
UINT16 | RingVoltageAdaptive
Offset 0x021E - Ring Turbo voltage Adaptive Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. More...
UINT16 | RingVoltageOffset
Offset 0x0220 - Ring Turbo voltage Offset The voltage offset applied to the ring while operating in turbo mode. More...
UINT8 | TjMaxOffset
Offset 0x0222 - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. More...
UINT8 | BiosGuard
Offset 0x0223 - BiosGuard Enable/Disable. More...
UINT8 | BiosGuardToolsInterface
Offset 0x0224.
UINT8 | EnableSgx
Offset 0x0225 - EnableSgx Enable/Disable. More...
UINT8 | Txt
Offset 0x0226 - Txt Enable/Disable. More...
UINT8 | UnusedUpdSpace6
Offset 0x0227.
UINT32 | PrmrrSize
Offset 0x0228 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000.
UINT32 | SinitMemorySize
Offset 0x022C - SinitMemorySize Enable/Disable. More...
UINT32 | TxtHeapMemorySize
Offset 0x0230 - TxtHeapMemorySize Enable/Disable. More...
UINT32 | TxtDprMemorySize
Offset 0x0234 - TxtDprMemorySize Enable/Disable. More...
UINT64 | TxtDprMemoryBase
Offset 0x0238 - TxtDprMemoryBase Enable/Disable. More...
UINT32 | BiosAcmBase
Offset 0x0240 - BiosAcmBase Enable/Disable. More...
UINT32 | BiosAcmSize
Offset 0x0244 - BiosAcmSize Enable/Disable. More...
UINT32 | ApStartupBase
Offset 0x0248 - ApStartupBase Enable/Disable. More...
UINT32 | TgaSize
Offset 0x024C - TgaSize Enable/Disable. More...
UINT64 | TxtLcpPdBase
Offset 0x0250 - TxtLcpPdBase Enable/Disable. More...
UINT64 | TxtLcpPdSize
Offset 0x0258 - TxtLcpPdSize Enable/Disable. More...
UINT8 | IsTPMPresence
Offset 0x0260 - IsTPMPresence IsTPMPresence default values.
UINT8 | ReservedSecurityPreMem [15]
Offset 0x0261 - ReservedSecurityPreMem Reserved for Security Pre-Mem $EN_DIS.
UINT8 | PchPcieHsioRxSetCtleEnable [24]
Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value.
UINT8 | PchPcieHsioRxSetCtle [24]
Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value PCH PCIe Gen 3 Set CTLE Value.
UINT8 | PchPcieHsioTxGen1DownscaleAmpEnable [24]
Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen1DownscaleAmp [24]
Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
UINT8 | PchPcieHsioTxGen2DownscaleAmpEnable [24]
Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen2DownscaleAmp [24]
Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
UINT8 | PchPcieHsioTxGen3DownscaleAmpEnable [24]
Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen3DownscaleAmp [24]
Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
UINT8 | PchPcieHsioTxGen1DeEmphEnable [24]
Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen1DeEmph [24]
Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
UINT8 | PchPcieHsioTxGen2DeEmph3p5Enable [24]
Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen2DeEmph3p5 [24]
Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
UINT8 | PchPcieHsioTxGen2DeEmph6p0Enable [24]
Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchPcieHsioTxGen2DeEmph6p0 [24]
Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
UINT8 | PchSataHsioRxGen1EqBoostMagEnable [8]
Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioRxGen1EqBoostMag [8]
Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 | PchSataHsioRxGen2EqBoostMagEnable [8]
Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioRxGen2EqBoostMag [8]
Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 | PchSataHsioRxGen3EqBoostMagEnable [8]
Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioRxGen3EqBoostMag [8]
Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 | PchSataHsioTxGen1DownscaleAmpEnable [8]
Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen1DownscaleAmp [8]
Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 | PchSataHsioTxGen2DownscaleAmpEnable [8]
Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen2DownscaleAmp [8]
Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 | PchSataHsioTxGen3DownscaleAmpEnable [8]
Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen3DownscaleAmp [8]
Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 | PchSataHsioTxGen1DeEmphEnable [8]
Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen1DeEmph [8]
Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT8 | PchSataHsioTxGen2DeEmphEnable [8]
Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen2DeEmph [8]
Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT8 | PchSataHsioTxGen3DeEmphEnable [8]
Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable.
UINT8 | PchSataHsioTxGen3DeEmph [8]
Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT8 | PchLpcEnhancePort8xhDecoding
Offset 0x0450 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h. More...
UINT8 | PchPort80Route
Offset 0x0451 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. More...
UINT8 | SmbusArpEnable
Offset 0x0452 - Enable SMBus ARP support Enable SMBus ARP support. More...
UINT8 | PchNumRsvdSmbusAddresses
Offset 0x0453 - Number of RsvdSmbusAddressTable. More...
UINT16 | PchSmbusIoBase
Offset 0x0454 - SMBUS Base Address SMBUS Base Address (IO space).
UINT16 | PcieImrSize
Offset 0x0456 - Size of PCIe IMR. More...
UINT32 | RsvdSmbusAddressTablePtr
Offset 0x0458 - Point of RsvdSmbusAddressTable Array of addresses reserved for non-ARP-capable SMBus devices.
UINT32 | PcieRpEnableMask
Offset 0x045C - Enable PCIE RP Mask Enable/disable PCIE Root Ports. More...
UINT8 | PcieImrEnabled
Offset 0x0460 - Enable PCIe IMR 0:Disable, 1:Enable $EN_DIS.
UINT8 | ImrRpSelection
Offset 0x0461 - Root port number for IMR. More...
UINT8 | PchSmbAlertEnable
Offset 0x0462 - Enable SMBus Alert Pin Enable SMBus Alert Pin. More...
UINT8 | ReservedPchPreMem [13]
Offset 0x0463 - ReservedPchPreMem Reserved for Pch Pre-Mem $EN_DIS.
UINT8 | PcdDebugInterfaceFlags
Offset 0x0470 - Debug Interfaces Debug Interfaces. More...
UINT8 | PcdSerialIoUartNumber
Offset 0x0471 - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug. More...
UINT8 | PcdIsaSerialUartBase
Offset 0x0472 - ISA Serial Base selection Select ISA Serial Base address. More...
UINT8 | GtPllVoltageOffset
Offset 0x0473 - GT PLL voltage offset Core PLL voltage offset. More...
UINT8 | RingPllVoltageOffset
Offset 0x0474 - Ring PLL voltage offset Core PLL voltage offset. More...
UINT8 | SaPllVoltageOffset
Offset 0x0475 - System Agent PLL voltage offset Core PLL voltage offset. More...
UINT8 | McPllVoltageOffset
Offset 0x0476 - Memory Controller PLL voltage offset Core PLL voltage offset. More...
UINT8 | MrcSafeConfig
Offset 0x0477 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS.
UINT8 | PcdSerialDebugBaudRate
Offset 0x0478 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. More...
UINT8 | HobBufferSize
Offset 0x0479 - HobBufferSize Size to set HOB Buffer. More...
UINT8 | ECT
Offset 0x047A - Early Command Training Enables/Disable Early Command Training $EN_DIS.
UINT8 | SOT
Offset 0x047B - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS.
UINT8 | ERDMPRTC2D
Offset 0x047C - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $EN_DIS.
UINT8 | RDMPRT
Offset 0x047D - Read MPR Training Enables/Disable Read MPR Training $EN_DIS.
UINT8 | RCVET
Offset 0x047E - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS.
UINT8 | JWRL
Offset 0x047F - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS.
UINT8 | EWRTC2D
Offset 0x0480 - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS.
UINT8 | ERDTC2D
Offset 0x0481 - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS.
UINT8 | WRTC1D
Offset 0x0482 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS.
UINT8 | WRVC1D
Offset 0x0483 - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS.
UINT8 | RDTC1D
Offset 0x0484 - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS.
UINT8 | DIMMODTT
Offset 0x0485 - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS.
UINT8 | DIMMRONT
Offset 0x0486 - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS.
UINT8 | WRDSEQT
Offset 0x0487 - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalization 2D $EN_DIS.
UINT8 | WRSRT
Offset 0x0488 - Write Slew Rate Training Enables/Disable Write Slew Rate Training $EN_DIS.
UINT8 | RDODTT
Offset 0x0489 - Read ODT Training Enables/Disable Read ODT Training $EN_DIS.
UINT8 | RDEQT
Offset 0x048A - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS.
UINT8 | RDAPT
Offset 0x048B - Read Amplifier Training Enables/Disable Read Amplifier Training $EN_DIS.
UINT8 | WRTC2D
Offset 0x048C - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS.
UINT8 | RDTC2D
Offset 0x048D - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS.
UINT8 | WRVC2D
Offset 0x048E - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS.
UINT8 | RDVC2D
Offset 0x048F - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS.
UINT8 | CMDVC
Offset 0x0490 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS.
UINT8 | LCT
Offset 0x0491 - Late Command Training Enables/Disable Late Command Training $EN_DIS.
UINT8 | RTL
Offset 0x0492 - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS.
UINT8 | TAT
Offset 0x0493 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS.
UINT8 | MEMTST
Offset 0x0494 - Memory Test Enables/Disable Memory Test $EN_DIS.
UINT8 | ALIASCHK
Offset 0x0495 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS.
UINT8 | RCVENC1D
Offset 0x0496 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS.
UINT8 | RMC
Offset 0x0497 - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS.
UINT8 | WRDSUDT
Offset 0x0498 - Write Drive Strength Up/Dn independently Enables/Disable Write Drive Strength Up/Dn independently $EN_DIS.
UINT8 | EccSupport
Offset 0x0499 - ECC Support Enables/Disable ECC Support $EN_DIS.
UINT8 | RemapEnable
Offset 0x049A - Memory Remap Enables/Disable Memory Remap $EN_DIS.
UINT8 | RankInterleave
Offset 0x049B - Rank Interleave support Enables/Disable Rank Interleave support. More...
UINT8 | EnhancedInterleave
Offset 0x049C - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS.
UINT8 | MemoryTrace
Offset 0x049D - Memory Trace Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. More...
UINT8 | ChHashEnable
Offset 0x049E - Ch Hash Support Enable/Disable Channel Hash Support. More...
UINT8 | EnableExtts
Offset 0x049F - Extern Therm Status Enables/Disable Extern Therm Status $EN_DIS.
UINT8 | EnableCltm
Offset 0x04A0 - Closed Loop Therm Manage Enables/Disable Closed Loop Therm Manage $EN_DIS.
UINT8 | EnableOltm
Offset 0x04A1 - Open Loop Therm Manage Enables/Disable Open Loop Therm Manage $EN_DIS.
UINT8 | EnablePwrDn
Offset 0x04A2 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter $EN_DIS.
UINT8 | EnablePwrDnLpddr
Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS.
UINT8 | UserPowerWeightsEn
Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values Enables/Disable Use user provided power weights, scale factor, and channel power floor values $EN_DIS.
UINT8 | RaplLim2Lock
Offset 0x04A5 - RAPL PL Lock Enables/Disable RAPL PL Lock $EN_DIS.
UINT8 | RaplLim2Ena
Offset 0x04A6 - RAPL PL 2 enable Enables/Disable RAPL PL 2 enable $EN_DIS.
UINT8 | RaplLim1Ena
Offset 0x04A7 - RAPL PL 1 enable Enables/Disable RAPL PL 1 enable $EN_DIS.
UINT8 | SrefCfgEna
Offset 0x04A8 - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS.
UINT8 | ThrtCkeMinDefeatLpddr
Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) $EN_DIS.
UINT8 | ThrtCkeMinDefeat
Offset 0x04AA - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS.
UINT8 | RhPrevention
Offset 0x04AB - Enable RH Prevention Enables/Disable RH Prevention $EN_DIS.
UINT8 | ExitOnFailure
Offset 0x04AC - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS.
UINT8 | DdrThermalSensor
Offset 0x04AD - LPDDR Thermal Sensor Enables/Disable LPDDR Thermal Sensor $EN_DIS.
UINT8 | Ddr4DdpSharedClock
Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS.
UINT8 | Ddr4DdpSharedZq
Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS.
UINT16 | ChHashMask
Offset 0x04B0 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. More...
UINT32 | BClkFrequency
Offset 0x04B2 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz.
UINT8 | ChHashInterleaveBit
Offset 0x04B6 - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode. More...
UINT8 | EnergyScaleFact
Offset 0x04B7 - Energy Scale Factor Energy Scale Factor, Default is 4.
UINT16 | Idd3n
Offset 0x04B8 - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet. More...
UINT16 | Idd3p
Offset 0x04BA - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet. More...
UINT8 | CMDSR
Offset 0x04BC - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS.
UINT8 | CMDDSEQ
Offset 0x04BD - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization $EN_DIS.
UINT8 | CMDNORM
Offset 0x04BE - CMD Normalization Enable/Disable CMD Normalization $EN_DIS.
UINT8 | EWRDSEQ
Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write Drive Strength and Equalization Training $EN_DIS.
UINT8 | RhActProbability
Offset 0x04C0 - RH Activation Probability RH Activation Probability, Probability value is 1/2^(inputvalue)
UINT8 | RaplLim2WindX
Offset 0x04C1 - RAPL PL 2 WindowX Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
UINT8 | RaplLim2WindY
Offset 0x04C2 - RAPL PL 2 WindowY Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
UINT8 | RaplLim1WindX
Offset 0x04C3 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
UINT8 | RaplLim1WindY
Offset 0x04C4 - RAPL PL 1 WindowY Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
UINT16 | RaplLim2Pwr
Offset 0x04C5 - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (222= Def)
UINT16 | RaplLim1Pwr
Offset 0x04C7 - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (0= Def)
UINT8 | WarmThresholdCh0Dimm0
Offset 0x04C9 - Warm Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | WarmThresholdCh0Dimm1
Offset 0x04CA - Warm Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | WarmThresholdCh1Dimm0
Offset 0x04CB - Warm Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | WarmThresholdCh1Dimm1
Offset 0x04CC - Warm Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | HotThresholdCh0Dimm0
Offset 0x04CD - Hot Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | HotThresholdCh0Dimm1
Offset 0x04CE - Hot Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | HotThresholdCh1Dimm0
Offset 0x04CF - Hot Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | HotThresholdCh1Dimm1
Offset 0x04D0 - Hot Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. More...
UINT8 | WarmBudgetCh0Dimm0
Offset 0x04D1 - Warm Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | WarmBudgetCh0Dimm1
Offset 0x04D2 - Warm Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | WarmBudgetCh1Dimm0
Offset 0x04D3 - Warm Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | WarmBudgetCh1Dimm1
Offset 0x04D4 - Warm Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | HotBudgetCh0Dimm0
Offset 0x04D5 - Hot Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | HotBudgetCh0Dimm1
Offset 0x04D6 - Hot Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | HotBudgetCh1Dimm0
Offset 0x04D7 - Hot Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | HotBudgetCh1Dimm1
Offset 0x04D8 - Hot Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 | IdleEnergyCh0Dimm0
Offset 0x04D9 - Idle Energy Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 | IdleEnergyCh0Dimm1
Offset 0x04DA - Idle Energy Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 | IdleEnergyCh1Dimm0
Offset 0x04DB - Idle Energy Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 | IdleEnergyCh1Dimm1
Offset 0x04DC - Idle Energy Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 | PdEnergyCh0Dimm0
Offset 0x04DD - PowerDown Energy Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
UINT8 | PdEnergyCh0Dimm1
Offset 0x04DE - PowerDown Energy Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
UINT8 | PdEnergyCh1Dimm0
Offset 0x04DF - PowerDown Energy Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
UINT8 | PdEnergyCh1Dimm1
Offset 0x04E0 - PowerDown Energy Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
UINT8 | ActEnergyCh0Dimm0
Offset 0x04E1 - Activate Energy Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 | ActEnergyCh0Dimm1
Offset 0x04E2 - Activate Energy Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 | ActEnergyCh1Dimm0
Offset 0x04E3 - Activate Energy Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 | ActEnergyCh1Dimm1
Offset 0x04E4 - Activate Energy Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 | RdEnergyCh0Dimm0
Offset 0x04E5 - Read Energy Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def)
UINT8 | RdEnergyCh0Dimm1
Offset 0x04E6 - Read Energy Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def)
UINT8 | RdEnergyCh1Dimm0
Offset 0x04E7 - Read Energy Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def)
UINT8 | RdEnergyCh1Dimm1
Offset 0x04E8 - Read Energy Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def)
UINT8 | WrEnergyCh0Dimm0
Offset 0x04E9 - Write Energy Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def)
UINT8 | WrEnergyCh0Dimm1
Offset 0x04EA - Write Energy Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def)
UINT8 | WrEnergyCh1Dimm0
Offset 0x04EB - Write Energy Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def)
UINT8 | WrEnergyCh1Dimm1
Offset 0x04EC - Write Energy Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def)
UINT8 | ThrtCkeMinTmr
Offset 0x04ED - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. More...
UINT8 | CkeRankMapping
Offset 0x04EE - Cke Rank Mapping Bits [7:4] - Channel 1, bits [3:0] - Channel 0. More...
UINT8 | RaplPwrFlCh0
Offset 0x04EF - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def)
UINT8 | RaplPwrFlCh1
Offset 0x04F0 - Rapl Power Floor Ch1 Power budget ,range[255;0],(0= 5.3W Def)
UINT8 | EnCmdRate
Offset 0x04F1 - Command Rate Support CMD Rate and Limit Support Option. More...
UINT8 | Refresh2X
Offset 0x04F2 - REFRESH_2X_MODE 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only.
UINT8 | EpgEnable
Offset 0x04F3 - Energy Performance Gain Enable/disable(default) Energy Performance Gain. More...
UINT8 | RhSolution
Offset 0x04F4 - Row Hammer Solution Type of method used to prevent Row Hammer. More...
UINT8 | UserThresholdEnable
Offset 0x04F5 - User Manual Threshold Disabled: Predefined threshold will be used. More...
UINT8 | UserBudgetEnable
Offset 0x04F6 - User Manual Budget Disabled: Configuration of memories will defined the Budget value. More...
UINT8 | TsodTcritMax
Offset 0x04F7 - TcritMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. More...
UINT8 | TsodEventMode
Offset 0x04F8 - Event mode Disable:Comparator mode. More...
UINT8 | TsodEventPolarity
Offset 0x04F9 - EVENT polarity Disable:Active LOW. More...
UINT8 | TsodCriticalEventOnly
Offset 0x04FA - Critical event only Disable:Trips on alarm or critical. More...
UINT8 | TsodEventOutputControl
Offset 0x04FB - Event output control Disable:Event output disable. More...
UINT8 | TsodAlarmwindowLockBit
Offset 0x04FC - Alarm window lock bit Disable:Alarm trips are not locked and can be changed. More...
UINT8 | TsodCriticaltripLockBit
Offset 0x04FD - Critical trip lock bit Disable:Critical trip is not locked and can be changed. More...
UINT8 | TsodShutdownMode
Offset 0x04FE - Shutdown mode Disable:Temperature sensor enable. More...
UINT8 | TsodThigMax
Offset 0x04FF - ThighMax Thigh = ThighMax (Default is 93)
UINT8 | TsodManualEnable
Offset 0x0500 - User Manual Thig and Tcrit Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate. More...
UINT8 | ForceOltmOrRefresh2x
Offset 0x0501 - Force OLTM or 2X Refresh when needed Disabled(Default): = Force OLTM. More...
UINT8 | PwdwnIdleCounter
Offset 0x0502 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. More...
UINT8 | CmdRanksTerminated
Offset 0x0503 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. More...
UINT8 | GdxcEnable
Offset 0x0504 - GDXC MOT enable GDXC MOT enable. More...
UINT8 | PcdSerialDebugLevel
Offset 0x0505 - PcdSerialDebugLevel Serial Debug Message Level. More...
UINT8 | FivrFaults
Offset 0x0506 - Fivr Faults Fivr Faults; 0: Disabled; 1: Enabled. More...
UINT8 | FivrEfficiency
Offset 0x0507 - Fivr Efficiency Fivr Efficiency Management; 0: Disabled; 1: Enabled. More...
UINT8 | SafeMode
Offset 0x0508 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative. More...
UINT8 | CleanMemory
Offset 0x0509 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. More...
UINT8 | LpDdrDqDqsReTraining
Offset 0x050A - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining $EN_DIS.
UINT16 | PostCodeOutputPort
Offset 0x050B - Post Code Output Port This option configures Post Code Output Port.
UINT8 | RMTLoopCount
Offset 0x050D - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. More...
UINT8 | EnBER
Offset 0x050E - BER Support Enable/Disable the Rank Margin Tool interpolation/extrapolation. More...
UINT8 | DualDimmPerChannelBoardType
Offset 0x050F - Dual Dimm Per-Channel Board Type Option to indicate if Board Layout includes One/Two DIMMs per channel. More...
UINT8 | Ddr4MixedUDimm2DpcLimit
Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. More...
UINT8 | ReservedFspmUpdCfl [2]
Offset 0x0511 - CFL Reserved Reserved FspmConfig CFL $EN_DIS.
UINT8 | MemTestOnWarmBoot
Offset 0x0513 - Memory Test on Warm Boot Run Base Memory Test on Warm Boot 0:Disable, 1:Enable.
UINT8 | ThrtCkeMinTmrLpddr
Offset 0x0514 - Throttler CKEMin Timer - LPDDR Timer value for CKEMin (For LPDDR Only), range[255;0]. More...
UINT8 | ReservedFspmUpd [10]
Offset 0x0515.

Detailed Description

Fsp M Configuration.

Definition at line 56 of file FspmUpd.h.

Member Data Documentation

UINT8 FSP_M_CONFIG::ActiveCoreCount

Offset 0x020C - Number of active cores Number of active cores(Depends on Number of cores).

0: All;1: 1 ;2: 2 ;3: 3 0:All, 1:1, 2:2, 3:3

Definition at line 1007 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ApertureSize

Offset 0x00BA - Aperture Size Select the Aperture Size.

0:128 MB, 1:256 MB, 2:512 MB

Definition at line 267 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::ApStartupBase

Offset 0x0248 - ApStartupBase Enable/Disable.

0: Disable, define default value of BiosAcmBase , 1: enable

Definition at line 1170 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Avx2RatioOffset

Offset 0x0210 - AVX2 Ratio Offset 0(Default)= No Offset.

Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.

Definition at line 1033 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Avx3RatioOffset

Offset 0x0211 - AVX3 Ratio Offset 0(Default)= No Offset.

Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.

Definition at line 1039 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BclkAdaptiveVoltage

Offset 0x0212 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.

0: Disable; 1: Enable $EN_DIS

Definition at line 1046 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::BiosAcmBase

Offset 0x0240 - BiosAcmBase Enable/Disable.

0: Disable, define default value of BiosAcmBase , 1: enable

Definition at line 1160 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::BiosAcmSize

Offset 0x0244 - BiosAcmSize Enable/Disable.

0: Disable, define default value of BiosAcmSize , 1: enable

Definition at line 1165 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BiosGuard

Offset 0x0223 - BiosGuard Enable/Disable.

0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS

Definition at line 1110 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BistOnReset

Offset 0x0200 - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 931 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::BootFrequency

Offset 0x020B - Boot frequency Sets the boot frequency starting from reset vector.

  • 0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance.
    Note
    If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode. 0:0, 1:1, 2:2

Definition at line 1000 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ChHashEnable

Offset 0x049E - Ch Hash Support Enable/Disable Channel Hash Support.

NOTE: ONLY if Memory interleaved Mode $EN_DIS

Definition at line 1704 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ChHashInterleaveBit

Offset 0x04B6 - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode.

NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13

Definition at line 1826 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::ChHashMask

Offset 0x04B0 - Ch Hash Mask Set the BIT(s) to be included in the XOR function.

NOTE BIT mask corresponds to BITS [19:6

Definition at line 1813 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CkeRankMapping

Offset 0x04EE - Cke Rank Mapping Bits [7:4] - Channel 1, bits [3:0] - Channel 0.

0xAA=Default Bit [i] specifies which rank CKE[i] goes to.

Definition at line 2094 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CleanMemory

Offset 0x0509 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory.

$EN_DIS

Definition at line 2269 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CmdRanksTerminated

Offset 0x0503 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated.

0x01=Default, Rank0 is terminating and Rank1 is non-terminating

Definition at line 2230 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CoreMaxOcRatio

Offset 0x0205 - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit.

0: Hardware defaults. Range: 0-255

Definition at line 963 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CorePllVoltageOffset

Offset 0x0213 - Core PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63

Definition at line 1051 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::CoreVoltageAdaptive

Offset 0x0216 - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.

Valid Range 0 to 2000

Definition at line 1063 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CoreVoltageMode

Offset 0x0206 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override.

$EN_DIS

Definition at line 969 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::CoreVoltageOverride

Offset 0x0214 - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies.

Valid Range 0 to 2000

Definition at line 1057 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CpuRatio

Offset 0x020A - CPU ratio value CPU ratio value.

Valid Range 0 to 63. CPU Ratio is 0 when disabled.

Definition at line 992 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CpuTraceHubMemReg0Size

Offset 0x00F4 - CPU Trace Hub Memory Region 0 CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB.

Note : Limitation of total buffer size (CPU + PCH) is 512MB. 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB

Definition at line 479 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CpuTraceHubMemReg1Size

Offset 0x00F5 - CPU Trace Hub Memory Region 1 CPU Trace Hub Memory Region 1.

The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB

Definition at line 486 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::CpuTraceHubMode

Offset 0x00F3 - CPU Trace Hub Mode Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.

0: Disable, 1:Target Debugger Mode

Definition at line 472 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DciUsb3TypecUfpDbg

Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.

0:Disabled, 1:Enabled, 2:No Change

Definition at line 222 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Ddr4MixedUDimm2DpcLimit

Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population.

Disable(Default)=0, Enable=1 $EN_DIS

Definition at line 2305 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::DdrFreqLimit

Offset 0x00BE - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz.

Valid values should match the refclk, i.e. divide by 133 or 100 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto

Definition at line 294 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DisableDimmChannel0

Offset 0x00C5 - Channel A DIMM Control Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.

0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs

Definition at line 320 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DisableDimmChannel1

Offset 0x00C6 - Channel B DIMM Control Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.

0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs

Definition at line 326 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DisableMtrrProgram

Offset 0x0207 - Program Cache Attributes Program Cache Attributes; 0: Program; 1: Disable Program.

$EN_DIS

Definition at line 975 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiDeEmphasis

Offset 0x0176 - DeEmphasis control for DMI DeEmphasis control for DMI.

0=-6dB, 1(Default)=-3.5 dB 0: -6dB, 1: -3.5dB

Definition at line 765 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3EndPointHint[8]

Offset 0x0138 - DMI Gen3 End port Hint values per lane Used for programming DMI Gen3 Hint values per lane.

Range: 0-6, 2 is default for each lane

Definition at line 712 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3EndPointPreset[8]

Offset 0x0130 - DMI Gen3 End port preset values per lane Used for programming DMI Gen3 preset values per lane.

Range: 0-9, 7 is default for each lane

Definition at line 707 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3ProgramStaticEq

Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Static Presets.

Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS

Definition at line 566 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DmiGen3RootPortPreset[8]

Offset 0x0128 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane.

Range: 0-9, 8 is default for each lane

Definition at line 702 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::DualDimmPerChannelBoardType

Offset 0x050F - Dual Dimm Per-Channel Board Type Option to indicate if Board Layout includes One/Two DIMMs per channel.

This is used to limit maximum frequency for some SKUs. 0:1DPC, 1:2DPC

Definition at line 2298 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EnableC6Dram

Offset 0x0202 - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.

  • 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. $EN_DIS

Definition at line 945 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EnableSgx

Offset 0x0225 - EnableSgx Enable/Disable.

0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control 0: Disable, 1: Enable, 2: Software Control

Definition at line 1120 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EnBER

Offset 0x050E - BER Support Enable/Disable the Rank Margin Tool interpolation/extrapolation.

0:Disable, 1:Enable

Definition at line 2291 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EnCmdRate

Offset 0x04F1 - Command Rate Support CMD Rate and Limit Support Option.

NOTE: ONLY supported in 1N Mode, Default is 3 CMDs 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS

Definition at line 2110 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::EpgEnable

Offset 0x04F3 - Energy Performance Gain Enable/disable(default) Energy Performance Gain.

$EN_DIS

Definition at line 2122 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::FClkFrequency

Offset 0x020D - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX).

1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved

Definition at line 1014 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::FivrEfficiency

Offset 0x0507 - Fivr Efficiency Fivr Efficiency Management; 0: Disabled; 1: Enabled.

$EN_DIS

Definition at line 2257 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::FivrFaults

Offset 0x0506 - Fivr Faults Fivr Faults; 0: Disabled; 1: Enabled.

$EN_DIS

Definition at line 2251 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ForceOltmOrRefresh2x

Offset 0x0501 - Force OLTM or 2X Refresh when needed Disabled(Default): = Force OLTM.

Enabled: = Force 2x Refresh. $EN_DIS

Definition at line 2218 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::FreqSaGvLow

Offset 0x00C0 - Low Frequency SAGV Low Frequency Selections in Mhz.

Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto. 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto

Definition at line 301 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::FreqSaGvMid

Offset 0x00C2 - Mid Frequency SAGV Mid Frequency Selections in Mhz.

Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto. 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto

Definition at line 308 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::GdxcEnable

Offset 0x0504 - GDXC MOT enable GDXC MOT enable.

$EN_DIS

Definition at line 2236 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::GmAdr

Offset 0x017A - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr + ApertureSize).

Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress

  • 0x1) (Where ApertureSize = 256MB)

Definition at line 785 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::GtPllVoltageOffset

Offset 0x0473 - GT PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63

Definition at line 1446 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::GtPsmiSupport

Offset 0x01F3 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE.

When TRUE, it will allow the PSMI Support $EN_DIS

Definition at line 893 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::GttMmAdr

Offset 0x017E - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize).

Default is (GmAdr - (2MB MMIO

  • 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)

Definition at line 793 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::HobBufferSize

Offset 0x0479 - HobBufferSize Size to set HOB Buffer.

0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size). 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value

Definition at line 1480 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::HotThresholdCh0Dimm0

Offset 0x04CD - Hot Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1927 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::HotThresholdCh0Dimm1

Offset 0x04CE - Hot Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1932 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::HotThresholdCh1Dimm0

Offset 0x04CF - Hot Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1937 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::HotThresholdCh1Dimm1

Offset 0x04D0 - Hot Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1942 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::Idd3n

Offset 0x04B8 - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet.

Must be calculated on a per DIMM basis. Default is 26

Definition at line 1837 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::Idd3p

Offset 0x04BA - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet.

Must be calculated on a per DIMM basis. Default is 11

Definition at line 1843 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::IgdDvmt50PreAlloc

Offset 0x00B8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics.

0x00:0 MB, 0x01:32 MB, 0x02:64 MB

Definition at line 255 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ImrRpSelection

Offset 0x0461 - Root port number for IMR.

Root port number for IMR.

Definition at line 1411 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::InitPcieAspmAfterOprom

Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM programming will happen in relation to the Oprom.

Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume 0:Before, 1:After

Definition at line 686 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::InternalGfx

Offset 0x00B9 - Internal Graphics Enable/disable internal graphics.

$EN_DIS

Definition at line 261 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::IsvtIoPort

Offset 0x00F2 - ISVT IO Port Address ISVT IO Port Address.

0=Minimal, 0xFF=Maximum, 0x99=Default

Definition at line 465 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::JtagC10PowerGateDisable

Offset 0x020E - Set JTAG power in C10 and deeper power states False: JTAG is power gated in C10 state.

True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False; 1: True. 0: False, 1: True

Definition at line 1021 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::McPllVoltageOffset

Offset 0x0476 - Memory Controller PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63

Definition at line 1461 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::MemoryTrace

Offset 0x049D - Memory Trace Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode.

Both channels must be of equal size. This option may change TOLUD and REMAP values as needed. $EN_DIS

Definition at line 1698 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::MmioSize

Offset 0x00A0 - MMIO Size Size of MMIO space reserved for devices.

0(Default)=Auto, non-Zero=size in MB

Definition at line 176 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::OcLock

Offset 0x0204 - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 957 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdDebugInterfaceFlags

Offset 0x0470 - Debug Interfaces Debug Interfaces.

BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used.

Definition at line 1429 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdIsaSerialUartBase

Offset 0x0472 - ISA Serial Base selection Select ISA Serial Base address.

Default is 0x3F8. 0:0x3F8, 1:0x2F8

Definition at line 1441 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdSerialDebugBaudRate

Offset 0x0478 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages.

3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200

Definition at line 1473 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdSerialDebugLevel

Offset 0x0505 - PcdSerialDebugLevel Serial Debug Message Level.

0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info and Verbose

Definition at line 2245 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PcdSerialIoUartNumber

Offset 0x0471 - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug.

0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2

Definition at line 1435 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchLpcEnhancePort8xhDecoding

Offset 0x0450 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h.

$EN_DIS

Definition at line 1362 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchNumRsvdSmbusAddresses

Offset 0x0453 - Number of RsvdSmbusAddressTable.

The number of elements in the RsvdSmbusAddressTable.

Definition at line 1379 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchPort80Route

Offset 0x0451 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.

$EN_DIS

Definition at line 1368 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchSmbAlertEnable

Offset 0x0462 - Enable SMBus Alert Pin Enable SMBus Alert Pin.

$EN_DIS

Definition at line 1417 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchTraceHubMemReg0Size

Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB.

Note : Limitation of total buffer size (PCH + CPU) is 512MB. 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB

Definition at line 236 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchTraceHubMemReg1Size

Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB.

Note : Limitation of total buffer size (PCH + CPU) is 512MB. 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB

Definition at line 243 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PchTraceHubMode

Offset 0x00AC - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.

0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode

Definition at line 229 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::PcieImrSize

Offset 0x0456 - Size of PCIe IMR.

Size of PCIe IMR in megabytes

Definition at line 1389 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::PcieRpEnableMask

Offset 0x045C - Enable PCIE RP Mask Enable/disable PCIE Root Ports.

0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.

Definition at line 1400 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PeciC10Reset

Offset 0x00F6 - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command.

If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value is 0: Disable for CNL, and 1: Enable for all other CPU's $EN_DIS

Definition at line 494 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PeciSxReset

Offset 0x00F7 - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 500 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::PegDataPtr

Offset 0x0152 - Memory data pointer for saved preset search results The reference code will store the Gen3 Preset Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data to skip preset search in the following boots.

Range: 0-0xFFFFFFFF, default is 0

Definition at line 748 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PegDisableSpreadSpectrumClocking

Offset 0x0124 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking.

Normal Operation(0x0)(Default) - SSC enabled, Disable SSC(0X1) - Disable SSC per platform design or for compliance testing 0:Normal Operation, 1:Disable SSC

Definition at line 693 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PlatformDebugConsent

Offset 0x00AA - Platform Debug Consent To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.

Enabling this BIOS option may alter the default value of other debug-related BIOS options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] have the same setting 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)

Definition at line 215 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ProbelessTrace

Offset 0x00A2 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable.

Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. $EN_DIS

Definition at line 183 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::PwdwnIdleCounter

Offset 0x0502 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length.

0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo

Definition at line 2224 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RankInterleave

Offset 0x049B - Rank Interleave support Enables/Disable Rank Interleave support.

NOTE: RI and HORI can not be enabled at the same time. $EN_DIS

Definition at line 1685 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Ratio

Offset 0x00DC - Memory Ratio Automatic or the frequency will equal ratio times reference clock.

Set to Auto to recalculate memory timings listed below. 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15

Definition at line 370 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::RcompResistor[3]

Offset 0x0082 - RcompResister settings Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment.

CFL will need to provide the appropriate values.

Definition at line 114 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::RcompTarget[5]

Offset 0x0088 - RcompTarget settings RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines, otherwise input an Ohmic value per segment.

CFL will need to provide the appropriate values.

Definition at line 120 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RealtimeMemoryTiming

Offset 0x01F0 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled.

When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE. 0: Disabled, 1: Enabled

Definition at line 875 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RefClk

Offset 0x00D9 - Memory Reference Clock 100MHz, 133MHz.

0:133MHz, 1:100MHz

Definition at line 356 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RhSolution

Offset 0x04F4 - Row Hammer Solution Type of method used to prevent Row Hammer.

Default is Hardware RHP 0:Hardware RHP, 1:2x Refresh

Definition at line 2128 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingDownBin

Offset 0x021A - Ring Downbin Ring Downbin enable/disable.

When enabled, CPU will ensure the ring ratio is always lower than the core ratio.0: Disable; 1: Enable. $EN_DIS

Definition at line 1075 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingMaxOcRatio

Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit.

0: Hardware defaults. Range: 0-255

Definition at line 981 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingPllVoltageOffset

Offset 0x0474 - Ring PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63

Definition at line 1451 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::RingVoltageAdaptive

Offset 0x021E - Ring Turbo voltage Adaptive Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.

Valid Range 0 to 2000

Definition at line 1093 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RingVoltageMode

Offset 0x021B - Ring voltage mode Ring voltage mode; 0: Adaptive; 1: Override.

$EN_DIS

Definition at line 1081 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::RingVoltageOffset

Offset 0x0220 - Ring Turbo voltage Offset The voltage offset applied to the ring while operating in turbo mode.

Valid Range 0 to 1000

Definition at line 1098 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::RingVoltageOverride

Offset 0x021C - Ring voltage override The ring voltage override which is applied to the entire range of cpu ring frequencies.

Valid Range 0 to 2000

Definition at line 1087 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RMT

Offset 0x00C4 - Rank Margin Tool Enable/disable Rank Margin Tool.

$EN_DIS

Definition at line 314 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RMTLoopCount

Offset 0x050D - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing.

0 - AUTO

Definition at line 2285 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::RmtPerTask

Offset 0x0096 - Rank Margin Tool per Task This option enables the user to execute Rank Margin Tool per major training step in the MRC.

$EN_DIS

Definition at line 152 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SafeMode

Offset 0x0508 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.

(def=Disable) $EN_DIS

Definition at line 2263 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SaGv

Offset 0x00BC - SA GV System Agent dynamic frequency support and when enabled memory will be training at two different frequencies.

Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled. 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled

Definition at line 282 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SaPllVoltageOffset

Offset 0x0475 - System Agent PLL voltage offset Core PLL voltage offset.

0: No offset. Range 0-63

Definition at line 1456 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ScramblerSupport

Offset 0x00C7 - Scrambler Support This option enables data scrambling in memory.

$EN_DIS

Definition at line 332 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::SinitMemorySize

Offset 0x022C - SinitMemorySize Enable/Disable.

0: Disable, define default value of SinitMemorySize , 1: enable

Definition at line 1140 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SkipMpInit

Offset 0x00C8 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API.

0: Initialize; 1: Skip $EN_DIS

Definition at line 339 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SmbusArpEnable

Offset 0x0452 - Enable SMBus ARP support Enable SMBus ARP support.

$EN_DIS

Definition at line 1374 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SmbusEnable

Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller.

$EN_DIS

Definition at line 199 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SpdAddressTable[4]

Offset 0x00A6 - Spd Address Tabl Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1.

MemorySpdPtr will be used if SPD Address is 00

Definition at line 205 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::SpdProfileSelected

Offset 0x00D8 - SPD Profile Selected Select DIMM timing profile.

Options are 0=Default profile, 1=Custom profile, 2=XMP Profile 1, 3=XMP Profile 2 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2

Definition at line 350 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::TgaSize

Offset 0x024C - TgaSize Enable/Disable.

0: Disable, define default value of TgaSize , 1: enable

Definition at line 1175 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ThrtCkeMinTmr

Offset 0x04ED - Throttler CKEMin Timer Timer value for CKEMin, range[255;0].

Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30

Definition at line 2088 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::ThrtCkeMinTmrLpddr

Offset 0x0514 - Throttler CKEMin Timer - LPDDR Timer value for CKEMin (For LPDDR Only), range[255;0].

Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40

Definition at line 2323 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TjMaxOffset

Offset 0x0222 - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius.

Valid Range 10 - 63

Definition at line 1104 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TrainTrace

Offset 0x0097 - Training Trace This option enables the trained state tracing feature in MRC.

This feature will print out the key training parameters state across major training steps. $EN_DIS

Definition at line 159 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::tRTP

Offset 0x00EA - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15.

DDR4 legal values: 5, 6, 7, 8, 9, 10, 12

Definition at line 422 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::TsegSize

Offset 0x009C - Tseg Size Size of SMRAM memory reserved.

0x400000 for Release build and 0x1000000 for Debug build 0x0400000:4MB, 0x01000000:16MB

Definition at line 171 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodAlarmwindowLockBit

Offset 0x04FC - Alarm window lock bit Disable:Alarm trips are not locked and can be changed.

Enable:Alarm trips are locked and cannot be changed $EN_DIS

Definition at line 2184 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodCriticalEventOnly

Offset 0x04FA - Critical event only Disable:Trips on alarm or critical.

Enable:Trips only if criticaal temperature is reached $EN_DIS

Definition at line 2170 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodCriticaltripLockBit

Offset 0x04FD - Critical trip lock bit Disable:Critical trip is not locked and can be changed.

Enable:Critical trip is locked and cannot be changed $EN_DIS

Definition at line 2191 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodEventMode

Offset 0x04F8 - Event mode Disable:Comparator mode.

Enable:Interrupt mode $EN_DIS

Definition at line 2156 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodEventOutputControl

Offset 0x04FB - Event output control Disable:Event output disable.

Enable:Event output enabled $EN_DIS

Definition at line 2177 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodEventPolarity

Offset 0x04F9 - EVENT polarity Disable:Active LOW.

Enable:Active HIGH $EN_DIS

Definition at line 2163 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodManualEnable

Offset 0x0500 - User Manual Thig and Tcrit Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.

Enabled: User Input will define for Thigh and Tcrit. $EN_DIS

Definition at line 2211 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodShutdownMode

Offset 0x04FE - Shutdown mode Disable:Temperature sensor enable.

Enable:Temperature sensor disable $EN_DIS

Definition at line 2198 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TsodTcritMax

Offset 0x04F7 - TcritMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor.

TCRITMax has to be greater than THIGHMax .
Critical temperature will be TcritMax

Definition at line 2149 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TvbRatioClipping

Offset 0x0144 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled.

This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature 0: Disabled, 1: Enabled

Definition at line 725 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TvbVoltageOptimization

Offset 0x0145 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default).

This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature. 0: Disabled, 1: Enabled

Definition at line 732 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::Txt

Offset 0x0226 - Txt Enable/Disable.

0: Disable, Enable/Disable Txt feature, 1: enable $EN_DIS

Definition at line 1126 of file FspmUpd.h.

UINT64 FSP_M_CONFIG::TxtDprMemoryBase

Offset 0x0238 - TxtDprMemoryBase Enable/Disable.

0: Disable, define default value of TxtDprMemoryBase , 1: enable

Definition at line 1155 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::TxtDprMemorySize

Offset 0x0234 - TxtDprMemorySize Enable/Disable.

0: Disable, define default value of TxtDprMemorySize , 1: enable

Definition at line 1150 of file FspmUpd.h.

UINT32 FSP_M_CONFIG::TxtHeapMemorySize

Offset 0x0230 - TxtHeapMemorySize Enable/Disable.

0: Disable, define default value of TxtHeapMemorySize , 1: enable

Definition at line 1145 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::TxtImplemented

Offset 0x01E3 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first.

Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization $EN_DIS

Definition at line 826 of file FspmUpd.h.

UINT64 FSP_M_CONFIG::TxtLcpPdBase

Offset 0x0250 - TxtLcpPdBase Enable/Disable.

0: Disable, define default value of TxtLcpPdBase , 1: enable

Definition at line 1180 of file FspmUpd.h.

UINT64 FSP_M_CONFIG::TxtLcpPdSize

Offset 0x0258 - TxtLcpPdSize Enable/Disable.

0: Disable, define default value of TxtLcpPdSize , 1: enable

Definition at line 1185 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::UserBudgetEnable

Offset 0x04F6 - User Manual Budget Disabled: Configuration of memories will defined the Budget value.

Enabled: User Input will be used. $EN_DIS

Definition at line 2142 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::UserThresholdEnable

Offset 0x04F5 - User Manual Threshold Disabled: Predefined threshold will be used.

Enabled: User Input will be used. $EN_DIS

Definition at line 2135 of file FspmUpd.h.

UINT16 FSP_M_CONFIG::VddVoltage

Offset 0x00DA - Memory Voltage Memory Voltage Override (Vddq).

Default = no override 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts

Definition at line 363 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::VmxEnable

Offset 0x020F - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1027 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::WarmThresholdCh0Dimm0

Offset 0x04C9 - Warm Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1907 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::WarmThresholdCh0Dimm1

Offset 0x04CA - Warm Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1912 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::WarmThresholdCh1Dimm0

Offset 0x04CB - Warm Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1917 of file FspmUpd.h.

UINT8 FSP_M_CONFIG::WarmThresholdCh1Dimm1

Offset 0x04CC - Warm Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.

Default is 255

Definition at line 1922 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_M_TEST_CONFIG Struct Reference

Public Attributes | List of all members
FSP_M_TEST_CONFIG Struct Reference

Fsp M Test Configuration. More...

#include <FspmUpd.h>

Public Attributes

UINT32 | Signature
Offset 0x0520.
UINT8 | SkipExtGfxScan
Offset 0x0524 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS.
UINT8 | BdatEnable
Offset 0x0525 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. More...
UINT8 | ScanExtGfxForLegacyOpRom
Offset 0x0526 - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). More...
UINT8 | LockPTMregs
Offset 0x0527 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. More...
UINT8 | DmiMaxLinkSpeed
Offset 0x0528 - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
UINT8 | DmiGen3EqPh2Enable
Offset 0x0529 - DMI Equalization Phase 2 DMI Equalization Phase 2. More...
UINT8 | DmiGen3EqPh3Method
Offset 0x052A - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3. More...
UINT8 | Peg0Gen3EqPh2Enable
Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0. More...
UINT8 | Peg1Gen3EqPh2Enable
Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1. More...
UINT8 | Peg2Gen3EqPh2Enable
Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2. More...
UINT8 | Peg3Gen3EqPh2Enable
Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3. More...
UINT8 | Peg0Gen3EqPh3Method
Offset 0x052F - Phase3 EQ method on the PEG 0:1:0. More...
UINT8 | Peg1Gen3EqPh3Method
Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1. More...
UINT8 | Peg2Gen3EqPh3Method
Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2. More...
UINT8 | Peg3Gen3EqPh3Method
Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3. More...
UINT8 | PegGen3ProgramStaticEq
Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets. More...
UINT8 | Gen3SwEqAlwaysAttempt
Offset 0x0534 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot. More...
UINT8 | Gen3SwEqNumberOfPresets
Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq. More...
UINT8 | Gen3SwEqEnableVocTest
Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. More...
UINT8 | PegRxCemTestingMode
Offset 0x0537 - PCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing $EN_DIS.
UINT8 | PegRxCemLoopbackLane
Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback. More...
UINT8 | PegGenerateBdatMarginTable
Offset 0x0539 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. More...
UINT8 | PegRxCemNonProtocolAwareness
Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. More...
UINT8 | PegGen3RxCtleOverride
Offset 0x053B - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified $EN_DIS.
UINT8 | PegGen3Rsvd
Offset 0x053C - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified $EN_DIS.
UINT8 | PegGen3RootPortPreset [20]
Offset 0x053D - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane. More...
UINT8 | PegGen3EndPointPreset [20]
Offset 0x0551 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane. More...
UINT8 | PegGen3EndPointHint [20]
Offset 0x0565 - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane. More...
UINT8 | UnusedUpdSpace8
Offset 0x0579.
UINT16 | Gen3SwEqJitterDwellTime
Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. More...
UINT16 | Gen3SwEqJitterErrorTarget
Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1. More...
UINT16 | Gen3SwEqVocDwellTime
Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000. More...
UINT16 | Gen3SwEqVocErrorTarget
Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2. More...
UINT8 | PanelPowerEnable
Offset 0x0582 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). More...
UINT8 | BdatTestType
Offset 0x0583 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. More...
UINT8 | SaPreMemTestRsvd [12]
Offset 0x0584 - SaPreMemTestRsvd Reserved for SA Pre-Mem Test $EN_DIS.
UINT16 | TotalFlashSize
Offset 0x0590 - TotalFlashSize Enable/Disable. More...
UINT16 | BiosSize
Offset 0x0592 - BiosSize Enable/Disable. More...
UINT8 | TxtAcheckRequest
Offset 0x0594 - TxtAcheckRequest Enable/Disable. More...
UINT8 | SecurityTestRsvd [3]
Offset 0x0595 - SecurityTestRsvd Reserved for SA Pre-Mem Test $EN_DIS.
UINT8 | SmbusDynamicPowerGating
Offset 0x0598 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. More...
UINT8 | WdtDisableAndLock
Offset 0x0599 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. More...
UINT8 | SmbusSpdWriteDisable
Offset 0x059A - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. More...
UINT8 | ChipsetInitMessage
Offset 0x059B - ChipsetInit HECI message DEPRECATED $EN_DIS.
UINT8 | BypassPhySyncReset
Offset 0x059C - Bypass ChipsetInit sync reset. More...
UINT8 | DidInitStat
Offset 0x059D - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS.
UINT8 | DisableCpuReplacedPolling
Offset 0x059E - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS.
UINT8 | SendDidMsg
Offset 0x059F - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent) $EN_DIS.
UINT8 | DisableHeciRetry
Offset 0x05A0 - Retry mechanism for HECI APIs Test, 0: disable, 1: enable, Enable/Disable HECI retry. More...
UINT8 | DisableMessageCheck
Offset 0x05A1 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. More...
UINT8 | SkipMbpHob
Offset 0x05A2 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. More...
UINT8 | HeciCommunication2
Offset 0x05A3 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. More...
UINT8 | KtDeviceEnable
Offset 0x05A4 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device. More...
UINT8 | tRd2RdSG
Offset 0x05A5 - tRd2RdSG Delay between Read-to-Read commands in the same Bank Group. More...
UINT8 | tRd2RdDG
Offset 0x05A6 - tRd2RdDG Delay between Read-to-Read commands in different Bank Group for DDR4. More...
UINT8 | tRd2RdDR
Offset 0x05A7 - tRd2RdDR Delay between Read-to-Read commands in different Ranks. More...
UINT8 | tRd2RdDD
Offset 0x05A8 - tRd2RdDD Delay between Read-to-Read commands in different DIMMs. More...
UINT8 | tWr2RdSG
Offset 0x05A9 - tWr2RdSG Delay between Write-to-Read commands in the same Bank Group. More...
UINT8 | tWr2RdDG
Offset 0x05AA - tWr2RdDG Delay between Write-to-Read commands in different Bank Group for DDR4. More...
UINT8 | tWr2RdDR
Offset 0x05AB - tWr2RdDR Delay between Write-to-Read commands in different Ranks. More...
UINT8 | tWr2RdDD
Offset 0x05AC - tWr2RdDD Delay between Write-to-Read commands in different DIMMs. More...
UINT8 | tWr2WrSG
Offset 0x05AD - tWr2WrSG Delay between Write-to-Write commands in the same Bank Group. More...
UINT8 | tWr2WrDG
Offset 0x05AE - tWr2WrDG Delay between Write-to-Write commands in different Bank Group for DDR4. More...
UINT8 | tWr2WrDR
Offset 0x05AF - tWr2WrDR Delay between Write-to-Write commands in different Ranks. More...
UINT8 | tWr2WrDD
Offset 0x05B0 - tWr2WrDD Delay between Write-to-Write commands in different DIMMs. More...
UINT8 | tRd2WrSG
Offset 0x05B1 - tRd2WrSG Delay between Read-to-Write commands in the same Bank Group. More...
UINT8 | tRd2WrDG
Offset 0x05B2 - tRd2WrDG Delay between Read-to-Write commands in different Bank Group for DDR4. More...
UINT8 | tRd2WrDR
Offset 0x05B3 - tRd2WrDR Delay between Read-to-Write commands in different Ranks. More...
UINT8 | tRd2WrDD
Offset 0x05B4 - tRd2WrDD Delay between Read-to-Write commands in different DIMMs. More...
UINT8 | tRRD_L
Offset 0x05B5 - tRRD_L Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. More...
UINT8 | tRRD_S
Offset 0x05B6 - tRRD_S Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. More...
UINT8 | tWTR_L
Offset 0x05B7 - tWTR_L Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. More...
UINT8 | tWTR_S
Offset 0x05B8 - tWTR_S Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. More...
UINT8 | ReservedFspmTestUpd [3]
Offset 0x05B9.

Detailed Description

Fsp M Test Configuration.

Definition at line 2332 of file FspmUpd.h.

Member Data Documentation

UINT8 FSP_M_TEST_CONFIG::BdatEnable

Offset 0x0525 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data.

Disable (Default): Do not generate it $EN_DIS

Definition at line 2349 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::BdatTestType

Offset 0x0583 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table.

0:Rank Margin Tool, 1:Margin2D

Definition at line 2585 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::BiosSize

Offset 0x0592 - BiosSize Enable/Disable.

0: Disable, define default value of BiosSize , 1: enable

Definition at line 2601 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::BypassPhySyncReset

Offset 0x059C - Bypass ChipsetInit sync reset.

DEPRECATED $EN_DIS

Definition at line 2644 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DisableHeciRetry

Offset 0x05A0 - Retry mechanism for HECI APIs Test, 0: disable, 1: enable, Enable/Disable HECI retry.

$EN_DIS

Definition at line 2670 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DisableMessageCheck

Offset 0x05A1 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check.

$EN_DIS

Definition at line 2676 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DmiGen3EqPh2Enable

Offset 0x0529 - DMI Equalization Phase 2 DMI Equalization Phase 2.

(0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method 0:Disable phase2, 1:Enable phase2, 2:Auto

Definition at line 2376 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::DmiGen3EqPh3Method

Offset 0x052A - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3.

Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 2386 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Gen3SwEqAlwaysAttempt

Offset 0x0534 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot.

Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended 0:Disable, 1:Enable

Definition at line 2469 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Gen3SwEqEnableVocTest

Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm.

Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default 0:Disable, 1:Enable, 2:Auto

Definition at line 2487 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqJitterDwellTime

Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000.

Warning
Do not change from the default

Definition at line 2557 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqJitterErrorTarget

Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1.

Warning
Do not change from the default

Definition at line 2562 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Gen3SwEqNumberOfPresets

Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq.

P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible for this default to change over time;using Auto will ensure Reference Code always uses the latest default settings 0:P7 P3 P5, 1:P0 to P9, 2:Auto

Definition at line 2479 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqVocDwellTime

Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000.

Warning
Do not change from the default

Definition at line 2567 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::Gen3SwEqVocErrorTarget

Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2.

Warning
Do not change from the default

Definition at line 2572 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::HeciCommunication2

Offset 0x05A3 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.

$EN_DIS

Definition at line 2688 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::KtDeviceEnable

Offset 0x05A4 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device.

$EN_DIS

Definition at line 2694 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::LockPTMregs

Offset 0x0527 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers.

Enable(Default)=1, Disable=0 $EN_DIS

Definition at line 2362 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PanelPowerEnable

Offset 0x0582 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel).

0=Disable, 1(Default)=Enable $EN_DIS

Definition at line 2579 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg0Gen3EqPh2Enable

Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0.

Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto

Definition at line 2393 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg0Gen3EqPh3Method

Offset 0x052F - Phase3 EQ method on the PEG 0:1:0.

PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 2424 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg1Gen3EqPh2Enable

Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1.

Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto

Definition at line 2400 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg1Gen3EqPh3Method

Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1.

PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 2434 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg2Gen3EqPh2Enable

Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2.

Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto

Definition at line 2407 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg2Gen3EqPh3Method

Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2.

PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 2444 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg3Gen3EqPh2Enable

Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3.

Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto

Definition at line 2414 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::Peg3Gen3EqPh3Method

Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3.

PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1), Disabled(0x4): Bypass Equalization Phase 3 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3

Definition at line 2454 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3EndPointHint[20]

Offset 0x0565 - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane.

Range: 0-6, 2 is default for each lane

Definition at line 2548 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3EndPointPreset[20]

Offset 0x0551 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane.

Range: 0-9, 7 is default for each lane

Definition at line 2543 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3ProgramStaticEq

Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets.

Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS

Definition at line 2461 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGen3RootPortPreset[20]

Offset 0x053D - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane.

Range: 0-9, 8 is default for each lane

Definition at line 2538 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegGenerateBdatMarginTable

Offset 0x0539 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table.

Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data $EN_DIS

Definition at line 2508 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegRxCemLoopbackLane

Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback.

Default is Lane 0

Definition at line 2500 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::PegRxCemNonProtocolAwareness

Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table.

Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing $EN_DIS

Definition at line 2517 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::ScanExtGfxForLegacyOpRom

Offset 0x0526 - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable).

Enable(Default)=1, Disable=0 $EN_DIS

Definition at line 2356 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::SkipMbpHob

Offset 0x05A2 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB.

$EN_DIS

Definition at line 2682 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::SmbusDynamicPowerGating

Offset 0x0598 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating.

$EN_DIS

Definition at line 2619 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::SmbusSpdWriteDisable

Offset 0x059A - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable.

0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS

Definition at line 2632 of file FspmUpd.h.

UINT16 FSP_M_TEST_CONFIG::TotalFlashSize

Offset 0x0590 - TotalFlashSize Enable/Disable.

0: Disable, define default value of TotalFlashSize , 1: enable

Definition at line 2596 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2RdDD

Offset 0x05A8 - tRd2RdDD Delay between Read-to-Read commands in different DIMMs.

0-Auto, Range 4-54.

Definition at line 2715 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2RdDG

Offset 0x05A6 - tRd2RdDG Delay between Read-to-Read commands in different Bank Group for DDR4.

All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54.

Definition at line 2705 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2RdDR

Offset 0x05A7 - tRd2RdDR Delay between Read-to-Read commands in different Ranks.

0-Auto, Range 4-54.

Definition at line 2710 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2RdSG

Offset 0x05A5 - tRd2RdSG Delay between Read-to-Read commands in the same Bank Group.

0-Auto, Range 4-54.

Definition at line 2699 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2WrDD

Offset 0x05B4 - tRd2WrDD Delay between Read-to-Write commands in different DIMMs.

0-Auto, Range 4-54.

Definition at line 2778 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2WrDG

Offset 0x05B2 - tRd2WrDG Delay between Read-to-Write commands in different Bank Group for DDR4.

All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54.

Definition at line 2768 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2WrDR

Offset 0x05B3 - tRd2WrDR Delay between Read-to-Write commands in different Ranks.

0-Auto, Range 4-54.

Definition at line 2773 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRd2WrSG

Offset 0x05B1 - tRd2WrSG Delay between Read-to-Write commands in the same Bank Group.

0-Auto, Range 4-54.

Definition at line 2762 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRRD_L

Offset 0x05B5 - tRRD_L Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only.

0: AUTO, max: 31

Definition at line 2783 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tRRD_S

Offset 0x05B6 - tRRD_S Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only.

0: AUTO, max: 31

Definition at line 2789 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2RdDD

Offset 0x05AC - tWr2RdDD Delay between Write-to-Read commands in different DIMMs.

0-Auto, Range 4-54.

Definition at line 2736 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2RdDG

Offset 0x05AA - tWr2RdDG Delay between Write-to-Read commands in different Bank Group for DDR4.

All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54.

Definition at line 2726 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2RdDR

Offset 0x05AB - tWr2RdDR Delay between Write-to-Read commands in different Ranks.

0-Auto, Range 4-54.

Definition at line 2731 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2RdSG

Offset 0x05A9 - tWr2RdSG Delay between Write-to-Read commands in the same Bank Group.

0-Auto, Range 4-86.

Definition at line 2720 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2WrDD

Offset 0x05B0 - tWr2WrDD Delay between Write-to-Write commands in different DIMMs.

0-Auto, Range 4-54.

Definition at line 2757 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2WrDG

Offset 0x05AE - tWr2WrDG Delay between Write-to-Write commands in different Bank Group for DDR4.

All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54.

Definition at line 2747 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2WrDR

Offset 0x05AF - tWr2WrDR Delay between Write-to-Write commands in different Ranks.

0-Auto, Range 4-54.

Definition at line 2752 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWr2WrSG

Offset 0x05AD - tWr2WrSG Delay between Write-to-Write commands in the same Bank Group.

0-Auto, Range 4-54.

Definition at line 2741 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWTR_L

Offset 0x05B7 - tWTR_L Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only.

0: AUTO, max: 60

Definition at line 2795 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::tWTR_S

Offset 0x05B8 - tWTR_S Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only.

0: AUTO, max: 28

Definition at line 2801 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::TxtAcheckRequest

Offset 0x0594 - TxtAcheckRequest Enable/Disable.

When Enabled, it will forcing calling TXT Acheck once. $EN_DIS

Definition at line 2607 of file FspmUpd.h.

UINT8 FSP_M_TEST_CONFIG::WdtDisableAndLock

Offset 0x0599 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers.

$EN_DIS

Definition at line 2625 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_S_CONFIG Struct Reference

Public Attributes | List of all members
FSP_S_CONFIG Struct Reference

Fsp S Configuration. More...

#include <FspsUpd.h>

Public Attributes

UINT32 | LogoPtr
Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
UINT32 | LogoSize
Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
UINT32 | GraphicsConfigPtr
Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
UINT8 | Device4Enable
Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
UINT8 | PchHdaDspEnable
Offset 0x002D - Enable HD Audio DSP Enable/disable HD Audio DSP feature. More...
UINT8 | UnusedUpdSpace0 [3]
Offset 0x002E.
UINT8 | ScsEmmcEnabled
Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller. More...
UINT8 | ScsEmmcHs400Enabled
Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. More...
UINT8 | ScsSdCardEnabled
Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller. More...
UINT8 | ShowSpiController
Offset 0x0034 - Show SPI controller Enable/disable to show SPI controller. More...
UINT8 | UnusedUpdSpace1 [3]
Offset 0x0035.
UINT32 | MicrocodeRegionBase
Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
UINT32 | MicrocodeRegionSize
Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
UINT8 | TurboMode
Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode. More...
UINT8 | SataSalpSupport
Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. More...
UINT8 | SataPortsEnable [8]
Offset 0x0042 - Enable SATA ports Enable/disable SATA ports. More...
UINT8 | SataPortsDevSlp [8]
Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. More...
UINT8 | PortUsb20Enable [16]
Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports. More...
UINT8 | PortUsb30Enable [10]
Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports. More...
UINT8 | XdciEnable
Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller. More...
UINT8 | UnusedUpdSpace2 [2]
Offset 0x006D.
UINT8 | SerialIoDevMode [12]
Offset 0x006F - Enable SerialIo Device Mode 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device mode respectively. More...
UINT32 | DevIntConfigPtr
Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table. More...
UINT8 | NumOfDevIntConfig
Offset 0x007F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. More...
UINT8 | PxRcConfig [8]
Offset 0x0080 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. More...
UINT8 | GpioIrqRoute
Offset 0x0088 - Select GPIO IRQ Route GPIO IRQ Select. More...
UINT8 | SciIrqSelect
Offset 0x0089 - Select SciIrqSelect SCI IRQ Select. More...
UINT8 | TcoIrqSelect
Offset 0x008A - Select TcoIrqSelect TCO IRQ Select. More...
UINT8 | TcoIrqEnable
Offset 0x008B - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
UINT8 | PchHdaVerbTableEntryNum
Offset 0x008C - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
UINT32 | PchHdaVerbTablePtr
Offset 0x008D - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
UINT8 | PchHdaCodecSxWakeCapability
Offset 0x0091 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx.
UINT8 | SataEnable
Offset 0x0092 - Enable SATA Enable/disable SATA controller. More...
UINT8 | SataMode
Offset 0x0093 - SATA Mode Select SATA controller working mode. More...
UINT8 | Usb2AfePetxiset [16]
Offset 0x0094 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. More...
UINT8 | Usb2AfeTxiset [16]
Offset 0x00A4 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. More...
UINT8 | Usb2AfePredeemp [16]
Offset 0x00B4 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. More...
UINT8 | Usb2AfePehalfbit [16]
Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. More...
UINT8 | Usb3HsioTxDeEmphEnable [10]
Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. More...
UINT8 | Usb3HsioTxDeEmph [10]
Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). More...
UINT8 | Usb3HsioTxDownscaleAmpEnable [10]
Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. More...
UINT8 | Usb3HsioTxDownscaleAmp [10]
Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. More...
UINT8 | PchLanEnable
Offset 0x00FC - Enable LAN Enable/disable LAN controller. More...
UINT8 | PchHdaAudioLinkHda
Offset 0x00FD - Enable HD Audio Link Enable/disable HD Audio Link. More...
UINT8 | PchHdaAudioLinkDmic0
Offset 0x00FE - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link. More...
UINT8 | PchHdaAudioLinkDmic1
Offset 0x00FF - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link. More...
UINT8 | PchHdaAudioLinkSsp0
Offset 0x0100 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link. More...
UINT8 | PchHdaAudioLinkSsp1
Offset 0x0101 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link. More...
UINT8 | PchHdaAudioLinkSsp2
Offset 0x0102 - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link. More...
UINT8 | PchHdaAudioLinkSndw1
Offset 0x0103 - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link. More...
UINT8 | PchHdaAudioLinkSndw2
Offset 0x0104 - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link. More...
UINT8 | PchHdaAudioLinkSndw3
Offset 0x0105 - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link. More...
UINT8 | PchHdaAudioLinkSndw4
Offset 0x0106 - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link. More...
UINT8 | PchHdaSndwBufferRcomp
Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. More...
UINT32 | PcieRpPtmMask
Offset 0x0108 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports. More...
UINT32 | PcieRpDpcMask
Offset 0x010C - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports. More...
UINT32 | PcieRpDpcExtensionsMask
Offset 0x0110 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports. More...
UINT8 | UsbPdoProgramming
Offset 0x0114 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. More...
UINT32 | PmcPowerButtonDebounce
Offset 0x0115 - Power button debounce configuration Debounce time for PWRBTN in microseconds. More...
UINT8 | PchEspiBmeMasterSlaveEnabled
Offset 0x0119 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS.
UINT8 | SataRstLegacyOrom
Offset 0x011A - PCH SATA use RST Legacy OROM Use PCH SATA RST Legacy OROM when CSM is Enabled $EN_DIS.
UINT32 | TraceHubMemBase
Offset 0x011B - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly.
UINT8 | PmcDbgMsgEn
Offset 0x011F - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. More...
UINT32 | ChipsetInitBinPtr
Offset 0x0120 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer.
UINT32 | ChipsetInitBinLen
Offset 0x0124 - Length of ChipsetInit Binary ChipsetInit Binary Length.
UINT8 | PchPostMemRsvd [29]
Offset 0x0128 - PchPostMemRsvd Reserved for PCH Post-Mem $EN_DIS.
UINT8 | ScsUfsEnabled
Offset 0x0145 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller. More...
UINT8 | PchCnviMode
Offset 0x0146 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. More...
UINT8 | SdCardPowerEnableActiveHigh
Offset 0x0147 - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high.
UINT8 | PchUsb2PhySusPgEnable
Offset 0x0148 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS.
UINT8 | PchUsbOverCurrentEnable
Offset 0x0149 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS.
UINT8 | UnusedUpdSpace3
Offset 0x014A.
UINT8 | PchCnviMfUart1Type
Offset 0x014B - CNVi MfUart1 Type This option configures Uart type which connects to MfUart1 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads.
UINT8 | PchEspiLgmrEnable
Offset 0x014C - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS.
UINT8 | Heci3Enabled
Offset 0x014D - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. More...
UINT8 | UnusedUpdSpace4
Offset 0x014E.
UINT8 | PchHotEnable
Offset 0x014F - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. More...
UINT8 | SataLedEnable
Offset 0x0150 - SATA LED SATA LED indicating SATA controller activity. More...
UINT8 | PchPmVrAlert
Offset 0x0151 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit. More...
UINT8 | PchPmSlpS0VmRuntimeControl
Offset 0x0152 - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy. More...
UINT8 | PchPmSlpS0Vm070VSupport
Offset 0x0153 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy. More...
UINT8 | PchPmSlpS0Vm075VSupport
Offset 0x0154 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy. More...
UINT8 | AmtEnabled
Offset 0x0155 - AMT Switch Enable/Disable. More...
UINT8 | WatchDog
Offset 0x0156 - WatchDog Timer Switch Enable/Disable. More...
UINT8 | AsfEnabled
Offset 0x0157 - ASF Switch Enable/Disable. More...
UINT8 | ManageabilityMode
Offset 0x0158 - Manageability Mode set by Mebx Enable/Disable. More...
UINT8 | FwProgress
Offset 0x0159 - PET Progress Enable/Disable. More...
UINT8 | AmtSolEnabled
Offset 0x015A - SOL Switch Enable/Disable. More...
UINT16 | WatchDogTimerOs
Offset 0x015B - OS Timer 16 bits Value, Set OS watchdog timer. More...
UINT16 | WatchDogTimerBios
Offset 0x015D - BIOS Timer 16 bits Value, Set BIOS watchdog timer. More...
UINT8 | RemoteAssistance
Offset 0x015F - Remote Assistance Trigger Availablilty Enable/Disable. More...
UINT8 | AmtKvmEnabled
Offset 0x0160 - KVM Switch Enable/Disable. More...
UINT8 | ForcMebxSyncUp
Offset 0x0161 - MEBX execution Enable/Disable. More...
UINT8 | UnusedUpdSpace5 [1]
Offset 0x0162.
UINT8 | PcieRpSlotImplemented [24]
Offset 0x0163 - PCH PCIe root port connection type 0: built-in device, 1:slot.
UINT8 | PcieClkSrcUsage [16]
Offset 0x017B - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used.
UINT8 | PcieClkSrcClkReq [16]
Offset 0x018B - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc.
UINT8 | PcieRpAcsEnabled [24]
Offset 0x019B - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability.
UINT8 | PcieRpEnableCpm [24]
Offset 0x01B3 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism.
UINT16 | PcieRpDetectTimeoutMs [24]
Offset 0x01CB - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.
UINT8 | PmcModPhySusPgEnable
Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. More...
UINT8 | SlpS0WithGbeSupport
Offset 0x01FC - SlpS0WithGbeSupport Enable/Disable SLP_S0 with GBE Support. More...
UINT8 | UnusedUpdSpace6 [3]
Offset 0x01FD.
UINT8 | CridEnable
Offset 0x0200 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS.
UINT8 | DmiAspm
Offset 0x0201 - DMI ASPM 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 0:Disable, 1:L0s, 2:L1, 3:L0sL1.
UINT8 | PegDeEmphasis [4]
Offset 0x0202 - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB 0:-6dB, 1:-3.5dB.
UINT8 | PegSlotPowerLimitValue [4]
Offset 0x0206 - PCIe Slot Power Limit value per root port Slot power limit value per root port.
UINT8 | PegSlotPowerLimitScale [4]
Offset 0x020A - PCIe Slot Power Limit scale per root port Slot power limit scale per root port 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x.
UINT16 | PegPhysicalSlotNumber [4]
Offset 0x020E - PCIe Physical Slot Number per root port Physical Slot Number per root port.
UINT8 | PavpEnable
Offset 0x0216 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS.
UINT8 | CdClock
Offset 0x0217 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz.
UINT8 | PeiGraphicsPeimInit
Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
UINT8 | UnusedUpdSpace7
Offset 0x0219.
UINT8 | GnaEnable
Offset 0x021A - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | X2ApicOptOut
Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS.
UINT32 | VtdBaseAddress [3]
Offset 0x021C - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine.
UINT8 | DdiPortEdp
Offset 0x0228 - Enable or disable eDP device 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortBHpd
Offset 0x0229 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortCHpd
Offset 0x022A - Enable or disable HPD of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortDHpd
Offset 0x022B - Enable or disable HPD of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortFHpd
Offset 0x022C - Enable or disable HPD of DDI port F 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortBDdc
Offset 0x022D - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortCDdc
Offset 0x022E - Enable or disable DDC of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortDDdc
Offset 0x022F - Enable or disable DDC of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8 | DdiPortFDdc
Offset 0x0230 - Enable or disable DDC of DDI port F 0(Default)=Disable, 1=Enable $EN_DIS.
UINT8 | SkipS3CdClockInit
Offset 0x0231 - Enable/Disable SkipS3CdClockInit Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent $EN_DIS.
UINT16 | DeltaT12PowerCycleDelay
Offset 0x0232 - Delta T12 Power Cycle Delay required in ms Select the value for delay required. More...
UINT32 | BltBufferAddress
Offset 0x0234 - Blt Buffer Address Address of Blt buffer.
UINT32 | BltBufferSize
Offset 0x0238 - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
UINT8 | SaPostMemProductionRsvd [35]
Offset 0x023C - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS.
UINT8 | PcieRootPortGen2PllL1CgDisable [24]
Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge.
UINT8 | AesEnable
Offset 0x0277 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable $EN_DIS.
UINT8 | Psi3Enable [5]
Offset 0x0278 - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. More...
UINT8 | Psi4Enable [5]
Offset 0x027D - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | ImonSlope [5]
Offset 0x0282 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. More...
UINT8 | ImonOffset [5]
Offset 0x0287 - Imon offset correction PCODE MMIO Mailbox: Imon offset correction. More...
UINT8 | VrConfigEnable [5]
Offset 0x028C - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | TdcEnable [5]
Offset 0x0291 - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | TdcTimeWindow [5]
Offset 0x0296 - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window. More...
UINT8 | TdcLock [5]
Offset 0x029B - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes.
UINT8 | PsysSlope
Offset 0x02A0 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. More...
UINT8 | PsysOffset
Offset 0x02A1 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. More...
UINT8 | AcousticNoiseMitigation
Offset 0x02A2 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. More...
UINT8 | FastPkgCRampDisableIa
Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SlowSlewRateForIa
Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SlowSlewRateForGt
Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SlowSlewRateForSa
Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. More...
UINT16 | TdcPowerLimit [5]
Offset 0x02A7 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. More...
UINT16 | AcLoadline [5]
Offset 0x02B1 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. More...
UINT8 | UnusedUpdSpace8 [10]
Offset 0x02BB.
UINT16 | DcLoadline [5]
Offset 0x02C5 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. More...
UINT16 | Psi1Threshold [5]
Offset 0x02CF - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. More...
UINT16 | Psi2Threshold [5]
Offset 0x02D9 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. More...
UINT16 | Psi3Threshold [5]
Offset 0x02E3 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. More...
UINT16 | IccMax [5]
Offset 0x02ED - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. More...
UINT16 | VrVoltageLimit [5]
Offset 0x02F7 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit. More...
UINT8 | FastPkgCRampDisableGt
Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | FastPkgCRampDisableSa
Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SendVrMbxCmd
Offset 0x0303 - Enable VR specific mailbox command VR specific mailbox commands. More...
UINT8 | Reserved2
Offset 0x0304 - Reserved Reserved.
UINT8 | TxtEnable
Offset 0x0305 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. More...
UINT8 | UnusedUpdSpace9 [6]
Offset 0x0306.
UINT8 | SkipMpInit
Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization. More...
UINT8 | McivrRfiFrequencyPrefix
Offset 0x030D - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. More...
UINT8 | McivrRfiFrequencyAdjust
Offset 0x030E - McIVR RFI Frequency Adjustment PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. More...
UINT16 | FivrRfiFrequency
Offset 0x030F - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. More...
UINT8 | McivrSpreadSpectrum
Offset 0x0311 - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. More...
UINT8 | FivrSpreadSpectrum
Offset 0x0312 - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. More...
UINT8 | FastPkgCRampDisableFivr
Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8 | SlowSlewRateForFivr
Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. More...
UINT32 | CpuBistData
Offset 0x0315 - CpuBistData Pointer CPU BIST Data.
UINT8 | IslVrCmd
Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues. More...
UINT16 | ImonSlope1 [5]
Offset 0x031A - Imon slope1 correction PCODE MMIO Mailbox: Imon slope correction. More...
UINT32 | VrPowerDeliveryDesign
Offset 0x0324 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. More...
UINT8 | PreWake
Offset 0x0328 - Pre Wake Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. More...
UINT8 | RampUp
Offset 0x0329 - Ramp Up Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0.
UINT8 | RampDown
Offset 0x032A - Ramp Down Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0.
UINT32 | CpuMpPpi
Offset 0x032B - CpuMpPpi Pointer for CpuMpPpi.
UINT32 | CpuMpHob
Offset 0x032F - CpuMpHob Pointer for CpuMpHob. More...
UINT8 | DebugInterfaceEnable
Offset 0x0333 - Enable or Disable processor debug features Enable or Disable processor debug features; 0: Disable; 1: Enable. More...
UINT8 | ReservedCpuPostMemProduction [18]
Offset 0x0334 - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS.
UINT8 | PchDmiAspm
Offset 0x0346 - Enable DMI ASPM Deprecated. More...
UINT8 | PchPwrOptEnable
Offset 0x0347 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. More...
UINT8 | PchWriteProtectionEnable [5]
Offset 0x0348 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware.
UINT8 | PchReadProtectionEnable [5]
Offset 0x034D - PCH Flash Protection Ranges Read Enble Read is blocked by hardware.
UINT16 | PchProtectedRangeLimit [5]
Offset 0x0352 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison.
UINT16 | PchProtectedRangeBase [5]
Offset 0x035C - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
UINT8 | PchHdaPme
Offset 0x0366 - Enable Pme Enable Azalia wake-on-ring. More...
UINT8 | UnusedUpdSpace10
Offset 0x0367.
UINT8 | PchHdaVcType
Offset 0x0368 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1. More...
UINT8 | PchHdaLinkFrequency
Offset 0x0369 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. More...
UINT8 | PchHdaIDispLinkFrequency
Offset 0x036A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. More...
UINT8 | PchHdaIDispLinkTmode
Offset 0x036B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. More...
UINT8 | PchHdaDspUaaCompliance
Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). More...
UINT8 | PchHdaIDispCodecDisconnect
Offset 0x036D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. More...
UINT8 | PchUsbHsioFilterSel [10]
Offset 0x036E - USB LFPS Filter selection For each byte bits 2:0 are for p, bits 4:6 are for n. More...
UINT8 | UnusedUpdSpace11 [5]
Offset 0x0378.
UINT8 | PchIoApicEntry24_119
Offset 0x037D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. More...
UINT8 | PchIoApicId
Offset 0x037E - PCH Io Apic ID This member determines IOAPIC ID. More...
UINT8 | UnusedUpdSpace12
Offset 0x037F.
UINT8 | PchIshSpiGpioAssign
Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshUart0GpioAssign
Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshUart1GpioAssign
Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshI2c0GpioAssign
Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshI2c1GpioAssign
Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshI2c2GpioAssign
Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp0GpioAssign
Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp1GpioAssign
Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp2GpioAssign
Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp3GpioAssign
Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp4GpioAssign
Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp5GpioAssign
Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp6GpioAssign
Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshGp7GpioAssign
Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8 | PchIshPdtUnlock
Offset 0x038E - PCH ISH PDT Unlock Msg 0: False; 1: True. More...
UINT8 | PchLanLtrEnable
Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. More...
UINT8 | UnusedUpdSpace13 [3]
Offset 0x0390.
UINT8 | PchLockDownBiosLock
Offset 0x0393 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. More...
UINT8 | PchCrid
Offset 0x0394 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. More...
UINT8 | PchLockDownRtcMemoryLock
Offset 0x0395 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. More...
UINT8 | PcieRpHotPlug [24]
Offset 0x0396 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available.
UINT8 | PcieRpPmSci [24]
Offset 0x03AE - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled.
UINT8 | PcieRpExtSync [24]
Offset 0x03C6 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled.
UINT8 | PcieRpTransmitterHalfSwing [24]
Offset 0x03DE - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled.
UINT8 | PcieRpClkReqDetect [24]
Offset 0x03F6 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management.
UINT8 | PcieRpAdvancedErrorReporting [24]
Offset 0x040E - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled.
UINT8 | PcieRpUnsupportedRequestReport [24]
Offset 0x0426 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled.
UINT8 | PcieRpFatalErrorReport [24]
Offset 0x043E - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled.
UINT8 | PcieRpNoFatalErrorReport [24]
Offset 0x0456 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled.
UINT8 | PcieRpCorrectableErrorReport [24]
Offset 0x046E - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled.
UINT8 | PcieRpSystemErrorOnFatalError [24]
Offset 0x0486 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled.
UINT8 | PcieRpSystemErrorOnNonFatalError [24]
Offset 0x049E - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled.
UINT8 | PcieRpSystemErrorOnCorrectableError [24]
Offset 0x04B6 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled.
UINT8 | PcieRpMaxPayload [24]
Offset 0x04CE - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
UINT8 | PchUsbHsioRxTuningParameters [10]
Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset.
UINT8 | PchUsbHsioRxTuningEnable [10]
Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable Mask for enabling tuning of HSIO Rx signals of USB3 ports. More...
UINT8 | UnusedUpdSpace14 [4]
Offset 0x04FA.
UINT8 | PcieRpPcieSpeed [24]
Offset 0x04FE - PCIE RP Pcie Speed Determines each PCIE Port speed capability. More...
UINT8 | PcieRpGen3EqPh3Method [24]
Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). More...
UINT8 | PcieRpPhysicalSlotNumber [24]
Offset 0x052E - PCIE RP Physical Slot Number Indicates the slot number for the root port. More...
UINT8 | PcieRpCompletionTimeout [24]
Offset 0x0546 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). More...
UINT8 | UnusedUpdSpace15 [106]
Offset 0x055E.
UINT8 | PcieRpAspm [24]
Offset 0x05C8 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). More...
UINT8 | PcieRpL1Substates [24]
Offset 0x05E0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). More...
UINT8 | PcieRpLtrEnable [24]
Offset 0x05F8 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism.
UINT8 | PcieRpLtrConfigLock [24]
Offset 0x0610 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable.
UINT8 | PcieEqPh3LaneParamCm [24]
Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. More...
UINT8 | PcieEqPh3LaneParamCp [24]
Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. More...
UINT8 | PcieSwEqCoeffListCm [5]
Offset 0x0658 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. More...
UINT8 | PcieSwEqCoeffListCp [5]
Offset 0x065D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. More...
UINT8 | PcieDisableRootPortClockGating
Offset 0x0662 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. More...
UINT8 | PcieEnablePeerMemoryWrite
Offset 0x0663 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. More...
UINT8 | UnusedUpdSpace16
Offset 0x0664.
UINT8 | PcieComplianceTestMode
Offset 0x0665 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. More...
UINT8 | PcieRpFunctionSwap
Offset 0x0666 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
UINT8 | TetonGlacierSupport
Offset 0x0667 - Teton Glacier Support Enables support for the Teton Glacier card. More...
UINT8 | TetonGlacierCR
Offset 0x0668 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. More...
UINT8 | PchPmPmeB0S5Dis
Offset 0x0669 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. More...
UINT8 | SerialIoSpiCsPolarity [3]
Offset 0x066A - SPI ChipSelect signal polarity Selects SPI ChipSelect signal polarity.
UINT8 | PcieRpImrEnabled
Offset 0x066D - PCIE IMR Enables Isolated Memory Region for PCIe. More...
UINT8 | PcieRpImrSelection
Offset 0x066E - PCIE IMR port number Selects PCIE root port number for IMR feature.
UINT8 | UnusedUpdSpace17
Offset 0x066F.
UINT8 | PchPmWolEnableOverride
Offset 0x0670 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. More...
UINT8 | PchPmPcieWakeFromDeepSx
Offset 0x0671 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. More...
UINT8 | PchPmWoWlanEnable
Offset 0x0672 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
UINT8 | PchPmWoWlanDeepSxEnable
Offset 0x0673 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
UINT8 | PchPmLanWakeFromDeepSx
Offset 0x0674 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. More...
UINT8 | PchPmDeepSxPol
Offset 0x0675 - PCH Pm Deep Sx Pol Deep Sx Policy. More...
UINT8 | PchPmSlpS3MinAssert
Offset 0x0676 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. More...
UINT8 | PchPmSlpS4MinAssert
Offset 0x0677 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. More...
UINT8 | PchPmSlpSusMinAssert
Offset 0x0678 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. More...
UINT8 | PchPmSlpAMinAssert
Offset 0x0679 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. More...
UINT8 | SlpS0Override
Offset 0x067A - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type. More...
UINT8 | SlpS0DisQForDebug
Offset 0x067B - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe type. More...
UINT8 | PchEnableDbcObs
Offset 0x067C - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. More...
UINT8 | UnusedUpdSpace18 [3]
Offset 0x067D.
UINT8 | PchPmLpcClockRun
Offset 0x0680 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
UINT8 | PchPmSlpStrchSusUp
Offset 0x0681 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. More...
UINT8 | PchPmSlpLanLowDc
Offset 0x0682 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. More...
UINT8 | PchPmPwrBtnOverridePeriod
Offset 0x0683 - PCH Pm Pwr Btn Override Period PCH power button override period. More...
UINT8 | PchPmDisableDsxAcPresentPulldown
Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
UINT8 | UnusedUpdSpace19
Offset 0x0685.
UINT8 | PchPmDisableNativePowerButton
Offset 0x0686 - PCH Pm Disable Native Power Button Power button native mode disable. More...
UINT8 | PchPmSlpS0Enable
Offset 0x0687 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. More...
UINT8 | PchPmMeWakeSts
Offset 0x0688 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. More...
UINT8 | PchPmWolOvrWkSts
Offset 0x0689 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. More...
UINT8 | PchPmPwrCycDur
Offset 0x068A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. More...
UINT8 | PchPmPciePllSsc
Offset 0x068B - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. More...
UINT8 | UnusedUpdSpace20
Offset 0x068C.
UINT8 | SataPwrOptEnable
Offset 0x068D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. More...
UINT8 | EsataSpeedLimit
Offset 0x068E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
UINT8 | SataSpeedLimit
Offset 0x068F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
UINT8 | SataPortsHotPlug [8]
Offset 0x0690 - Enable SATA Port HotPlug Enable SATA Port HotPlug.
UINT8 | SataPortsInterlockSw [8]
Offset 0x0698 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw.
UINT8 | SataPortsExternal [8]
Offset 0x06A0 - Enable SATA Port External Enable SATA Port External.
UINT8 | SataPortsSpinUp [8]
Offset 0x06A8 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device.
UINT8 | SataPortsSolidStateDrive [8]
Offset 0x06B0 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD.
UINT8 | SataPortsEnableDitoConfig [8]
Offset 0x06B8 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
UINT8 | SataPortsDmVal [8]
Offset 0x06C0 - Enable SATA Port DmVal DITO multiplier. More...
UINT16 | SataPortsDitoVal [8]
Offset 0x06C8 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625.
UINT8 | SataPortsZpOdd [8]
Offset 0x06D8 - Enable SATA Port ZpOdd Support zero power ODD.
UINT8 | SataRstRaidDeviceId
Offset 0x06E0 - PCH Sata Rst Raid Device Id Enable RAID Alternate ID. More...
UINT8 | SataRstRaid0
Offset 0x06E1 - PCH Sata Rst Raid0 RAID0. More...
UINT8 | SataRstRaid1
Offset 0x06E2 - PCH Sata Rst Raid1 RAID1. More...
UINT8 | SataRstRaid10
Offset 0x06E3 - PCH Sata Rst Raid10 RAID10. More...
UINT8 | SataRstRaid5
Offset 0x06E4 - PCH Sata Rst Raid5 RAID5. More...
UINT8 | SataRstIrrt
Offset 0x06E5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology. More...
UINT8 | SataRstOromUiBanner
Offset 0x06E6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. More...
UINT8 | SataRstOromUiDelay
Offset 0x06E7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
UINT8 | SataRstHddUnlock
Offset 0x06E8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. More...
UINT8 | SataRstLedLocate
Offset 0x06E9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. More...
UINT8 | SataRstIrrtOnly
Offset 0x06EA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. More...
UINT8 | SataRstSmartStorage
Offset 0x06EB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. More...
UINT8 | SataRstPcieEnable [3]
Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping.
UINT8 | SataRstPcieStoragePort [3]
Offset 0x06EF - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
UINT8 | SataRstPcieDeviceResetDelay [3]
Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. More...
UINT8 | PchScsEmmcHs400TuningRequired
Offset 0x06F5 - Enable eMMC HS400 Training Deprecated. More...
UINT8 | PchScsEmmcHs400DllDataValid
Offset 0x06F6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. More...
UINT8 | PchScsEmmcHs400RxStrobeDll1
Offset 0x06F7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
UINT8 | PchScsEmmcHs400TxDataDll
Offset 0x06F8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
UINT8 | PchScsEmmcHs400DriverStrength
Offset 0x06F9 - I/O Driver Strength Deprecated. More...
UINT8 | PchSerialIoI2cPadsTermination [6]
Offset 0x06FA - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. More...
UINT8 | UnusedUpdSpace21
Offset 0x0700.
UINT8 | SerialIoUart0PinMuxing
Offset 0x0701 - PcdSerialIoUart0PinMuxing Select SerialIo Uart0 pin muxing. More...
UINT8 | UnusedUpdSpace22 [1]
Offset 0x0702.
UINT8 | SerialIoUartHwFlowCtrl [3]
Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS linesh.
UINT8 | SerialIoDebugUartNumber
Offset 0x0706 - UART Number For Debug Purpose UART number for debug purpose. More...
UINT8 | SerialIoEnableDebugUartAfterPost
Offset 0x0707 - Enable Debug UART Controller Enable debug UART controller after post. More...
UINT8 | PchSirqEnable
Offset 0x0708 - Enable Serial IRQ Determines if enable Serial IRQ. More...
UINT8 | PchSirqMode
Offset 0x0709 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. More...
UINT8 | PchStartFramePulse
Offset 0x070A - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. More...
UINT8 | ReservedForFuture1
Offset 0x070B - Reserved Reserved $EN_DIS.
UINT8 | PchTsmicLock
Offset 0x070C - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. More...
UINT16 | PchT0Level
Offset 0x070D - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
UINT16 | PchT1Level
Offset 0x070F - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
UINT16 | PchT2Level
Offset 0x0711 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
UINT8 | PchTTEnable
Offset 0x0713 - Enable The Thermal Throttle Enable the thermal throttle function. More...
UINT8 | PchTTState13Enable
Offset 0x0714 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
UINT8 | PchTTLock
Offset 0x0715 - Thermal Throttle Lock Thermal Throttle Lock. More...
UINT8 | TTSuggestedSetting
Offset 0x0716 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. More...
UINT8 | TTCrossThrottling
Offset 0x0717 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
UINT8 | PchDmiTsawEn
Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. More...
UINT8 | DmiSuggestedSetting
Offset 0x0719 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. More...
UINT8 | DmiTS0TW
Offset 0x071A - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values. More...
UINT8 | DmiTS1TW
Offset 0x071B - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. More...
UINT8 | DmiTS2TW
Offset 0x071C - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. More...
UINT8 | DmiTS3TW
Offset 0x071D - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. More...
UINT8 | SataP0T1M
Offset 0x071E - Port 0 T1 Multipler Port 0 T1 Multipler.
UINT8 | SataP0T2M
Offset 0x071F - Port 0 T2 Multipler Port 0 T2 Multipler.
UINT8 | SataP0T3M
Offset 0x0720 - Port 0 T3 Multipler Port 0 T3 Multipler.
UINT8 | SataP0TDisp
Offset 0x0721 - Port 0 Tdispatch Port 0 Tdispatch.
UINT8 | SataP1T1M
Offset 0x0722 - Port 1 T1 Multipler Port 1 T1 Multipler.
UINT8 | SataP1T2M
Offset 0x0723 - Port 1 T2 Multipler Port 1 T2 Multipler.
UINT8 | SataP1T3M
Offset 0x0724 - Port 1 T3 Multipler Port 1 T3 Multipler.
UINT8 | SataP1TDisp
Offset 0x0725 - Port 1 Tdispatch Port 1 Tdispatch.
UINT8 | SataP0Tinact
Offset 0x0726 - Port 0 Tinactive Port 0 Tinactive.
UINT8 | SataP0TDispFinit
Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. More...
UINT8 | SataP1Tinact
Offset 0x0728 - Port 1 Tinactive Port 1 Tinactive.
UINT8 | SataP1TDispFinit
Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. More...
UINT8 | SataThermalSuggestedSetting
Offset 0x072A - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. More...
UINT8 | PchMemoryThrottlingEnable
Offset 0x072B - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. More...
UINT8 | PchMemoryPmsyncEnable [2]
Offset 0x072C - Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT8 | PchMemoryC0TransmitEnable [2]
Offset 0x072E - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT8 | PchMemoryPinSelection [2]
Offset 0x0730 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT16 | PchTemperatureHotLevel
Offset 0x0732 - Thermal Device Temperature Decides the temperature.
UINT8 | PchEnableComplianceMode
Offset 0x0734 - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this option but this is disabled by default. More...
UINT8 | Usb2OverCurrentPin [16]
Offset 0x0735 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N.
UINT8 | Usb3OverCurrentPin [10]
Offset 0x0745 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N.
UINT8 | Enable8254ClockGating
Offset 0x074F - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. More...
UINT8 | SataRstOptaneMemory
Offset 0x0750 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
UINT8 | SataRstCpuAttachedStorage
Offset 0x0751 - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS.
UINT8 | Enable8254ClockGatingOnS3
Offset 0x0752 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. More...
UINT8 | UnusedUpdSpace23
Offset 0x0753.
UINT32 | PchPcieDeviceOverrideTablePtr
Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. More...
UINT8 | EnableTcoTimer
Offset 0x0758 - Enable TCO timer. More...
UINT64 | BgpdtHash [4]
Offset 0x0759 - BgpdtHash[4] BgpdtHash values.
UINT32 | BiosGuardAttr
Offset 0x0779 - BiosGuardAttr BiosGuardAttr default values.
UINT64 | BiosGuardModulePtr
Offset 0x077D - BiosGuardModulePtr BiosGuardModulePtr default values.
UINT64 | SendEcCmd
Offset 0x0785 - SendEcCmd SendEcCmd function pointer. More...
UINT8 | EcCmdProvisionEav
Offset 0x078D - EcCmdProvisionEav Ephemeral Authorization Value default values. More...
UINT8 | EcCmdLock
Offset 0x078E - EcCmdLock EcCmdLock default values. More...
UINT64 | SgxEpoch0
Offset 0x078F - SgxEpoch0 SgxEpoch0 default values.
UINT64 | SgxEpoch1
Offset 0x0797 - SgxEpoch1 SgxEpoch1 default values.
UINT8 | SgxSinitNvsData
Offset 0x079F - SgxSinitNvsData SgxSinitNvsData default values.
UINT8 | SiCsmFlag
Offset 0x07A0 - Si Config CSM Flag. More...
UINT32 | SiSsidTablePtr
Offset 0x07A1.
UINT16 | SiNumberOfSsidTableEntry
Offset 0x07A5.
UINT8 | SataRstInterrupt
Offset 0x07A7 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. More...
UINT8 | MeUnconfigOnRtcClear
Offset 0x07A8 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. More...
UINT8 | PsOnEnable
Offset 0x07A9 - Enable PS_ON. More...
UINT8 | PmcCpuC10GatePinEnable
Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. More...
UINT8 | PchDmiAspmCtrl
Offset 0x07AB - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. More...
UINT8 | ReservedFspsUpd [1]
Offset 0x07AC.

Detailed Description

Fsp S Configuration.

Definition at line 86 of file FspsUpd.h.

Member Data Documentation

UINT16 FSP_S_CONFIG::AcLoadline[5]

Offset 0x02B1 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie.

1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU.

Definition at line 965 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AcousticNoiseMitigation

Offset 0x02A2 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature.

This has to be enabled to program slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: Disabled; 1: Enabled $EN_DIS

Definition at line 925 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AmtEnabled

Offset 0x0155 - AMT Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS

Definition at line 571 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AmtKvmEnabled

Offset 0x0160 - KVM Switch Enable/Disable.

0: Disable, 1: enable, KVM enable/disable state by Mebx $EN_DIS

Definition at line 626 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AmtSolEnabled

Offset 0x015A - SOL Switch Enable/Disable.

0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx $EN_DIS

Definition at line 602 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AsfEnabled

Offset 0x0157 - ASF Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable ASF functionality. $EN_DIS

Definition at line 583 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::CpuMpHob

Offset 0x032F - CpuMpHob Pointer for CpuMpHob.

This is optional data buffer for CpuMpPpi usage.

Definition at line 1143 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::DcLoadline[5]

Offset 0x02C5 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie.

1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU.

Definition at line 975 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DebugInterfaceEnable

Offset 0x0333 - Enable or Disable processor debug features Enable or Disable processor debug features; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1149 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::DeltaT12PowerCycleDelay

Offset 0x0232 - Delta T12 Power Cycle Delay required in ms Select the value for delay required.

0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay

Definition at line 828 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::DevIntConfigPtr

Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.

The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.

Definition at line 214 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DmiSuggestedSetting

Offset 0x0719 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values.

$EN_DIS

Definition at line 2070 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DmiTS0TW

Offset 0x071A - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values.

0:x1, 1:x2, 2:x4, 3:x8, 4:x16

Definition at line 2076 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DmiTS1TW

Offset 0x071B - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width.

0:x1, 1:x2, 2:x4, 3:x8, 4:x16

Definition at line 2082 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DmiTS2TW

Offset 0x071C - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width.

0:x1, 1:x2, 2:x4, 3:x8, 4:x16

Definition at line 2088 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DmiTS3TW

Offset 0x071D - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width.

0:x1, 1:x2, 2:x4, 3:x8, 4:x16

Definition at line 2094 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EcCmdLock

Offset 0x078E - EcCmdLock EcCmdLock default values.

Locks Ephemeral Authorization Value sent previously

Definition at line 2285 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EcCmdProvisionEav

Offset 0x078D - EcCmdProvisionEav Ephemeral Authorization Value default values.

Provisions an ephemeral shared secret to the EC

Definition at line 2280 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Enable8254ClockGating

Offset 0x074F - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support.

However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. $EN_DIS

Definition at line 2213 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Enable8254ClockGatingOnS3

Offset 0x0752 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled.

FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. $EN_DIS

Definition at line 2233 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EnableTcoTimer

Offset 0x0758 - Enable TCO timer.

When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. $EN_DIS

Definition at line 2253 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EsataSpeedLimit

Offset 0x068E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.

$EN_DIS

Definition at line 1777 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableFivr

Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 1081 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableGt

Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 1007 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableIa

Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 932 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableSa

Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 1014 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::FivrRfiFrequency

Offset 0x030F - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.

0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock.

Definition at line 1062 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FivrSpreadSpectrum

Offset 0x0312 - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments.

0: 0%; Range: 0.0% to 10.0% (0-100).

Definition at line 1074 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ForcMebxSyncUp

Offset 0x0161 - MEBX execution Enable/Disable.

0: Disable, 1: enable, Force MEBX execution $EN_DIS

Definition at line 632 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FwProgress

Offset 0x0159 - PET Progress Enable/Disable.

0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. $EN_DIS

Definition at line 596 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::GpioIrqRoute

Offset 0x0088 - Select GPIO IRQ Route GPIO IRQ Select.

The valid value is 14 or 15.

Definition at line 232 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Heci3Enabled

Offset 0x014D - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.

0: disable, 1: enable $EN_DIS

Definition at line 524 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::IccMax[5]

Offset 0x02ED - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit.

0-255A in 1/4 A units. 400 = 100A

Definition at line 995 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ImonOffset[5]

Offset 0x0287 - Imon offset correction PCODE MMIO Mailbox: Imon offset correction.

Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto

Definition at line 881 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ImonSlope[5]

Offset 0x0282 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction.

Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes

Definition at line 875 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::ImonSlope1[5]

Offset 0x031A - Imon slope1 correction PCODE MMIO Mailbox: Imon slope correction.

Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes

Definition at line 1105 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::IslVrCmd

Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.

Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.

Definition at line 1099 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ManageabilityMode

Offset 0x0158 - Manageability Mode set by Mebx Enable/Disable.

0: Disable, 1: enable, Enable or disable Manageability Mode. $EN_DIS

Definition at line 589 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::McivrRfiFrequencyAdjust

Offset 0x030E - McIVR RFI Frequency Adjustment PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz.

For subtraction, change McivrRfiFrequencyPrefix. 0: Auto.

Definition at line 1055 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::McivrRfiFrequencyPrefix

Offset 0x030D - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix.

0: Plus (+); 1: Minus (-).

Definition at line 1049 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::McivrSpreadSpectrum

Offset 0x0311 - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum.

0: 0%; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.

Definition at line 1068 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::MeUnconfigOnRtcClear

Offset 0x07A8 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear.

1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos is clear, 3: Reserved

Definition at line 2328 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::NumOfDevIntConfig

Offset 0x007F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry.

If this is not zero, the DevIntConfigPtr must not be NULL.

Definition at line 220 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchCnviMode

Offset 0x0146 - CNVi Configuration This option allows for automatic detection of Connectivity Solution.

[Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto

Definition at line 481 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchCrid

Offset 0x0394 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled.

$EN_DIS

Definition at line 1373 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDmiAspm

Offset 0x0346 - Enable DMI ASPM Deprecated.

$EN_DIS

Definition at line 1161 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDmiAspmCtrl

Offset 0x07AB - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link.

Default is PchPcieAspmAutoConfig 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto

Definition at line 2349 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDmiTsawEn

Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable.

$EN_DIS

Definition at line 2064 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchEnableComplianceMode

Offset 0x0734 - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this option but this is disabled by default.

$EN_DIS

Definition at line 2195 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchEnableDbcObs

Offset 0x067C - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option.

Enable when DbC is used to avoid signaling conflicts. $EN_DIS

Definition at line 1687 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkDmic0

Offset 0x00FE - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link.

Muxed with SNDW4. $EN_DIS

Definition at line 341 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkDmic1

Offset 0x00FF - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link.

Muxed with SNDW3. $EN_DIS

Definition at line 347 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkHda

Offset 0x00FD - Enable HD Audio Link Enable/disable HD Audio Link.

Muxed with SSP0/SSP1/SNDW1. $EN_DIS

Definition at line 335 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkSndw1

Offset 0x0103 - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link.

Muxed with HDA. $EN_DIS

Definition at line 371 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkSndw2

Offset 0x0104 - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link.

Muxed with SSP1. $EN_DIS

Definition at line 377 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkSndw3

Offset 0x0105 - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link.

Muxed with DMIC1. $EN_DIS

Definition at line 383 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkSndw4

Offset 0x0106 - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link.

Muxed with DMIC0. $EN_DIS

Definition at line 389 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkSsp0

Offset 0x0100 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link.

Muxed with HDA. $EN_DIS

Definition at line 353 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkSsp1

Offset 0x0101 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link.

Muxed with HDA/SNDW2. $EN_DIS

Definition at line 359 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaAudioLinkSsp2

Offset 0x0102 - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link.

$EN_DIS

Definition at line 365 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspEnable

Offset 0x002D - Enable HD Audio DSP Enable/disable HD Audio DSP feature.

$EN_DIS

Definition at line 113 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspUaaCompliance

Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported).

$EN_DIS

Definition at line 1229 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaIDispCodecDisconnect

Offset 0x036D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.

$EN_DIS

Definition at line 1235 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaIDispLinkFrequency

Offset 0x036A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.

4: 96MHz, 3: 48MHz

Definition at line 1216 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaIDispLinkTmode

Offset 0x036B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.

0: 2T, 1: 1T

Definition at line 1222 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaLinkFrequency

Offset 0x0369 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.

0: 6MHz, 1: 12MHz, 2: 24MHz

Definition at line 1210 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaPme

Offset 0x0366 - Enable Pme Enable Azalia wake-on-ring.

$EN_DIS

Definition at line 1194 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaSndwBufferRcomp

Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.

$EN_DIS

Definition at line 395 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaVcType

Offset 0x0368 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1.

0: VC0, 1: VC1

Definition at line 1204 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHotEnable

Offset 0x014F - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel.

0: disable, 1: enable $EN_DIS

Definition at line 534 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicEntry24_119

Offset 0x037D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1251 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicId

Offset 0x037E - PCH Io Apic ID This member determines IOAPIC ID.

Default is 0x02.

Definition at line 1256 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp0GpioAssign

Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1302 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp1GpioAssign

Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1308 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp2GpioAssign

Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1314 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp3GpioAssign

Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1320 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp4GpioAssign

Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1326 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp5GpioAssign

Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1332 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp6GpioAssign

Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1338 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp7GpioAssign

Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1344 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c0GpioAssign

Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1284 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c1GpioAssign

Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1290 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c2GpioAssign

Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1296 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshPdtUnlock

Offset 0x038E - PCH ISH PDT Unlock Msg 0: False; 1: True.

$EN_DIS

Definition at line 1350 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshSpiGpioAssign

Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1266 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshUart0GpioAssign

Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1272 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshUart1GpioAssign

Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1278 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanEnable

Offset 0x00FC - Enable LAN Enable/disable LAN controller.

$EN_DIS

Definition at line 329 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanLtrEnable

Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1356 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLockDownBiosLock

Offset 0x0393 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection.

$EN_DIS

Definition at line 1367 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLockDownRtcMemoryLock

Offset 0x0395 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM.

$EN_DIS

Definition at line 1380 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchMemoryThrottlingEnable

Offset 0x072B - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.

$EN_DIS

Definition at line 2168 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PchPcieDeviceOverrideTablePtr

Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings.

This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0.

Definition at line 2245 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDeepSxPol

Offset 0x0675 - PCH Pm Deep Sx Pol Deep Sx Policy.

$EN_DIS

Definition at line 1639 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDisableDsxAcPresentPulldown

Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.

$EN_DIS

Definition at line 1721 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDisableNativePowerButton

Offset 0x0686 - PCH Pm Disable Native Power Button Power button native mode disable.

$EN_DIS

Definition at line 1731 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmLanWakeFromDeepSx

Offset 0x0674 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx.

$EN_DIS

Definition at line 1633 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmLpcClockRun

Offset 0x0680 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled.

Default value is Disabled $EN_DIS

Definition at line 1698 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmMeWakeSts

Offset 0x0688 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.

$EN_DIS

Definition at line 1743 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPciePllSsc

Offset 0x068B - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage.

The default is 0xFF: AUTO - No BIOS override.

Definition at line 1761 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPcieWakeFromDeepSx

Offset 0x0671 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx.

$EN_DIS

Definition at line 1614 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPmeB0S5Dis

Offset 0x0669 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.

$EN_DIS

Definition at line 1582 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPwrBtnOverridePeriod

Offset 0x0683 - PCH Pm Pwr Btn Override Period PCH power button override period.

000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.

Definition at line 1715 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPwrCycDur

Offset 0x068A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second.

Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ...

Definition at line 1755 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpAMinAssert

Offset 0x0679 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy.

Default is PchSlpA2s.

Definition at line 1659 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpLanLowDc

Offset 0x0682 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power.

$EN_DIS

Definition at line 1710 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0Enable

Offset 0x0687 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.

$EN_DIS

Definition at line 1737 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0Vm070VSupport

Offset 0x0153 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy.

0: disable, 1: enable $EN_DIS

Definition at line 559 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0Vm075VSupport

Offset 0x0154 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy.

0: disable, 1: enable $EN_DIS

Definition at line 565 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0VmRuntimeControl

Offset 0x0152 - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy.

0: disable, 1: enable $EN_DIS

Definition at line 553 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS3MinAssert

Offset 0x0676 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy.

Default is PchSlpS350ms.

Definition at line 1644 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS4MinAssert

Offset 0x0677 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy.

Default is PchSlpS44s.

Definition at line 1649 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpStrchSusUp

Offset 0x0681 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up.

$EN_DIS

Definition at line 1704 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpSusMinAssert

Offset 0x0678 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy.

Default is PchSlpSus4s.

Definition at line 1654 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmVrAlert

Offset 0x0151 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.

. 0: disable, 1: enable $EN_DIS

Definition at line 547 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWolEnableOverride

Offset 0x0670 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.

$EN_DIS

Definition at line 1608 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWolOvrWkSts

Offset 0x0689 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.

$EN_DIS

Definition at line 1749 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWoWlanDeepSxEnable

Offset 0x0673 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register.

$EN_DIS

Definition at line 1627 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWoWlanEnable

Offset 0x0672 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.

$EN_DIS

Definition at line 1620 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPwrOptEnable

Offset 0x0347 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side.

$EN_DIS

Definition at line 1167 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchScsEmmcHs400DllDataValid

Offset 0x06F6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid.

$EN_DIS

Definition at line 1926 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchScsEmmcHs400DriverStrength

Offset 0x06F9 - I/O Driver Strength Deprecated.

0:33 Ohm, 1:40 Ohm, 2:50 Ohm

Definition at line 1942 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchScsEmmcHs400TuningRequired

Offset 0x06F5 - Enable eMMC HS400 Training Deprecated.

$EN_DIS

Definition at line 1920 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSerialIoI2cPadsTermination[6]

Offset 0x06FA - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively.

One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.

Definition at line 1950 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSirqEnable

Offset 0x0708 - Enable Serial IRQ Determines if enable Serial IRQ.

$EN_DIS

Definition at line 1988 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSirqMode

Offset 0x0709 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.

$EN_DIS

Definition at line 1994 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchStartFramePulse

Offset 0x070A - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.

0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk

Definition at line 2000 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTsmicLock

Offset 0x070C - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip.

$EN_DIS

Definition at line 2012 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTEnable

Offset 0x0713 - Enable The Thermal Throttle Enable the thermal throttle function.

$EN_DIS

Definition at line 2033 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTLock

Offset 0x0715 - Thermal Throttle Lock Thermal Throttle Lock.

$EN_DIS

Definition at line 2046 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTState13Enable

Offset 0x0714 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.

$EN_DIS

Definition at line 2040 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchUsbHsioFilterSel[10]

Offset 0x036E - USB LFPS Filter selection For each byte bits 2:0 are for p, bits 4:6 are for n.

0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns.

Definition at line 1241 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchUsbHsioRxTuningEnable[10]

Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable Mask for enabling tuning of HSIO Rx signals of USB3 ports.

Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable

Definition at line 1462 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieComplianceTestMode

Offset 0x0665 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board.

$EN_DIS

Definition at line 1557 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieDisableRootPortClockGating

Offset 0x0662 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules.

0: Disable; 1: Enable. $EN_DIS

Definition at line 1541 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEnablePeerMemoryWrite

Offset 0x0663 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform.

$EN_DIS

Definition at line 1547 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEqPh3LaneParamCm[24]

Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM.

Coefficient C-1.

Definition at line 1519 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEqPh3LaneParamCp[24]

Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM.

Coefficient C+1.

Definition at line 1524 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpAspm[24]

Offset 0x05C8 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL).

Default is PchPcieAspmAutoConfig.

Definition at line 1498 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpCompletionTimeout[24]

Offset 0x0546 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT).

Default is PchPcieCompletionTO_Default.

Definition at line 1488 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PcieRpDpcExtensionsMask

Offset 0x0110 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports.

0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.

Definition at line 413 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PcieRpDpcMask

Offset 0x010C - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports.

0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.

Definition at line 407 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpFunctionSwap

Offset 0x0666 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled.

$EN_DIS

Definition at line 1564 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpGen3EqPh3Method[24]

Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD).

0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients.

Definition at line 1478 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpImrEnabled

Offset 0x066D - PCIE IMR Enables Isolated Memory Region for PCIe.

$EN_DIS

Definition at line 1593 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpL1Substates[24]

Offset 0x05E0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).

Default is PchPcieL1SubstatesL1_1_2.

Definition at line 1504 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpPcieSpeed[24]

Offset 0x04FE - PCIE RP Pcie Speed Determines each PCIE Port speed capability.

0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED).

Definition at line 1472 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpPhysicalSlotNumber[24]

Offset 0x052E - PCIE RP Physical Slot Number Indicates the slot number for the root port.

Default is the value as root port index.

Definition at line 1483 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PcieRpPtmMask

Offset 0x0108 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports.

0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.

Definition at line 401 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieSwEqCoeffListCm[5]

Offset 0x0658 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM.

Coefficient C-1.

Definition at line 1529 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieSwEqCoeffListCp[5]

Offset 0x065D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM.

Coefficient C+1.

Definition at line 1534 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PmcCpuC10GatePinEnable

Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin.

$EN_DIS

Definition at line 2343 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PmcDbgMsgEn

Offset 0x011F - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub.

Noted: When Enabled, may not enter S0ix $EN_DIS

Definition at line 452 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PmcModPhySusPgEnable

Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating.

Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS

Definition at line 677 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PmcPowerButtonDebounce

Offset 0x0115 - Power button debounce configuration Debounce time for PWRBTN in microseconds.

For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range

Definition at line 426 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PortUsb20Enable[16]

Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 185 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PortUsb30Enable[10]

Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 191 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PreWake

Offset 0x0328 - Pre Wake Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.

Range 0-255 0.

Definition at line 1119 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi1Threshold[5]

Offset 0x02CF - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments.

Range is 0-128A.

Definition at line 980 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi2Threshold[5]

Offset 0x02D9 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments.

Range is 0-128A.

Definition at line 985 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Psi3Enable[5]

Offset 0x0278 - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable.

For all VR Indexes

Definition at line 863 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi3Threshold[5]

Offset 0x02E3 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments.

Range is 0-128A.

Definition at line 990 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PsOnEnable

Offset 0x07A9 - Enable PS_ON.

PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. $EN_DIS

Definition at line 2336 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PsysOffset

Offset 0x02A1 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction.

0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset

Definition at line 917 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PsysSlope

Offset 0x02A0 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction.

0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25

Definition at line 911 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PxRcConfig[8]

Offset 0x0080 - PIRQx to IRQx Map Config PIRQx to IRQx mapping.

The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode.

Definition at line 227 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::RemoteAssistance

Offset 0x015F - Remote Assistance Trigger Availablilty Enable/Disable.

0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx $EN_DIS

Definition at line 620 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataEnable

Offset 0x0092 - Enable SATA Enable/disable SATA controller.

$EN_DIS

Definition at line 269 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataLedEnable

Offset 0x0150 - SATA LED SATA LED indicating SATA controller activity.

0: disable, 1: enable $EN_DIS

Definition at line 540 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataMode

Offset 0x0093 - SATA Mode Select SATA controller working mode.

0:AHCI, 1:RAID

Definition at line 275 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataP0TDispFinit

Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch.

$EN_DIS

Definition at line 2145 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataP1TDispFinit

Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch.

$EN_DIS

Definition at line 2156 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsDevSlp[8]

Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port.

0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 179 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsDmVal[8]

Offset 0x06C0 - Enable SATA Port DmVal DITO multiplier.

Default is 15.

Definition at line 1817 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsEnable[8]

Offset 0x0042 - Enable SATA ports Enable/disable SATA ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 173 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPwrOptEnable

Offset 0x068D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side.

$EN_DIS

Definition at line 1771 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstHddUnlock

Offset 0x06E8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled.

$EN_DIS

Definition at line 1880 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstInterrupt

Offset 0x07A7 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.

0:Msix, 1:Msi, 2:Legacy

Definition at line 2320 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstIrrt

Offset 0x06E5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology.

$EN_DIS

Definition at line 1863 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstIrrtOnly

Offset 0x06EA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports.

$EN_DIS

Definition at line 1893 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstLedLocate

Offset 0x06E9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.

$EN_DIS

Definition at line 1887 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstOromUiBanner

Offset 0x06E6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER.

$EN_DIS

Definition at line 1869 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstPcieDeviceResetDelay[3]

Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds.

Default value is 100ms

Definition at line 1914 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid0

Offset 0x06E1 - PCH Sata Rst Raid0 RAID0.

$EN_DIS

Definition at line 1839 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid1

Offset 0x06E2 - PCH Sata Rst Raid1 RAID1.

$EN_DIS

Definition at line 1845 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid10

Offset 0x06E3 - PCH Sata Rst Raid10 RAID10.

$EN_DIS

Definition at line 1851 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid5

Offset 0x06E4 - PCH Sata Rst Raid5 RAID5.

$EN_DIS

Definition at line 1857 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaidDeviceId

Offset 0x06E0 - PCH Sata Rst Raid Device Id Enable RAID Alternate ID.

0:Client, 1:Alternate, 2:Server

Definition at line 1833 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstSmartStorage

Offset 0x06EB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit.

$EN_DIS

Definition at line 1899 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataSalpSupport

Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management.

$EN_DIS

Definition at line 167 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataThermalSuggestedSetting

Offset 0x072A - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting.

$EN_DIS

Definition at line 2162 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SciIrqSelect

Offset 0x0089 - Select SciIrqSelect SCI IRQ Select.

The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.

Definition at line 237 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsEmmcEnabled

Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller.

$EN_DIS

Definition at line 123 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsEmmcHs400Enabled

Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode.

$EN_DIS

Definition at line 129 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsSdCardEnabled

Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller.

$EN_DIS

Definition at line 135 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsUfsEnabled

Offset 0x0145 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller.

$EN_DIS

Definition at line 474 of file FspsUpd.h.

UINT64 FSP_S_CONFIG::SendEcCmd

Offset 0x0785 - SendEcCmd SendEcCmd function pointer.

typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData);

Definition at line 2275 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SendVrMbxCmd

Offset 0x0303 - Enable VR specific mailbox command VR specific mailbox commands.

00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved. $EN_DIS

Definition at line 1022 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoDebugUartNumber

Offset 0x0706 - UART Number For Debug Purpose UART number for debug purpose.

0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:UART0, 1:UART1, 2:UART2

Definition at line 1976 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoDevMode[12]

Offset 0x006F - Enable SerialIo Device Mode 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device mode respectively.

One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.

Definition at line 209 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoEnableDebugUartAfterPost

Offset 0x0707 - Enable Debug UART Controller Enable debug UART controller after post.

$EN_DIS

Definition at line 1982 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoUart0PinMuxing

Offset 0x0701 - PcdSerialIoUart0PinMuxing Select SerialIo Uart0 pin muxing.

Setting applicable only if SerialIO UART0 is enabled. 0:default pins, 1:pins muxed with CNV_BRI/RGI

Definition at line 1960 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ShowSpiController

Offset 0x0034 - Show SPI controller Enable/disable to show SPI controller.

$EN_DIS

Definition at line 141 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SiCsmFlag

Offset 0x07A0 - Si Config CSM Flag.

Platform specific common policies that used by several silicon components. CSM status flag. $EN_DIS

Definition at line 2306 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SkipMpInit

Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization.

Deprecated:
SkipMpInit has been moved to FspmUpd $EN_DIS

Definition at line 1043 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForFivr

Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 1088 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForGt

Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 946 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForIa

Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 939 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForSa

Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 953 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlpS0DisQForDebug

Offset 0x067B - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe type.

'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.
Reminder: DCI OOB (aka BSSB) uses CCA probe.
Note: This BIOS option should keep 'Auto', other options are intended for advanced configuration only. 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto

Definition at line 1680 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlpS0Override

Offset 0x067A - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type.

Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled.
Note: This BIOS option should keep 'Auto', other options are intended for advanced configuration only. 0:Disabled, 1:Enabled, 2:Auto

Definition at line 1669 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlpS0WithGbeSupport

Offset 0x01FC - SlpS0WithGbeSupport Enable/Disable SLP_S0 with GBE Support.

0: disable, 1: enable $EN_DIS

Definition at line 683 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TcoIrqSelect

Offset 0x008A - Select TcoIrqSelect TCO IRQ Select.

The valid value is 9, 10, 11, 20, 21, 22, 23.

Definition at line 242 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::TdcPowerLimit[5]

Offset 0x02A7 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit.

Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes

Definition at line 959 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TdcTimeWindow[5]

Offset 0x0296 - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window.

Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe

Definition at line 899 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TetonGlacierCR

Offset 0x0668 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled.

Default is 0 for CNP-H system and 1 for CNP-LP system

Definition at line 1576 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TetonGlacierSupport

Offset 0x0667 - Teton Glacier Support Enables support for the Teton Glacier card.

$EN_DIS

Definition at line 1570 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TTSuggestedSetting

Offset 0x0716 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting.

$EN_DIS

Definition at line 2052 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TurboMode

Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode.

0: disable, 1: enable $EN_DIS

Definition at line 161 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TxtEnable

Offset 0x0305 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1033 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePehalfbit[16]

Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis.

1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port.

Definition at line 299 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePetxiset[16]

Offset 0x0094 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias.

000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.

Definition at line 281 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePredeemp[16]

Offset 0x00B4 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis.

00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.

Definition at line 293 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfeTxiset[16]

Offset 0x00A4 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias.

000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.

Definition at line 287 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDeEmph[10]

Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis).

One byte for each port.

Definition at line 311 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDeEmphEnable[10]

Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment.

Each value in arrary can be between 0-1. One byte for each port.

Definition at line 305 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDownscaleAmp[10]

Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h.

One byte for each port.

Definition at line 323 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDownscaleAmpEnable[10]

Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1.

One byte for each port.

Definition at line 317 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::UsbPdoProgramming

Offset 0x0114 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase.

Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS

Definition at line 420 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::VrPowerDeliveryDesign

Offset 0x0324 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board.

This value is an enum of the available power delivery segments that are defined in the Platform Design Guide.

Definition at line 1112 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::VrVoltageLimit[5]

Offset 0x02F7 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit.

Range is 0-7999mV.

Definition at line 1000 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::WatchDog

Offset 0x0156 - WatchDog Timer Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable WatchDog timer. $EN_DIS

Definition at line 577 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::WatchDogTimerBios

Offset 0x015D - BIOS Timer 16 bits Value, Set BIOS watchdog timer.

$EN_DIS

Definition at line 614 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::WatchDogTimerOs

Offset 0x015B - OS Timer 16 bits Value, Set OS watchdog timer.

$EN_DIS

Definition at line 608 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::XdciEnable

Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller.

$EN_DIS

Definition at line 197 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_S_TEST_CONFIG Struct Reference

Public Attributes | List of all members
FSP_S_TEST_CONFIG Struct Reference

Fsp S Test Configuration. More...

#include <FspsUpd.h>

Public Attributes

UINT32 | Signature
Offset 0x07AD.
UINT8 | ChapDeviceEnable
Offset 0x07B1 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disabled $EN_DIS.
UINT8 | SkipPamLock
Offset 0x07B2 - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS.
UINT8 | EdramTestMode
Offset 0x07B3 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode.
UINT8 | DmiExtSync
Offset 0x07B4 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS.
UINT8 | DmiIot
Offset 0x07B5 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control $EN_DIS.
UINT8 | PegMaxPayload [4]
Offset 0x07B6 - PEG Max Payload size per root port 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B.
UINT8 | RenderStandby
Offset 0x07BA - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS.
UINT8 | PmSupport
Offset 0x07BB - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS.
UINT8 | CdynmaxClampEnable
Offset 0x07BC - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS.
UINT8 | VtdDisable
Offset 0x07BD - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS.
UINT8 | GtFreqMax
Offset 0x07BE - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz.
UINT8 | DisableTurboGt
Offset 0x07BF - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS.
UINT8 | SaPostMemTestRsvd [11]
Offset 0x07C0 - SaPostMemTestRsvd Reserved for SA Post-Mem Test $EN_DIS.
UINT8 | OneCoreRatioLimit
Offset 0x07CB - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | TwoCoreRatioLimit
Offset 0x07CC - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | ThreeCoreRatioLimit
Offset 0x07CD - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | FourCoreRatioLimit
Offset 0x07CE - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | Hwp
Offset 0x07CF - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. More...
UINT8 | HdcControl
Offset 0x07D0 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. More...
UINT8 | PowerLimit1Time
Offset 0x07D1 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. More...
UINT8 | PowerLimit2
Offset 0x07D2 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. More...
UINT8 | TurboPowerLimitLock
Offset 0x07D3 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS.
UINT8 | PowerLimit3Time
Offset 0x07D4 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms.
UINT8 | PowerLimit3DutyCycle
Offset 0x07D5 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100.
UINT8 | PowerLimit3Lock
Offset 0x07D6 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS.
UINT8 | PowerLimit4Lock
Offset 0x07D7 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS.
UINT8 | TccActivationOffset
Offset 0x07D8 - TCC Activation Offset TCC Activation Offset. More...
UINT8 | TccOffsetClamp
Offset 0x07D9 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. More...
UINT8 | TccOffsetLock
Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. More...
UINT8 | NumberOfEntries
Offset 0x07DB - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. More...
UINT8 | Custom1PowerLimit1Time
Offset 0x07DC - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. More...
UINT8 | Custom1TurboActivationRatio
Offset 0x07DD - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. More...
UINT8 | Custom1ConfigTdpControl
Offset 0x07DE - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
UINT8 | Custom2PowerLimit1Time
Offset 0x07DF - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. More...
UINT8 | Custom2TurboActivationRatio
Offset 0x07E0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. More...
UINT8 | Custom2ConfigTdpControl
Offset 0x07E1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
UINT8 | Custom3PowerLimit1Time
Offset 0x07E2 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. More...
UINT8 | Custom3TurboActivationRatio
Offset 0x07E3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. More...
UINT8 | Custom3ConfigTdpControl
Offset 0x07E4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
UINT8 | ConfigTdpLock
Offset 0x07E5 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS.
UINT8 | ConfigTdpBios
Offset 0x07E6 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. More...
UINT8 | PsysPowerLimit1
Offset 0x07E7 - PL1 Enable value PL1 Enable value to limit average platform power. More...
UINT8 | PsysPowerLimit1Time
Offset 0x07E8 - PL1 timewindow PL1 timewindow in seconds. More...
UINT8 | PsysPowerLimit2
Offset 0x07E9 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power. More...
UINT8 | MlcStreamerPrefetcher
Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. More...
UINT8 | MlcSpatialPrefetcher
Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS.
UINT8 | MonitorMwaitEnable
Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. More...
UINT8 | MachineCheckEnable
Offset 0x07ED - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. More...
UINT8 | DebugInterfaceEnable
Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features. More...
UINT8 | DebugInterfaceLockEnable
Offset 0x07EF - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable. More...
UINT8 | ApIdleManner
Offset 0x07F0 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. More...
UINT8 | ProcessorTraceOutputScheme
Offset 0x07F1 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. More...
UINT8 | ProcessorTraceEnable
Offset 0x07F2 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. More...
UINT64 | ProcessorTraceMemBase
Offset 0x07F3 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace. More...
UINT32 | ProcessorTraceMemLength
Offset 0x07FB - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace. More...
UINT8 | VoltageOptimization
Offset 0x07FF - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable $EN_DIS.
UINT8 | Eist
Offset 0x0800 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. More...
UINT8 | EnergyEfficientPState
Offset 0x0801 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. More...
UINT8 | EnergyEfficientTurbo
Offset 0x0802 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. More...
UINT8 | TStates
Offset 0x0803 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. More...
UINT8 | BiProcHot
Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS.
UINT8 | DisableProcHotOut
Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. More...
UINT8 | ProcHotResponse
Offset 0x0806 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. More...
UINT8 | DisableVrThermalAlert
Offset 0x0807 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. More...
UINT8 | AutoThermalReporting
Offset 0x0808 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. More...
UINT8 | ThermalMonitor
Offset 0x0809 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS.
UINT8 | Cx
Offset 0x080A - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). More...
UINT8 | PmgCstCfgCtrlLock
Offset 0x080B - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. More...
UINT8 | C1e
Offset 0x080C - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. More...
UINT8 | PkgCStateDemotion
Offset 0x080D - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. More...
UINT8 | PkgCStateUnDemotion
Offset 0x080E - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. More...
UINT8 | CStatePreWake
Offset 0x080F - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. More...
UINT8 | TimedMwait
Offset 0x0810 - Enable or Disable TimedMwait Support. More...
UINT8 | CstCfgCtrIoMwaitRedirection
Offset 0x0811 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. More...
UINT8 | PkgCStateLimit
Offset 0x0812 - Set the Max Pkg Cstate Set the Max Pkg Cstate. More...
UINT8 | CstateLatencyControl0TimeUnit
Offset 0x0813 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl1TimeUnit
Offset 0x0814 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl2TimeUnit
Offset 0x0815 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl3TimeUnit
Offset 0x0816 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl4TimeUnit
Offset 0x0817 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | CstateLatencyControl5TimeUnit
Offset 0x0818 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
UINT8 | PpmIrmSetting
Offset 0x0819 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
UINT8 | ProcHotLock
Offset 0x081A - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS.
UINT8 | ConfigTdpLevel
Offset 0x081B - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate.
UINT8 | RaceToHalt
Offset 0x081C - Race To Halt Enable/Disable Race To Halt feature. More...
UINT8 | MaxRatio
Offset 0x081D - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F.
UINT8 | StateRatio [40]
Offset 0x081E - P-state ratios for custom P-state table P-state ratios for custom P-state table. More...
UINT8 | StateRatioMax16 [16]
Offset 0x0846 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. More...
UINT16 | PsysPmax
Offset 0x0856 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. More...
UINT16 | CstateLatencyControl0Irtl
Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl1Irtl
Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl2Irtl
Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl3Irtl
Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl4Irtl
Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
UINT16 | CstateLatencyControl5Irtl
Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
UINT32 | PowerLimit1
Offset 0x0864 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. More...
UINT32 | PowerLimit2Power
Offset 0x0868 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. More...
UINT32 | PowerLimit3
Offset 0x086C - Package PL3 power limit Package PL3 power limit. More...
UINT32 | PowerLimit4
Offset 0x0870 - Package PL4 power limit Package PL4 power limit. More...
UINT32 | TccOffsetTimeWindowForRatl
Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit. More...
UINT32 | Custom1PowerLimit1
Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. More...
UINT32 | Custom1PowerLimit2
Offset 0x087C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. More...
UINT32 | Custom2PowerLimit1
Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. More...
UINT32 | Custom2PowerLimit2
Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. More...
UINT32 | Custom3PowerLimit1
Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. More...
UINT32 | Custom3PowerLimit2
Offset 0x088C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. More...
UINT32 | PsysPowerLimit1Power
Offset 0x0890 - Platform PL1 power Platform PL1 power. More...
UINT32 | PsysPowerLimit2Power
Offset 0x0894 - Platform PL2 power Platform PL2 power. More...
UINT8 | ThreeStrikeCounterDisable
Offset 0x0898 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. More...
UINT8 | HwpInterruptControl
Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. More...
UINT8 | FiveCoreRatioLimit
Offset 0x089A - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | SixCoreRatioLimit
Offset 0x089B - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | SevenCoreRatioLimit
Offset 0x089C - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | EightCoreRatioLimit
Offset 0x089D - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
UINT8 | EnableItbm
Offset 0x089E - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. More...
UINT8 | EnableItbmDriver
Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled $EN_DIS.
UINT8 | C1StateAutoDemotion
Offset 0x08A0 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. More...
UINT8 | C1StateUnDemotion
Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. More...
UINT8 | CpuWakeUpTimer
Offset 0x08A2 - CpuWakeUpTimer Enable long CPU Wakeup Timer. More...
UINT8 | MinRingRatioLimit
Offset 0x08A3 - Minimum Ring ratio limit override Minimum Ring ratio limit override. More...
UINT8 | MaxRingRatioLimit
Offset 0x08A4 - Minimum Ring ratio limit override Maximum Ring ratio limit override. More...
UINT8 | C3StateAutoDemotion
Offset 0x08A5 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion. More...
UINT8 | C3StateUnDemotion
Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion. More...
UINT8 | ReservedCpuPostMemTest [19]
Offset 0x08A7 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS.
UINT8 | SgxSinitDataFromTpm
Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values.
UINT8 | EndOfPostMessage
Offset 0x08BB - End of Post message Test, Send End of Post message. More...
UINT8 | DisableD0I3SettingForHeci
Offset 0x08BC - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS.
UINT16 | PchHdaResetWaitTimer
Offset 0x08BD - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds. More...
UINT8 | PchLockDownGlobalSmi
Offset 0x08BF - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. More...
UINT8 | PchLockDownBiosInterface
Offset 0x08C0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. More...
UINT8 | PchUnlockGpioPads
Offset 0x08C1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. More...
UINT8 | PchSbiUnlock
Offset 0x08C2 - PCH Unlock SBI access Deprecated $EN_DIS.
UINT8 | PchSbAccessUnlock
Offset 0x08C3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. More...
UINT16 | PcieRpLtrMaxSnoopLatency [24]
Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency.
UINT16 | PcieRpLtrMaxNoSnoopLatency [24]
Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency.
UINT8 | PcieRpSnoopLatencyOverrideMode [24]
Offset 0x0924 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode.
UINT8 | PcieRpSnoopLatencyOverrideMultiplier [24]
Offset 0x093C - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier.
UINT16 | PcieRpSnoopLatencyOverrideValue [24]
Offset 0x0954 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value.
UINT8 | PcieRpNonSnoopLatencyOverrideMode [24]
Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
UINT8 | PcieRpNonSnoopLatencyOverrideMultiplier [24]
Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
UINT16 | PcieRpNonSnoopLatencyOverrideValue [24]
Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value.
UINT8 | PcieRpSlotPowerLimitScale [24]
Offset 0x09E4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. More...
UINT16 | PcieRpSlotPowerLimitValue [24]
Offset 0x09FC - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. More...
UINT8 | PcieRpUptp [24]
Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. More...
UINT8 | PcieRpDptp [24]
Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. More...
UINT8 | PcieEnablePort8xhDecode
Offset 0x0A5C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. More...
UINT8 | PchPciePort8xhDecodePortIndex
Offset 0x0A5D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
UINT8 | PchPmDisableEnergyReport
Offset 0x0A5E - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. More...
UINT8 | SataTestMode
Offset 0x0A5F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. More...
UINT8 | PchXhciOcLock
Offset 0x0A60 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. More...
UINT8 | UnusedUpdSpace24 [17]
Offset 0x0A61.
UINT8 | SkipPostBootSai
Offset 0x0A72 - Skip POSTBOOT SAI Deprecated $EN_DIS.
UINT8 | MctpBroadcastCycle
Offset 0x0A73 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. More...
UINT8 | ReservedFspsTestUpd [12]
Offset 0x0A74.

Detailed Description

Fsp S Test Configuration.

Definition at line 2358 of file FspsUpd.h.

Member Data Documentation

UINT8 FSP_S_TEST_CONFIG::ApIdleManner

Offset 0x07F0 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop.

1: HALT loop, 2: MWAIT loop, 3: RUN loop

Definition at line 2681 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::AutoThermalReporting

Offset 0x0808 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2767 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C1e

Offset 0x080C - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states.

0: Disable; 1: Enable $EN_DIS

Definition at line 2791 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C1StateAutoDemotion

Offset 0x08A0 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion.

Disable; 1: Enable $EN_DIS

Definition at line 3083 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C1StateUnDemotion

Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion.

Disable; 1: Enable $EN_DIS

Definition at line 3089 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C3StateAutoDemotion

Offset 0x08A5 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion.

Disable; 1: Enable $EN_DIS

Definition at line 3114 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C3StateUnDemotion

Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion.

Disable; 1: Enable $EN_DIS

Definition at line 3120 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ConfigTdpBios

Offset 0x07E6 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2620 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CpuWakeUpTimer

Offset 0x08A2 - CpuWakeUpTimer Enable long CPU Wakeup Timer.

When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable $EN_DIS

Definition at line 3096 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CStatePreWake

Offset 0x080F - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake.

0: Disable; 1: Enable $EN_DIS

Definition at line 2809 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CstCfgCtrIoMwaitRedirection

Offset 0x0811 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2821 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1ConfigTdpControl

Offset 0x07DE - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2576 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom1PowerLimit1

Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2982 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1PowerLimit1Time

Offset 0x07DC - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1.

Valid Range 0 to 128, 0 = AUTO

Definition at line 2566 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom1PowerLimit2

Offset 0x087C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2988 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1TurboActivationRatio

Offset 0x07DD - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1.

Valid Range 0 to 255

Definition at line 2571 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2ConfigTdpControl

Offset 0x07E1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2592 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom2PowerLimit1

Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2994 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2PowerLimit1Time

Offset 0x07DF - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2.

Valid Range 0 to 128, 0 = AUTO

Definition at line 2582 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom2PowerLimit2

Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3000 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2TurboActivationRatio

Offset 0x07E0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2.

Valid Range 0 to 255

Definition at line 2587 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3ConfigTdpControl

Offset 0x07E4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2608 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom3PowerLimit1

Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3006 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3PowerLimit1Time

Offset 0x07E2 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3.

Valid Range 0 to 128, 0 = AUTO

Definition at line 2598 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom3PowerLimit2

Offset 0x088C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3012 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3TurboActivationRatio

Offset 0x07E3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3.

Valid Range 0 to 255

Definition at line 2603 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Cx

Offset 0x080A - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states).

0: Disable; 1: Enable $EN_DIS

Definition at line 2779 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DebugInterfaceEnable

Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features.

Deprecated:
Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS

Definition at line 2669 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DebugInterfaceLockEnable

Offset 0x07EF - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2675 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DisableProcHotOut

Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2749 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DisableVrThermalAlert

Offset 0x0807 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2761 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EightCoreRatioLimit

Offset 0x089D - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3065 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Eist

Offset 0x0800 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology.

0: Disable; 1: Enable $EN_DIS

Definition at line 2717 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnableItbm

Offset 0x089E - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0.

0: Disabled; 1: Enabled $EN_DIS

Definition at line 3071 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EndOfPostMessage

Offset 0x08BB - End of Post message Test, Send End of Post message.

Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved

Definition at line 3138 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnergyEfficientPState

Offset 0x0801 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode.

Disable; 1: Enable $EN_DIS

Definition at line 2724 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnergyEfficientTurbo

Offset 0x0802 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode.

Disable; 1: Enable $EN_DIS

Definition at line 2731 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::FiveCoreRatioLimit

Offset 0x089A - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3044 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::FourCoreRatioLimit

Offset 0x07CE - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2477 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::HdcControl

Offset 0x07D0 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration.

0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS

Definition at line 2490 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Hwp

Offset 0x07CF - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support.

0: Disable; 1: Enable; 2-3:Reserved $EN_DIS

Definition at line 2484 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::HwpInterruptControl

Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 3037 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MachineCheckEnable

Offset 0x07ED - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2663 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MaxRingRatioLimit

Offset 0x08A4 - Minimum Ring ratio limit override Maximum Ring ratio limit override.

0: Hardware defaults. Range: 0 - Max turbo ratio limit

Definition at line 3108 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MctpBroadcastCycle

Offset 0x0A73 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable.

$EN_DIS

Definition at line 3288 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MinRingRatioLimit

Offset 0x08A3 - Minimum Ring ratio limit override Minimum Ring ratio limit override.

0: Hardware defaults. Range: 0 - Max turbo ratio limit

Definition at line 3102 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MlcStreamerPrefetcher

Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2645 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MonitorMwaitEnable

Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2657 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::NumberOfEntries

Offset 0x07DB - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states.

At least 2 states must be present

Definition at line 2560 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::OneCoreRatioLimit

Offset 0x07CB - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255

Definition at line 2459 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PchHdaResetWaitTimer

Offset 0x08BD - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds.

Default is 600.

Definition at line 3150 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchLockDownBiosInterface

Offset 0x08C0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.

$EN_DIS

Definition at line 3162 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchLockDownGlobalSmi

Offset 0x08BF - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.

$EN_DIS

Definition at line 3156 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchPmDisableEnergyReport

Offset 0x0A5E - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature.

$EN_DIS

Definition at line 3259 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchSbAccessUnlock

Offset 0x08C3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g.

PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS

Definition at line 3181 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchUnlockGpioPads

Offset 0x08C1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose.

$EN_DIS

Definition at line 3168 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchXhciOcLock

Offset 0x0A60 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.

$EN_DIS

Definition at line 3272 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieEnablePort8xhDecode

Offset 0x0A5C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled.

0: Disable; 1: Enable. $EN_DIS

Definition at line 3248 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpDptp[24]

Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization.

Used for all lanes. Default is 7.

Definition at line 3241 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpSlotPowerLimitScale[24]

Offset 0x09E4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value.

Leave as 0 to set to default.

Definition at line 3226 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PcieRpSlotPowerLimitValue[24]

Offset 0x09FC - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot.

Leave as 0 to set to default.

Definition at line 3231 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpUptp[24]

Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization.

Used for all lanes. Default is 5.

Definition at line 3236 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateDemotion

Offset 0x080D - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion.

0: Disable; 1: Enable $EN_DIS

Definition at line 2797 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateLimit

Offset 0x0812 - Set the Max Pkg Cstate Set the Max Pkg Cstate.

Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto

Definition at line 2828 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateUnDemotion

Offset 0x080E - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion.

0: Disable; 1: Enable $EN_DIS

Definition at line 2803 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PmgCstCfgCtrlLock

Offset 0x080B - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2785 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit1

Offset 0x0864 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125

Definition at line 2952 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PowerLimit1Time

Offset 0x07D1 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds.

0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128

Definition at line 2497 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PowerLimit2

Offset 0x07D2 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode.

0 : Disable; 1: Enable $EN_DIS

Definition at line 2503 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit2Power

Offset 0x0868 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2958 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit3

Offset 0x086C - Package PL3 power limit Package PL3 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2964 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit4

Offset 0x0870 - Package PL4 power limit Package PL4 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125

Definition at line 2970 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcessorTraceEnable

Offset 0x07F2 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2693 of file FspsUpd.h.

UINT64 FSP_S_TEST_CONFIG::ProcessorTraceMemBase

Offset 0x07F3 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace.

Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable

Definition at line 2699 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::ProcessorTraceMemLength

Offset 0x07FB - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace.

Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable

Definition at line 2705 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcessorTraceOutputScheme

Offset 0x07F1 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.

0: Single Range Output, 1: ToPA Output

Definition at line 2687 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcHotResponse

Offset 0x0806 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2755 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PsysPmax

Offset 0x0856 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax.

0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W

Definition at line 2916 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit1

Offset 0x07E7 - PL1 Enable value PL1 Enable value to limit average platform power.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2626 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PsysPowerLimit1Power

Offset 0x0890 - Platform PL1 power Platform PL1 power.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3018 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit1Time

Offset 0x07E8 - PL1 timewindow PL1 timewindow in seconds.

0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128

Definition at line 2632 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit2

Offset 0x07E9 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2639 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PsysPowerLimit2Power

Offset 0x0894 - Platform PL2 power Platform PL2 power.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3024 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::RaceToHalt

Offset 0x081C - Race To Halt Enable/Disable Race To Halt feature.

RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable $EN_DIS

Definition at line 2889 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SataTestMode

Offset 0x0A5F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes.

$EN_DIS

Definition at line 3265 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SevenCoreRatioLimit

Offset 0x089C - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3058 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SixCoreRatioLimit

Offset 0x089B - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3051 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::StateRatio[40]

Offset 0x081E - P-state ratios for custom P-state table P-state ratios for custom P-state table.

NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F

Definition at line 2901 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::StateRatioMax16[16]

Offset 0x0846 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table.

This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F

Definition at line 2910 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccActivationOffset

Offset 0x07D8 - TCC Activation Offset TCC Activation Offset.

Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, For all other SKUs the recommended default are 0

Definition at line 2539 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccOffsetClamp

Offset 0x07D9 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled.

$EN_DIS

Definition at line 2547 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccOffsetLock

Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled.

$EN_DIS

Definition at line 2554 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::TccOffsetTimeWindowForRatl

Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125

Definition at line 2976 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ThreeCoreRatioLimit

Offset 0x07CD - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2471 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ThreeStrikeCounterDisable

Offset 0x0898 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True.

0: False, 1: True

Definition at line 3031 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TimedMwait

Offset 0x0810 - Enable or Disable TimedMwait Support.

Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS

Definition at line 2815 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TStates

Offset 0x0803 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2737 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TwoCoreRatioLimit

Offset 0x07CC - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2465 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_T_CONFIG Struct Reference

Public Attributes | List of all members
FSP_T_CONFIG Struct Reference

Fsp T Configuration. More...

#include <FsptUpd.h>

Public Attributes

UINT8 | PcdSerialIoUartDebugEnable
Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. More...
UINT8 | PcdSerialIoUartNumber
Offset 0x0041 - PcdSerialIoUartNumber - FSPT Select SerialIo Uart Controller for debug. More...
UINT8 | PcdSerialIoUart0PinMuxing
Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT Select SerialIo Uart0 pin muxing. More...
UINT8 | UnusedUpdSpace0
Offset 0x0043.
UINT32 | PcdSerialIoUartInputClock
Offset 0x0044.
UINT64 | PcdPciExpressBaseAddress
Offset 0x0048 - Pci Express Base Address Base address to be programmed for Pci Express.
UINT32 | PcdPciExpressRegionLength
Offset 0x0050 - Pci Express Region Length Region Length to be programmed for Pci Express.
UINT8 | ReservedFsptUpd1 [44]
Offset 0x0054.

Detailed Description

Fsp T Configuration.

Definition at line 68 of file FsptUpd.h.

Member Data Documentation

UINT8 FSP_T_CONFIG::PcdSerialIoUart0PinMuxing

Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT Select SerialIo Uart0 pin muxing.

Setting valid only if PcdSerialIoUartNumber is set to UART0. 0:default pins, 1:pins muxed with CNV_BRI/RGI

Definition at line 88 of file FsptUpd.h.

UINT8 FSP_T_CONFIG::PcdSerialIoUartDebugEnable

Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.

0:Disable, 1:Enable and Initialize, 2:Enable without Initializing

Definition at line 74 of file FsptUpd.h.

UINT8 FSP_T_CONFIG::PcdSerialIoUartNumber

Offset 0x0041 - PcdSerialIoUartNumber - FSPT Select SerialIo Uart Controller for debug.

Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2

Definition at line 81 of file FsptUpd.h.

The documentation for this struct was generated from the following file:
  • FsptUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPM_UPD Struct Reference

Public Attributes | List of all members
FSPM_UPD Struct Reference

Fsp M UPD Configuration. More...

#include <FspmUpd.h>

Collaboration diagram for FSPM_UPD:
[legend]

Public Attributes

FSP_UPD_HEADER | FspUpdHeader
Offset 0x0000.
FSPM_ARCH_UPD | FspmArchUpd
Offset 0x0020.
FSP_M_CONFIG FspmConfig
Offset 0x0040.
UINT8 | UnusedUpdSpace7
Offset 0x051F.
FSP_M_TEST_CONFIG FspmTestConfig
Offset 0x0520.
UINT32 | UpdTerminator
Offset 0x05BC.

Detailed Description

Fsp M UPD Configuration.

Definition at line 2810 of file FspmUpd.h.

The documentation for this struct was generated from the following file:
  • FspmUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPS_UPD Struct Reference

Public Attributes | List of all members
FSPS_UPD Struct Reference

Fsp S UPD Configuration. More...

#include <FspsUpd.h>

Collaboration diagram for FSPS_UPD:
[legend]

Public Attributes

FSP_UPD_HEADER | FspUpdHeader
Offset 0x0000.
FSP_S_CONFIG FspsConfig
Offset 0x0020.
FSP_S_TEST_CONFIG FspsTestConfig
Offset 0x07AD.
UINT16 | UpdTerminator
Offset 0x0A80.

Detailed Description

Fsp S UPD Configuration.

Definition at line 3297 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPT_CORE_UPD Struct Reference

Public Attributes | List of all members
FSPT_CORE_UPD Struct Reference

Fsp T Core UPD. More...

#include <FsptUpd.h>

Public Attributes

UINT32 | MicrocodeRegionBase
Offset 0x0020.
UINT32 | MicrocodeRegionSize
Offset 0x0024.
UINT32 | CodeRegionBase
Offset 0x0028.
UINT32 | CodeRegionSize
Offset 0x002C.
UINT8 | Reserved [16]
Offset 0x0030.

Detailed Description

Fsp T Core UPD.

Definition at line 43 of file FsptUpd.h.

The documentation for this struct was generated from the following file:
  • FsptUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSPT_UPD Struct Reference

Public Attributes | List of all members
FSPT_UPD Struct Reference

Fsp T UPD Configuration. More...

#include <FsptUpd.h>

Collaboration diagram for FSPT_UPD:
[legend]

Public Attributes

FSP_UPD_HEADER | FspUpdHeader
Offset 0x0000.
FSPT_CORE_UPD FsptCoreUpd
Offset 0x0020.
FSP_T_CONFIG FsptConfig
Offset 0x0040.
UINT16 | UpdTerminator
Offset 0x0080.

Detailed Description

Fsp T UPD Configuration.

Definition at line 115 of file FsptUpd.h.

The documentation for this struct was generated from the following file:
  • FsptUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: GPIO_CONFIG Struct Reference

Public Attributes | List of all members
GPIO_CONFIG Struct Reference

GPIO configuration structure used for pin programming. More...

#include <GpioConfig.h>

Public Attributes

UINT32 | PadMode: 5
Pad Mode Pad can be set as GPIO or one of its native functions. More...
UINT32 | HostSoftPadOwn: 2
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode. More...
UINT32 | Direction: 6
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. More...
UINT32 | OutputState: 2
Output State Set Pad output value. More...
UINT32 | InterruptConfig: 9
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). More...
UINT32 | PowerConfig: 8
GPIO Power Configuration. More...
UINT32 | ElectricalConfig: 9
GPIO Electrical Configuration This setting controls pads termination. More...
UINT32 | LockConfig: 4
GPIO Lock Configuration This setting controls pads lock. More...
UINT32 | OtherSettings: 9
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
UINT32 | RsvdBits: 10
Reserved bits for future extension.

Detailed Description

GPIO configuration structure used for pin programming.

Structure contains fields that can be used to configure pad.

Definition at line 36 of file GpioConfig.h.

Member Data Documentation

UINT32 GPIO_CONFIG::Direction

GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.

Refer to definition of GPIO_DIRECTION for supported settings.

Definition at line 57 of file GpioConfig.h.

UINT32 GPIO_CONFIG::ElectricalConfig

GPIO Electrical Configuration This setting controls pads termination.

Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.

Definition at line 83 of file GpioConfig.h.

UINT32 GPIO_CONFIG::HostSoftPadOwn

Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.

Refer to definition of GPIO_HOSTSW_OWN.

Definition at line 51 of file GpioConfig.h.

UINT32 GPIO_CONFIG::InterruptConfig

GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).

This setting is applicable only if GPIO is in GpioMode with input enabled. Refer to definition of GPIO_INT_CONFIG for supported settings.

Definition at line 71 of file GpioConfig.h.

UINT32 GPIO_CONFIG::LockConfig

GPIO Lock Configuration This setting controls pads lock.

Refer to definition of GPIO_LOCK_CONFIG for supported settings.

Definition at line 89 of file GpioConfig.h.

UINT32 GPIO_CONFIG::OutputState

Output State Set Pad output value.

Refer to definition of GPIO_OUTPUT_STATE for supported settings. This setting takes place when output is enabled.

Definition at line 64 of file GpioConfig.h.

UINT32 GPIO_CONFIG::PadMode

Pad Mode Pad can be set as GPIO or one of its native functions.

When in native mode setting Direction (except Inversion), OutputState, InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. Refer to definition of GPIO_PAD_MODE. Refer to EDS for each native mode according to the pad.

Definition at line 45 of file GpioConfig.h.

UINT32 GPIO_CONFIG::PowerConfig

GPIO Power Configuration.

This setting controls Pad Reset Configuration. Refer to definition of GPIO_RESET_CONFIG for supported settings.

Definition at line 77 of file GpioConfig.h.

The documentation for this struct was generated from the following file:
  • GpioConfig.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: HOB_USAGE_DATA_HOB Struct Reference

List of all members
HOB_USAGE_DATA_HOB Struct Reference

Hob Usage Data Hob. More...

#include <HobUsageDataHob.h>

Detailed Description

Hob Usage Data Hob.

Revision 1:

  • Initial version.

Definition at line 30 of file HobUsageDataHob.h.

The documentation for this struct was generated from the following file:
  • HobUsageDataHob.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: MEMORY_PLATFORM_DATA Struct Reference

List of all members
MEMORY_PLATFORM_DATA Struct Reference

Memory Platform Data Hob. More...

#include <MemInfoHob.h>

Detailed Description

Memory Platform Data Hob.

Revision 1:

  • Initial version. Revision 2:
  • Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields

Definition at line 247 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SI_PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

Public Attributes | List of all members
SI_PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...

#include <FspsUpd.h>

Public Attributes

UINT8 | Device
Device number.
UINT8 | Function
Device function.
UINT8 | IntX
Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
UINT8 | Irq
IRQ to be set for device.

Detailed Description

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.

Definition at line 74 of file FspsUpd.h.

The documentation for this struct was generated from the following file:
  • FspsUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SMBIOS_CACHE_INFO Struct Reference

Public Attributes | List of all members
SMBIOS_CACHE_INFO Struct Reference

SMBIOS Cache Info HOB Structure. More...

#include <SmbiosCacheInfoHob.h>

Public Attributes

UINT16 | NumberOfCacheLevels
Based on Number of Cache Types L1/L2/L3.
UINT8 | SocketDesignationStrIndex
String Index in the string Buffer. Example "L1-CACHE".
UINT16 | CacheConfiguration
Format defined in SMBIOS Spec v3.1 Section7.8 Table36.
UINT16 | MaxCacheSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
UINT16 | InstalledSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
UINT16 | SupportedSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
UINT16 | CurrentSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
UINT8 | CacheSpeed
Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 | ErrorCorrectionType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3.
UINT8 | SystemCacheType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4.
UINT8 | Associativity
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5.
UINT32 | MaximumCacheSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.
UINT32 | InstalledSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.

Detailed Description

SMBIOS Cache Info HOB Structure.

Definition at line 30 of file SmbiosCacheInfoHob.h.

The documentation for this struct was generated from the following file:
  • SmbiosCacheInfoHob.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SMBIOS_PROCESSOR_INFO Struct Reference

Public Attributes | List of all members
SMBIOS_PROCESSOR_INFO Struct Reference

SMBIOS Processor Info HOB Structure. More...

#include <SmbiosProcessorInfoHob.h>

Public Attributes

UINT8 | ProcessorType
ENUM defined in SMBIOS Spec v3.1 Section 7.5.1.
UINT16 | ProcessorFamily
This info is used for both ProcessorFamily and ProcessorFamily2 fields See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2.
UINT8 | ProcessorManufacturerStrIndex
Index of the String in the String Buffer.
UINT64 | ProcessorId
ENUM defined in SMBIOS Spec v3.1 Section 7.5.3.
UINT8 | ProcessorVersionStrIndex
Index of the String in the String Buffer.
UINT8 | Voltage
Format defined in SMBIOS Spec v3.1 Section 7.5.4.
UINT16 | ExternalClockInMHz
External Clock Frequency. Set to 0 if unknown.
UINT16 | CurrentSpeedInMHz
Snapshot of current processor speed during boot.
UINT8 | Status
Format defined in the SMBIOS Spec v3.1 Table 21.
UINT8 | ProcessorUpgrade
ENUM defined in SMBIOS Spec v3.1 Section 7.5.5.
UINT16 | CoreCount
This info is used for both CoreCount & CoreCount2 fields See detailed description in SMBIOS Spec v3.1 Section 7.5.6.
UINT16 | EnabledCoreCount
This info is used for both CoreEnabled & CoreEnabled2 fields See detailed description in SMBIOS Spec v3.1 Section 7.5.7.
UINT16 | ThreadCount
This info is used for both ThreadCount & ThreadCount2 fields See detailed description in SMBIOS Spec v3.1 Section 7.5.8.
UINT16 | ProcessorCharacteristics
Format defined in SMBIOS Spec v3.1 Section 7.5.9.

Detailed Description

SMBIOS Processor Info HOB Structure.

Definition at line 29 of file SmbiosProcessorInfoHob.h.

The documentation for this struct was generated from the following file:
  • SmbiosProcessorInfoHob.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SMBIOS_STRUCTURE Struct Reference

List of all members
SMBIOS_STRUCTURE Struct Reference

The Smbios structure header. More...

#include <FirmwareVersionInfoHob.h>

Detailed Description

The Smbios structure header.

Definition at line 48 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Index

Class Index
A | C | D | F | G | H | M | S
A
F
FSP_S_TEST_CONFIG
H
SMBIOS_CACHE_INFO
FSP_T_CONFIG SMBIOS_PROCESSOR_INFO
AUDIO_AZALIA_VERB_TABLE FIRMWARE_VERSION FSPM_UPD HOB_USAGE_DATA_HOB SMBIOS_STRUCTURE
AZALIA_HEADER FIRMWARE_VERSION_INFO FSPS_UPD
M
C
FIRMWARE_VERSION_INFO_HOB FSPT_CORE_UPD
FSP_M_CONFIG FSPT_UPD MEMORY_PLATFORM_DATA
CHIPSET_INIT_INFO FSP_M_TEST_CONFIG
G
S
D
FSP_S_CONFIG
GPIO_CONFIG SI_PCH_DEVICE_INTERRUPT_CONFIG
DIMM_INFO
A | C | D | F | G | H | M | S


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • AcLoadline : FSP_S_CONFIG
  • AcousticNoiseMitigation : FSP_S_CONFIG
  • ActEnergyCh0Dimm0 : FSP_M_CONFIG
  • ActEnergyCh0Dimm1 : FSP_M_CONFIG
  • ActEnergyCh1Dimm0 : FSP_M_CONFIG
  • ActEnergyCh1Dimm1 : FSP_M_CONFIG
  • ActiveCoreCount : FSP_M_CONFIG
  • AesEnable : FSP_S_CONFIG
  • ALIASCHK : FSP_M_CONFIG
  • AmtEnabled : FSP_S_CONFIG
  • AmtKvmEnabled : FSP_S_CONFIG
  • AmtSolEnabled : FSP_S_CONFIG
  • ApertureSize : FSP_M_CONFIG
  • ApIdleManner : FSP_S_TEST_CONFIG
  • ApStartupBase : FSP_M_CONFIG
  • AsfEnabled : FSP_S_CONFIG
  • Associativity : SMBIOS_CACHE_INFO
  • AutoThermalReporting : FSP_S_TEST_CONFIG
  • Avx2RatioOffset : FSP_M_CONFIG
  • Avx3RatioOffset : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- b -

  • BclkAdaptiveVoltage : FSP_M_CONFIG
  • BClkFrequency : FSP_M_CONFIG
  • BdatEnable : FSP_M_TEST_CONFIG
  • BdatTestType : FSP_M_TEST_CONFIG
  • BgpdtHash : FSP_S_CONFIG
  • BiosAcmBase : FSP_M_CONFIG
  • BiosAcmSize : FSP_M_CONFIG
  • BiosChipInitCrc : CHIPSET_INIT_INFO
  • BiosGuard : FSP_M_CONFIG
  • BiosGuardAttr : FSP_S_CONFIG
  • BiosGuardModulePtr : FSP_S_CONFIG
  • BiosGuardToolsInterface : FSP_M_CONFIG
  • BiosSize : FSP_M_TEST_CONFIG
  • BiProcHot : FSP_S_TEST_CONFIG
  • BistOnReset : FSP_M_CONFIG
  • BltBufferAddress : FSP_S_CONFIG
  • BltBufferSize : FSP_S_CONFIG
  • BootFrequency : FSP_M_CONFIG
  • BypassPhySyncReset : FSP_M_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
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Here is a list of all documented class members with links to the class documentation for each member:

- c -

  • C1e : FSP_S_TEST_CONFIG
  • C1StateAutoDemotion : FSP_S_TEST_CONFIG
  • C1StateUnDemotion : FSP_S_TEST_CONFIG
  • C3StateAutoDemotion : FSP_S_TEST_CONFIG
  • C3StateUnDemotion : FSP_S_TEST_CONFIG
  • CacheConfiguration : SMBIOS_CACHE_INFO
  • CacheSpeed : SMBIOS_CACHE_INFO
  • CaVrefConfig : FSP_M_CONFIG
  • CdClock : FSP_S_CONFIG
  • CdynmaxClampEnable : FSP_S_TEST_CONFIG
  • ChapDeviceEnable : FSP_S_TEST_CONFIG
  • ChHashEnable : FSP_M_CONFIG
  • ChHashInterleaveBit : FSP_M_CONFIG
  • ChHashMask : FSP_M_CONFIG
  • ChipsetInitBinLen : FSP_S_CONFIG
  • ChipsetInitBinPtr : FSP_S_CONFIG
  • ChipsetInitMessage : FSP_M_TEST_CONFIG
  • CkeRankMapping : FSP_M_CONFIG
  • CleanMemory : FSP_M_CONFIG
  • CMDDSEQ : FSP_M_CONFIG
  • CMDNORM : FSP_M_CONFIG
  • CmdRanksTerminated : FSP_M_CONFIG
  • CMDSR : FSP_M_CONFIG
  • CMDVC : FSP_M_CONFIG
  • CodeRegionBase : FSPT_CORE_UPD
  • CodeRegionSize : FSPT_CORE_UPD
  • ComponentNameIndex : FIRMWARE_VERSION_INFO
  • ConfigTdpBios : FSP_S_TEST_CONFIG
  • ConfigTdpLevel : FSP_S_TEST_CONFIG
  • ConfigTdpLock : FSP_S_TEST_CONFIG
  • CoreCount : SMBIOS_PROCESSOR_INFO
  • CoreMaxOcRatio : FSP_M_CONFIG
  • CorePllVoltageOffset : FSP_M_CONFIG
  • CoreVoltageAdaptive : FSP_M_CONFIG
  • CoreVoltageMode : FSP_M_CONFIG
  • CoreVoltageOffset : FSP_M_CONFIG
  • CoreVoltageOverride : FSP_M_CONFIG
  • Count : FIRMWARE_VERSION_INFO_HOB
  • CpuBistData : FSP_S_CONFIG
  • CpuMpHob : FSP_S_CONFIG
  • CpuMpPpi : FSP_S_CONFIG
  • CpuRatio : FSP_M_CONFIG
  • CpuTraceHubMemReg0Size : FSP_M_CONFIG
  • CpuTraceHubMemReg1Size : FSP_M_CONFIG
  • CpuTraceHubMode : FSP_M_CONFIG
  • CpuWakeUpTimer : FSP_S_TEST_CONFIG
  • CridEnable : FSP_S_CONFIG
  • CstateLatencyControl0Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl1Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl2Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl3Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl4Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl5Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : FSP_S_TEST_CONFIG
  • CStatePreWake : FSP_S_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : FSP_S_TEST_CONFIG
  • CurrentSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • CurrentSramType : SMBIOS_CACHE_INFO
  • Custom1ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom1PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom1TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom2ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom2PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom2TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom3ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom3PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom3TurboActivationRatio : FSP_S_TEST_CONFIG
  • Cx : FSP_S_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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  • Variables
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Here is a list of all documented class members with links to the class documentation for each member:

- d -

  • Data : AUDIO_AZALIA_VERB_TABLE
  • DataDwords : AZALIA_HEADER
  • DciUsb3TypecUfpDbg : FSP_M_CONFIG
  • DcLoadline : FSP_S_CONFIG
  • DdiPortBDdc : FSP_S_CONFIG
  • DdiPortBHpd : FSP_S_CONFIG
  • DdiPortCDdc : FSP_S_CONFIG
  • DdiPortCHpd : FSP_S_CONFIG
  • DdiPortDDdc : FSP_S_CONFIG
  • DdiPortDHpd : FSP_S_CONFIG
  • DdiPortEdp : FSP_S_CONFIG
  • DdiPortFDdc : FSP_S_CONFIG
  • DdiPortFHpd : FSP_S_CONFIG
  • Ddr4DdpSharedClock : FSP_M_CONFIG
  • Ddr4DdpSharedZq : FSP_M_CONFIG
  • Ddr4MixedUDimm2DpcLimit : FSP_M_CONFIG
  • DdrFreqLimit : FSP_M_CONFIG
  • DdrThermalSensor : FSP_M_CONFIG
  • DebugInterfaceEnable : FSP_S_CONFIG , FSP_S_TEST_CONFIG
  • DebugInterfaceLockEnable : FSP_S_TEST_CONFIG
  • DeltaT12PowerCycleDelay : FSP_S_CONFIG
  • Device : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Device4Enable : FSP_S_CONFIG
  • DeviceId : AZALIA_HEADER
  • DevIntConfigPtr : FSP_S_CONFIG
  • DidInitStat : FSP_M_TEST_CONFIG
  • DimmCapacity : DIMM_INFO
  • DIMMODTT : FSP_M_CONFIG
  • DIMMRONT : FSP_M_CONFIG
  • Direction : GPIO_CONFIG
  • DisableCpuReplacedPolling : FSP_M_TEST_CONFIG
  • DisableD0I3SettingForHeci : FSP_S_TEST_CONFIG
  • DisableDimmChannel0 : FSP_M_CONFIG
  • DisableDimmChannel1 : FSP_M_CONFIG
  • DisableHeciRetry : FSP_M_TEST_CONFIG
  • DisableMessageCheck : FSP_M_TEST_CONFIG
  • DisableMtrrProgram : FSP_M_CONFIG
  • DisableProcHotOut : FSP_S_TEST_CONFIG
  • DisableTurboGt : FSP_S_TEST_CONFIG
  • DisableVrThermalAlert : FSP_S_TEST_CONFIG
  • DllBwEn0 : FSP_M_CONFIG
  • DllBwEn1 : FSP_M_CONFIG
  • DllBwEn2 : FSP_M_CONFIG
  • DllBwEn3 : FSP_M_CONFIG
  • DmiAspm : FSP_S_CONFIG
  • DmiDeEmphasis : FSP_M_CONFIG
  • DmiExtSync : FSP_S_TEST_CONFIG
  • DmiGen3EndPointHint : FSP_M_CONFIG
  • DmiGen3EndPointPreset : FSP_M_CONFIG
  • DmiGen3EqPh2Enable : FSP_M_TEST_CONFIG
  • DmiGen3EqPh3Method : FSP_M_TEST_CONFIG
  • DmiGen3ProgramStaticEq : FSP_M_CONFIG
  • DmiGen3RootPortPreset : FSP_M_CONFIG
  • DmiGen3RxCtlePeaking : FSP_M_CONFIG
  • DmiIot : FSP_S_TEST_CONFIG
  • DmiMaxLinkSpeed : FSP_M_TEST_CONFIG
  • DmiSuggestedSetting : FSP_S_CONFIG
  • DmiTS0TW : FSP_S_CONFIG
  • DmiTS1TW : FSP_S_CONFIG
  • DmiTS2TW : FSP_S_CONFIG
  • DmiTS3TW : FSP_S_CONFIG
  • DqByteMapCh0 : FSP_M_CONFIG
  • DqByteMapCh1 : FSP_M_CONFIG
  • DqPinsInterleaved : FSP_M_CONFIG
  • DqsMapCpu2DramCh0 : FSP_M_CONFIG
  • DqsMapCpu2DramCh1 : FSP_M_CONFIG
  • DualDimmPerChannelBoardType : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- e -

  • EcCmdLock : FSP_S_CONFIG
  • EcCmdProvisionEav : FSP_S_CONFIG
  • EccSupport : FSP_M_CONFIG
  • ECT : FSP_M_CONFIG
  • EdramTestMode : FSP_S_TEST_CONFIG
  • EightCoreRatioLimit : FSP_S_TEST_CONFIG
  • Eist : FSP_S_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • Enable8254ClockGating : FSP_S_CONFIG
  • Enable8254ClockGatingOnS3 : FSP_S_CONFIG
  • EnableC6Dram : FSP_M_CONFIG
  • EnableCltm : FSP_M_CONFIG
  • EnabledCoreCount : SMBIOS_PROCESSOR_INFO
  • EnableExtts : FSP_M_CONFIG
  • EnableItbm : FSP_S_TEST_CONFIG
  • EnableItbmDriver : FSP_S_TEST_CONFIG
  • EnableOltm : FSP_M_CONFIG
  • EnablePwrDn : FSP_M_CONFIG
  • EnablePwrDnLpddr : FSP_M_CONFIG
  • EnableSgx : FSP_M_CONFIG
  • EnableTcoTimer : FSP_S_CONFIG
  • EnBER : FSP_M_CONFIG
  • EnCmdRate : FSP_M_CONFIG
  • EndOfPostMessage : FSP_S_TEST_CONFIG
  • EnergyEfficientPState : FSP_S_TEST_CONFIG
  • EnergyEfficientTurbo : FSP_S_TEST_CONFIG
  • EnergyScaleFact : FSP_M_CONFIG
  • EnhancedInterleave : FSP_M_CONFIG
  • EpgEnable : FSP_M_CONFIG
  • ERDMPRTC2D : FSP_M_CONFIG
  • ERDTC2D : FSP_M_CONFIG
  • ErrorCorrectionType : SMBIOS_CACHE_INFO
  • EsataSpeedLimit : FSP_S_CONFIG
  • EWRDSEQ : FSP_M_CONFIG
  • EWRTC2D : FSP_M_CONFIG
  • ExitOnFailure : FSP_M_CONFIG
  • ExternalClockInMHz : SMBIOS_PROCESSOR_INFO


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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  • Variables
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Here is a list of all documented class members with links to the class documentation for each member:

- f -

  • FastPkgCRampDisableFivr : FSP_S_CONFIG
  • FastPkgCRampDisableGt : FSP_S_CONFIG
  • FastPkgCRampDisableIa : FSP_S_CONFIG
  • FastPkgCRampDisableSa : FSP_S_CONFIG
  • FClkFrequency : FSP_M_CONFIG
  • FiveCoreRatioLimit : FSP_S_TEST_CONFIG
  • FivrEfficiency : FSP_M_CONFIG
  • FivrFaults : FSP_M_CONFIG
  • FivrRfiFrequency : FSP_S_CONFIG
  • FivrSpreadSpectrum : FSP_S_CONFIG
  • ForceOltmOrRefresh2x : FSP_M_CONFIG
  • ForcMebxSyncUp : FSP_S_CONFIG
  • FourCoreRatioLimit : FSP_S_TEST_CONFIG
  • FreqSaGvLow : FSP_M_CONFIG
  • FreqSaGvMid : FSP_M_CONFIG
  • FspmArchUpd : FSPM_UPD
  • FspmConfig : FSPM_UPD
  • FspmTestConfig : FSPM_UPD
  • FspsConfig : FSPS_UPD
  • FspsTestConfig : FSPS_UPD
  • FsptConfig : FSPT_UPD
  • FsptCoreUpd : FSPT_UPD
  • FspUpdHeader : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Function : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • FwProgress : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
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Here is a list of all documented class members with links to the class documentation for each member:

- g -

  • GdxcEnable : FSP_M_CONFIG
  • GdxcIotSize : FSP_M_CONFIG
  • GdxcMotSize : FSP_M_CONFIG
  • Gen3SwEqAlwaysAttempt : FSP_M_TEST_CONFIG
  • Gen3SwEqEnableVocTest : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterErrorTarget : FSP_M_TEST_CONFIG
  • Gen3SwEqNumberOfPresets : FSP_M_TEST_CONFIG
  • Gen3SwEqVocDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqVocErrorTarget : FSP_M_TEST_CONFIG
  • GmAdr : FSP_M_CONFIG
  • GnaEnable : FSP_S_CONFIG
  • GpioIrqRoute : FSP_S_CONFIG
  • GraphicsConfigPtr : FSP_S_CONFIG
  • GtExtraTurboVoltage : FSP_M_CONFIG
  • GtFreqMax : FSP_S_TEST_CONFIG
  • GtMaxOcRatio : FSP_M_CONFIG
  • GtPllVoltageOffset : FSP_M_CONFIG
  • GtPsmiSupport : FSP_M_CONFIG
  • GttMmAdr : FSP_M_CONFIG
  • GttSize : FSP_M_CONFIG
  • GtusExtraTurboVoltage : FSP_M_CONFIG
  • GtusMaxOcRatio : FSP_M_CONFIG
  • GtusVoltageMode : FSP_M_CONFIG
  • GtusVoltageOffset : FSP_M_CONFIG
  • GtusVoltageOverride : FSP_M_CONFIG
  • GtVoltageMode : FSP_M_CONFIG
  • GtVoltageOffset : FSP_M_CONFIG
  • GtVoltageOverride : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
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Here is a list of all documented class members with links to the class documentation for each member:

- h -

  • HdcControl : FSP_S_TEST_CONFIG
  • Header : AUDIO_AZALIA_VERB_TABLE , FIRMWARE_VERSION_INFO_HOB
  • Heci1BarAddress : FSP_M_CONFIG
  • Heci2BarAddress : FSP_M_CONFIG
  • Heci3BarAddress : FSP_M_CONFIG
  • Heci3Enabled : FSP_S_CONFIG
  • HeciCommunication2 : FSP_M_TEST_CONFIG
  • HeciTimeouts : FSP_M_CONFIG
  • HobBufferSize : FSP_M_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • HotBudgetCh0Dimm0 : FSP_M_CONFIG
  • HotBudgetCh0Dimm1 : FSP_M_CONFIG
  • HotBudgetCh1Dimm0 : FSP_M_CONFIG
  • HotBudgetCh1Dimm1 : FSP_M_CONFIG
  • HotThresholdCh0Dimm0 : FSP_M_CONFIG
  • HotThresholdCh0Dimm1 : FSP_M_CONFIG
  • HotThresholdCh1Dimm0 : FSP_M_CONFIG
  • HotThresholdCh1Dimm1 : FSP_M_CONFIG
  • Hwp : FSP_S_TEST_CONFIG
  • HwpInterruptControl : FSP_S_TEST_CONFIG
  • HyperThreading : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
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Here is a list of all documented class members with links to the class documentation for each member:

- i -

  • IccMax : FSP_S_CONFIG
  • Idd3n : FSP_M_CONFIG
  • Idd3p : FSP_M_CONFIG
  • IdleEnergyCh0Dimm0 : FSP_M_CONFIG
  • IdleEnergyCh0Dimm1 : FSP_M_CONFIG
  • IdleEnergyCh1Dimm0 : FSP_M_CONFIG
  • IdleEnergyCh1Dimm1 : FSP_M_CONFIG
  • IedSize : FSP_M_CONFIG
  • IgdDvmt50PreAlloc : FSP_M_CONFIG
  • ImonOffset : FSP_S_CONFIG
  • ImonSlope : FSP_S_CONFIG
  • ImonSlope1 : FSP_S_CONFIG
  • ImrRpSelection : FSP_M_CONFIG
  • InitPcieAspmAfterOprom : FSP_M_CONFIG
  • InstalledSize : SMBIOS_CACHE_INFO
  • InstalledSize2 : SMBIOS_CACHE_INFO
  • InternalGfx : FSP_M_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • IntX : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Irq : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • IslVrCmd : FSP_S_CONFIG
  • IsTPMPresence : FSP_M_CONFIG
  • IsvtIoPort : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- j -

  • JtagC10PowerGateDisable : FSP_M_CONFIG
  • JWRL : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- k -

  • KtDeviceEnable : FSP_M_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- l -

  • LCT : FSP_M_CONFIG
  • LockConfig : GPIO_CONFIG
  • LockPTMregs : FSP_M_TEST_CONFIG
  • LogoPtr : FSP_S_CONFIG
  • LogoSize : FSP_S_CONFIG
  • LpDdrDqDqsReTraining : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- m -

  • MachineCheckEnable : FSP_S_TEST_CONFIG
  • ManageabilityMode : FSP_S_CONFIG
  • MaxCacheSize : SMBIOS_CACHE_INFO
  • MaximumCacheSize2 : SMBIOS_CACHE_INFO
  • MaxRatio : FSP_S_TEST_CONFIG
  • MaxRingRatioLimit : FSP_S_TEST_CONFIG
  • McivrRfiFrequencyAdjust : FSP_S_CONFIG
  • McivrRfiFrequencyPrefix : FSP_S_CONFIG
  • McivrSpreadSpectrum : FSP_S_CONFIG
  • McPllVoltageOffset : FSP_M_CONFIG
  • MctpBroadcastCycle : FSP_S_TEST_CONFIG
  • MeChipInitCrc : CHIPSET_INIT_INFO
  • MemorySpdDataLen : FSP_M_CONFIG
  • MemorySpdPtr00 : FSP_M_CONFIG
  • MemorySpdPtr01 : FSP_M_CONFIG
  • MemorySpdPtr10 : FSP_M_CONFIG
  • MemorySpdPtr11 : FSP_M_CONFIG
  • MemoryTrace : FSP_M_CONFIG
  • MemTestOnWarmBoot : FSP_M_CONFIG
  • MEMTST : FSP_M_CONFIG
  • MeUnconfigOnRtcClear : FSP_S_CONFIG
  • MicrocodeRegionBase : FSP_S_CONFIG , FSPT_CORE_UPD
  • MicrocodeRegionSize : FSP_S_CONFIG , FSPT_CORE_UPD
  • MinRingRatioLimit : FSP_S_TEST_CONFIG
  • MlcSpatialPrefetcher : FSP_S_TEST_CONFIG
  • MlcStreamerPrefetcher : FSP_S_TEST_CONFIG
  • MmioSize : FSP_M_CONFIG
  • MmioSizeAdjustment : FSP_M_CONFIG
  • ModulePartNum : DIMM_INFO
  • MonitorMwaitEnable : FSP_S_TEST_CONFIG
  • MrcFastBoot : FSP_M_CONFIG
  • MrcSafeConfig : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- n -

  • NModeSupport : FSP_M_CONFIG
  • NumberOfCacheLevels : SMBIOS_CACHE_INFO
  • NumberOfEntries : FSP_S_TEST_CONFIG
  • NumOfDevIntConfig : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- o -

  • OcLock : FSP_M_CONFIG
  • OcSupport : FSP_M_CONFIG
  • OddRatioMode : FSP_M_CONFIG
  • OneCoreRatioLimit : FSP_S_TEST_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputState : GPIO_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- p -

  • PadMode : GPIO_CONFIG
  • PanelPowerEnable : FSP_M_TEST_CONFIG
  • PavpEnable : FSP_S_CONFIG
  • PcdDebugInterfaceFlags : FSP_M_CONFIG
  • PcdIsaSerialUartBase : FSP_M_CONFIG
  • PcdPciExpressBaseAddress : FSP_T_CONFIG
  • PcdPciExpressRegionLength : FSP_T_CONFIG
  • PcdSerialDebugBaudRate : FSP_M_CONFIG
  • PcdSerialDebugLevel : FSP_M_CONFIG
  • PcdSerialIoUart0PinMuxing : FSP_T_CONFIG
  • PcdSerialIoUartDebugEnable : FSP_T_CONFIG
  • PcdSerialIoUartInputClock : FSP_T_CONFIG
  • PcdSerialIoUartNumber : FSP_M_CONFIG , FSP_T_CONFIG
  • PchCnviMfUart1Type : FSP_S_CONFIG
  • PchCnviMode : FSP_S_CONFIG
  • PchCrid : FSP_S_CONFIG
  • PchDmiAspm : FSP_S_CONFIG
  • PchDmiAspmCtrl : FSP_S_CONFIG
  • PchDmiTsawEn : FSP_S_CONFIG
  • PchEnableComplianceMode : FSP_S_CONFIG
  • PchEnableDbcObs : FSP_S_CONFIG
  • PchEspiBmeMasterSlaveEnabled : FSP_S_CONFIG
  • PchEspiLgmrEnable : FSP_S_CONFIG
  • PchHdaAudioLinkDmic0 : FSP_S_CONFIG
  • PchHdaAudioLinkDmic1 : FSP_S_CONFIG
  • PchHdaAudioLinkHda : FSP_S_CONFIG
  • PchHdaAudioLinkSndw1 : FSP_S_CONFIG
  • PchHdaAudioLinkSndw2 : FSP_S_CONFIG
  • PchHdaAudioLinkSndw3 : FSP_S_CONFIG
  • PchHdaAudioLinkSndw4 : FSP_S_CONFIG
  • PchHdaAudioLinkSsp0 : FSP_S_CONFIG
  • PchHdaAudioLinkSsp1 : FSP_S_CONFIG
  • PchHdaAudioLinkSsp2 : FSP_S_CONFIG
  • PchHdaCodecSxWakeCapability : FSP_S_CONFIG
  • PchHdaDspEnable : FSP_S_CONFIG
  • PchHdaDspUaaCompliance : FSP_S_CONFIG
  • PchHdaEnable : FSP_M_CONFIG
  • PchHdaIDispCodecDisconnect : FSP_S_CONFIG
  • PchHdaIDispLinkFrequency : FSP_S_CONFIG
  • PchHdaIDispLinkTmode : FSP_S_CONFIG
  • PchHdaLinkFrequency : FSP_S_CONFIG
  • PchHdaPme : FSP_S_CONFIG
  • PchHdaResetWaitTimer : FSP_S_TEST_CONFIG
  • PchHdaSndwBufferRcomp : FSP_S_CONFIG
  • PchHdaVcType : FSP_S_CONFIG
  • PchHdaVerbTableEntryNum : FSP_S_CONFIG
  • PchHdaVerbTablePtr : FSP_S_CONFIG
  • PchHotEnable : FSP_S_CONFIG
  • PchIoApicEntry24_119 : FSP_S_CONFIG
  • PchIoApicId : FSP_S_CONFIG
  • PchIshEnable : FSP_M_CONFIG
  • PchIshGp0GpioAssign : FSP_S_CONFIG
  • PchIshGp1GpioAssign : FSP_S_CONFIG
  • PchIshGp2GpioAssign : FSP_S_CONFIG
  • PchIshGp3GpioAssign : FSP_S_CONFIG
  • PchIshGp4GpioAssign : FSP_S_CONFIG
  • PchIshGp5GpioAssign : FSP_S_CONFIG
  • PchIshGp6GpioAssign : FSP_S_CONFIG
  • PchIshGp7GpioAssign : FSP_S_CONFIG
  • PchIshI2c0GpioAssign : FSP_S_CONFIG
  • PchIshI2c1GpioAssign : FSP_S_CONFIG
  • PchIshI2c2GpioAssign : FSP_S_CONFIG
  • PchIshPdtUnlock : FSP_S_CONFIG
  • PchIshSpiGpioAssign : FSP_S_CONFIG
  • PchIshUart0GpioAssign : FSP_S_CONFIG
  • PchIshUart1GpioAssign : FSP_S_CONFIG
  • PchLanEnable : FSP_S_CONFIG
  • PchLanLtrEnable : FSP_S_CONFIG
  • PchLockDownBiosInterface : FSP_S_TEST_CONFIG
  • PchLockDownBiosLock : FSP_S_CONFIG
  • PchLockDownGlobalSmi : FSP_S_TEST_CONFIG
  • PchLockDownRtcMemoryLock : FSP_S_CONFIG
  • PchLpcEnhancePort8xhDecoding : FSP_M_CONFIG
  • PchMemoryC0TransmitEnable : FSP_S_CONFIG
  • PchMemoryPinSelection : FSP_S_CONFIG
  • PchMemoryPmsyncEnable : FSP_S_CONFIG
  • PchMemoryThrottlingEnable : FSP_S_CONFIG
  • PchNumRsvdSmbusAddresses : FSP_M_CONFIG
  • PchPcieDeviceOverrideTablePtr : FSP_S_CONFIG
  • PchPcieHsioRxSetCtle : FSP_M_CONFIG
  • PchPcieHsioRxSetCtleEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchPciePort8xhDecodePortIndex : FSP_S_TEST_CONFIG
  • PchPmDeepSxPol : FSP_S_CONFIG
  • PchPmDisableDsxAcPresentPulldown : FSP_S_CONFIG
  • PchPmDisableEnergyReport : FSP_S_TEST_CONFIG
  • PchPmDisableNativePowerButton : FSP_S_CONFIG
  • PchPmLanWakeFromDeepSx : FSP_S_CONFIG
  • PchPmLpcClockRun : FSP_S_CONFIG
  • PchPmMeWakeSts : FSP_S_CONFIG
  • PchPmPciePllSsc : FSP_S_CONFIG
  • PchPmPcieWakeFromDeepSx : FSP_S_CONFIG
  • PchPmPmeB0S5Dis : FSP_S_CONFIG
  • PchPmPwrBtnOverridePeriod : FSP_S_CONFIG
  • PchPmPwrCycDur : FSP_S_CONFIG
  • PchPmSlpAMinAssert : FSP_S_CONFIG
  • PchPmSlpLanLowDc : FSP_S_CONFIG
  • PchPmSlpS0Enable : FSP_S_CONFIG
  • PchPmSlpS0Vm070VSupport : FSP_S_CONFIG
  • PchPmSlpS0Vm075VSupport : FSP_S_CONFIG
  • PchPmSlpS0VmRuntimeControl : FSP_S_CONFIG
  • PchPmSlpS3MinAssert : FSP_S_CONFIG
  • PchPmSlpS4MinAssert : FSP_S_CONFIG
  • PchPmSlpStrchSusUp : FSP_S_CONFIG
  • PchPmSlpSusMinAssert : FSP_S_CONFIG
  • PchPmVrAlert : FSP_S_CONFIG
  • PchPmWolEnableOverride : FSP_S_CONFIG
  • PchPmWolOvrWkSts : FSP_S_CONFIG
  • PchPmWoWlanDeepSxEnable : FSP_S_CONFIG
  • PchPmWoWlanEnable : FSP_S_CONFIG
  • PchPort80Route : FSP_M_CONFIG
  • PchPostMemRsvd : FSP_S_CONFIG
  • PchPreMemRsvd : FSP_M_CONFIG
  • PchProtectedRangeBase : FSP_S_CONFIG
  • PchProtectedRangeLimit : FSP_S_CONFIG
  • PchPwrOptEnable : FSP_S_CONFIG
  • PchReadProtectionEnable : FSP_S_CONFIG
  • PchSataHsioRxGen1EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen1EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchSbAccessUnlock : FSP_S_TEST_CONFIG
  • PchSbiUnlock : FSP_S_TEST_CONFIG
  • PchScsEmmcHs400DllDataValid : FSP_S_CONFIG
  • PchScsEmmcHs400DriverStrength : FSP_S_CONFIG
  • PchScsEmmcHs400RxStrobeDll1 : FSP_S_CONFIG
  • PchScsEmmcHs400TuningRequired : FSP_S_CONFIG
  • PchScsEmmcHs400TxDataDll : FSP_S_CONFIG
  • PchSerialIoI2cPadsTermination : FSP_S_CONFIG
  • PchSirqEnable : FSP_S_CONFIG
  • PchSirqMode : FSP_S_CONFIG
  • PchSmbAlertEnable : FSP_M_CONFIG
  • PchSmbusIoBase : FSP_M_CONFIG
  • PchStartFramePulse : FSP_S_CONFIG
  • PchT0Level : FSP_S_CONFIG
  • PchT1Level : FSP_S_CONFIG
  • PchT2Level : FSP_S_CONFIG
  • PchTemperatureHotLevel : FSP_S_CONFIG
  • PchTraceHubMemReg0Size : FSP_M_CONFIG
  • PchTraceHubMemReg1Size : FSP_M_CONFIG
  • PchTraceHubMode : FSP_M_CONFIG
  • PchTsmicLock : FSP_S_CONFIG
  • PchTTEnable : FSP_S_CONFIG
  • PchTTLock : FSP_S_CONFIG
  • PchTTState13Enable : FSP_S_CONFIG
  • PchUnlockGpioPads : FSP_S_TEST_CONFIG
  • PchUsb2PhySusPgEnable : FSP_S_CONFIG
  • PchUsbHsioFilterSel : FSP_S_CONFIG
  • PchUsbHsioRxTuningEnable : FSP_S_CONFIG
  • PchUsbHsioRxTuningParameters : FSP_S_CONFIG
  • PchUsbOverCurrentEnable : FSP_S_CONFIG
  • PchWriteProtectionEnable : FSP_S_CONFIG
  • PchXhciOcLock : FSP_S_TEST_CONFIG
  • PcieClkSrcClkReq : FSP_S_CONFIG
  • PcieClkSrcUsage : FSP_S_CONFIG
  • PcieComplianceTestMode : FSP_S_CONFIG
  • PcieDisableRootPortClockGating : FSP_S_CONFIG
  • PcieEnablePeerMemoryWrite : FSP_S_CONFIG
  • PcieEnablePort8xhDecode : FSP_S_TEST_CONFIG
  • PcieEqPh3LaneParamCm : FSP_S_CONFIG
  • PcieEqPh3LaneParamCp : FSP_S_CONFIG
  • PcieImrEnabled : FSP_M_CONFIG
  • PcieImrSize : FSP_M_CONFIG
  • PcieRootPortGen2PllL1CgDisable : FSP_S_CONFIG
  • PcieRpAcsEnabled : FSP_S_CONFIG
  • PcieRpAdvancedErrorReporting : FSP_S_CONFIG
  • PcieRpAspm : FSP_S_CONFIG
  • PcieRpClkReqDetect : FSP_S_CONFIG
  • PcieRpCompletionTimeout : FSP_S_CONFIG
  • PcieRpCorrectableErrorReport : FSP_S_CONFIG
  • PcieRpDetectTimeoutMs : FSP_S_CONFIG
  • PcieRpDpcExtensionsMask : FSP_S_CONFIG
  • PcieRpDpcMask : FSP_S_CONFIG
  • PcieRpDptp : FSP_S_TEST_CONFIG
  • PcieRpEnableCpm : FSP_S_CONFIG
  • PcieRpEnableMask : FSP_M_CONFIG
  • PcieRpExtSync : FSP_S_CONFIG
  • PcieRpFatalErrorReport : FSP_S_CONFIG
  • PcieRpFunctionSwap : FSP_S_CONFIG
  • PcieRpGen3EqPh3Method : FSP_S_CONFIG
  • PcieRpHotPlug : FSP_S_CONFIG
  • PcieRpImrEnabled : FSP_S_CONFIG
  • PcieRpImrSelection : FSP_S_CONFIG
  • PcieRpL1Substates : FSP_S_CONFIG
  • PcieRpLtrConfigLock : FSP_S_CONFIG
  • PcieRpLtrEnable : FSP_S_CONFIG
  • PcieRpLtrMaxNoSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpLtrMaxSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpMaxPayload : FSP_S_CONFIG
  • PcieRpNoFatalErrorReport : FSP_S_CONFIG
  • PcieRpNonSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpPcieSpeed : FSP_S_CONFIG
  • PcieRpPhysicalSlotNumber : FSP_S_CONFIG
  • PcieRpPmSci : FSP_S_CONFIG
  • PcieRpPtmMask : FSP_S_CONFIG
  • PcieRpSlotImplemented : FSP_S_CONFIG
  • PcieRpSlotPowerLimitScale : FSP_S_TEST_CONFIG
  • PcieRpSlotPowerLimitValue : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpSystemErrorOnCorrectableError : FSP_S_CONFIG
  • PcieRpSystemErrorOnFatalError : FSP_S_CONFIG
  • PcieRpSystemErrorOnNonFatalError : FSP_S_CONFIG
  • PcieRpTransmitterHalfSwing : FSP_S_CONFIG
  • PcieRpUnsupportedRequestReport : FSP_S_CONFIG
  • PcieRpUptp : FSP_S_TEST_CONFIG
  • PcieSwEqCoeffListCm : FSP_S_CONFIG
  • PcieSwEqCoeffListCp : FSP_S_CONFIG
  • PdEnergyCh0Dimm0 : FSP_M_CONFIG
  • PdEnergyCh0Dimm1 : FSP_M_CONFIG
  • PdEnergyCh1Dimm0 : FSP_M_CONFIG
  • PdEnergyCh1Dimm1 : FSP_M_CONFIG
  • PeciC10Reset : FSP_M_CONFIG
  • PeciSxReset : FSP_M_CONFIG
  • Peg0Enable : FSP_M_CONFIG
  • Peg0Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg0Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg0MaxLinkSpeed : FSP_M_CONFIG
  • Peg0MaxLinkWidth : FSP_M_CONFIG
  • Peg0PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg1Enable : FSP_M_CONFIG
  • Peg1Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg1Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg1MaxLinkSpeed : FSP_M_CONFIG
  • Peg1MaxLinkWidth : FSP_M_CONFIG
  • Peg1PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg2Enable : FSP_M_CONFIG
  • Peg2Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg2Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg2MaxLinkSpeed : FSP_M_CONFIG
  • Peg2MaxLinkWidth : FSP_M_CONFIG
  • Peg2PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg3Enable : FSP_M_CONFIG
  • Peg3Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg3Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg3MaxLinkSpeed : FSP_M_CONFIG
  • Peg3MaxLinkWidth : FSP_M_CONFIG
  • Peg3PowerDownUnusedLanes : FSP_M_CONFIG
  • PegDataPtr : FSP_M_CONFIG
  • PegDeEmphasis : FSP_S_CONFIG
  • PegDisableSpreadSpectrumClocking : FSP_M_CONFIG
  • PegGen3EndPointHint : FSP_M_TEST_CONFIG
  • PegGen3EndPointPreset : FSP_M_TEST_CONFIG
  • PegGen3ProgramStaticEq : FSP_M_TEST_CONFIG
  • PegGen3RootPortPreset : FSP_M_TEST_CONFIG
  • PegGen3Rsvd : FSP_M_TEST_CONFIG
  • PegGen3RxCtleOverride : FSP_M_TEST_CONFIG
  • PegGen3RxCtlePeaking : FSP_M_CONFIG
  • PegGenerateBdatMarginTable : FSP_M_TEST_CONFIG
  • PegGpioData : FSP_M_CONFIG
  • PegMaxPayload : FSP_S_TEST_CONFIG
  • PegPhysicalSlotNumber : FSP_S_CONFIG
  • PegRootPortHPE : FSP_M_CONFIG
  • PegRxCemLoopbackLane : FSP_M_TEST_CONFIG
  • PegRxCemNonProtocolAwareness : FSP_M_TEST_CONFIG
  • PegRxCemTestingMode : FSP_M_TEST_CONFIG
  • PegSlotPowerLimitScale : FSP_S_CONFIG
  • PegSlotPowerLimitValue : FSP_S_CONFIG
  • PeiGraphicsPeimInit : FSP_S_CONFIG
  • PkgCStateDemotion : FSP_S_TEST_CONFIG
  • PkgCStateLimit : FSP_S_TEST_CONFIG
  • PkgCStateUnDemotion : FSP_S_TEST_CONFIG
  • PlatformDebugConsent : FSP_M_CONFIG
  • PlatformMemorySize : FSP_M_CONFIG
  • PmcCpuC10GatePinEnable : FSP_S_CONFIG
  • PmcDbgMsgEn : FSP_S_CONFIG
  • PmcModPhySusPgEnable : FSP_S_CONFIG
  • PmcPowerButtonDebounce : FSP_S_CONFIG
  • PmgCstCfgCtrlLock : FSP_S_TEST_CONFIG
  • PmSupport : FSP_S_TEST_CONFIG
  • PortUsb20Enable : FSP_S_CONFIG
  • PortUsb30Enable : FSP_S_CONFIG
  • PostCodeOutputPort : FSP_M_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerLimit1 : FSP_S_TEST_CONFIG
  • PowerLimit1Time : FSP_S_TEST_CONFIG
  • PowerLimit2 : FSP_S_TEST_CONFIG
  • PowerLimit2Power : FSP_S_TEST_CONFIG
  • PowerLimit3 : FSP_S_TEST_CONFIG
  • PowerLimit3DutyCycle : FSP_S_TEST_CONFIG
  • PowerLimit3Lock : FSP_S_TEST_CONFIG
  • PowerLimit3Time : FSP_S_TEST_CONFIG
  • PowerLimit4 : FSP_S_TEST_CONFIG
  • PowerLimit4Lock : FSP_S_TEST_CONFIG
  • PpmIrmSetting : FSP_S_TEST_CONFIG
  • PreWake : FSP_S_CONFIG
  • PrimaryDisplay : FSP_M_CONFIG
  • PrmrrSize : FSP_M_CONFIG
  • ProbelessTrace : FSP_M_CONFIG
  • ProcessorCharacteristics : SMBIOS_PROCESSOR_INFO
  • ProcessorFamily : SMBIOS_PROCESSOR_INFO
  • ProcessorId : SMBIOS_PROCESSOR_INFO
  • ProcessorManufacturerStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcessorTraceEnable : FSP_S_TEST_CONFIG
  • ProcessorTraceMemBase : FSP_S_TEST_CONFIG
  • ProcessorTraceMemLength : FSP_S_TEST_CONFIG
  • ProcessorTraceOutputScheme : FSP_S_TEST_CONFIG
  • ProcessorType : SMBIOS_PROCESSOR_INFO
  • ProcessorUpgrade : SMBIOS_PROCESSOR_INFO
  • ProcessorVersionStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcHotLock : FSP_S_TEST_CONFIG
  • ProcHotResponse : FSP_S_TEST_CONFIG
  • Psi1Threshold : FSP_S_CONFIG
  • Psi2Threshold : FSP_S_CONFIG
  • Psi3Enable : FSP_S_CONFIG
  • Psi3Threshold : FSP_S_CONFIG
  • Psi4Enable : FSP_S_CONFIG
  • PsmiRegionSize : FSP_M_CONFIG
  • PsOnEnable : FSP_S_CONFIG
  • PsysOffset : FSP_S_CONFIG
  • PsysPmax : FSP_S_TEST_CONFIG
  • PsysPowerLimit1 : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Power : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Time : FSP_S_TEST_CONFIG
  • PsysPowerLimit2 : FSP_S_TEST_CONFIG
  • PsysPowerLimit2Power : FSP_S_TEST_CONFIG
  • PsysSlope : FSP_S_CONFIG
  • PwdwnIdleCounter : FSP_M_CONFIG
  • PxRcConfig : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
  • b
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  • d
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  • x
Here is a list of all documented class members with links to the class documentation for each member:

- r -

  • RaceToHalt : FSP_S_TEST_CONFIG
  • RampDown : FSP_S_CONFIG
  • RampUp : FSP_S_CONFIG
  • RankInDimm : DIMM_INFO
  • RankInterleave : FSP_M_CONFIG
  • RaplLim1Ena : FSP_M_CONFIG
  • RaplLim1Pwr : FSP_M_CONFIG
  • RaplLim1WindX : FSP_M_CONFIG
  • RaplLim1WindY : FSP_M_CONFIG
  • RaplLim2Ena : FSP_M_CONFIG
  • RaplLim2Lock : FSP_M_CONFIG
  • RaplLim2Pwr : FSP_M_CONFIG
  • RaplLim2WindX : FSP_M_CONFIG
  • RaplLim2WindY : FSP_M_CONFIG
  • RaplPwrFlCh0 : FSP_M_CONFIG
  • RaplPwrFlCh1 : FSP_M_CONFIG
  • Ratio : FSP_M_CONFIG
  • RcompResistor : FSP_M_CONFIG
  • RcompTarget : FSP_M_CONFIG
  • RCVENC1D : FSP_M_CONFIG
  • RCVET : FSP_M_CONFIG
  • RDAPT : FSP_M_CONFIG
  • RdEnergyCh0Dimm0 : FSP_M_CONFIG
  • RdEnergyCh0Dimm1 : FSP_M_CONFIG
  • RdEnergyCh1Dimm0 : FSP_M_CONFIG
  • RdEnergyCh1Dimm1 : FSP_M_CONFIG
  • RDEQT : FSP_M_CONFIG
  • RDMPRT : FSP_M_CONFIG
  • RDODTT : FSP_M_CONFIG
  • RDTC1D : FSP_M_CONFIG
  • RDTC2D : FSP_M_CONFIG
  • RDVC2D : FSP_M_CONFIG
  • RealtimeMemoryTiming : FSP_M_CONFIG
  • RefClk : FSP_M_CONFIG
  • Refresh2X : FSP_M_CONFIG
  • RemapEnable : FSP_M_CONFIG
  • RemoteAssistance : FSP_S_CONFIG
  • RenderStandby : FSP_S_TEST_CONFIG
  • Reserved : AZALIA_HEADER , FSPT_CORE_UPD
  • Reserved2 : FSP_S_CONFIG
  • ReservedCpuPostMemProduction : FSP_S_CONFIG
  • ReservedCpuPostMemTest : FSP_S_TEST_CONFIG
  • ReservedForFuture1 : FSP_S_CONFIG
  • ReservedFspmTestUpd : FSP_M_TEST_CONFIG
  • ReservedFspmUpd : FSP_M_CONFIG
  • ReservedFspmUpdCfl : FSP_M_CONFIG
  • ReservedFspsTestUpd : FSP_S_TEST_CONFIG
  • ReservedFspsUpd : FSP_S_CONFIG
  • ReservedFsptUpd1 : FSP_T_CONFIG
  • ReservedPchPreMem : FSP_M_CONFIG
  • ReservedSecurityPreMem : FSP_M_CONFIG
  • Revision : CHIPSET_INIT_INFO
  • RevisionId : AZALIA_HEADER
  • RhActProbability : FSP_M_CONFIG
  • RhPrevention : FSP_M_CONFIG
  • RhSolution : FSP_M_CONFIG
  • RingDownBin : FSP_M_CONFIG
  • RingMaxOcRatio : FSP_M_CONFIG
  • RingPllVoltageOffset : FSP_M_CONFIG
  • RingVoltageAdaptive : FSP_M_CONFIG
  • RingVoltageMode : FSP_M_CONFIG
  • RingVoltageOffset : FSP_M_CONFIG
  • RingVoltageOverride : FSP_M_CONFIG
  • RMC : FSP_M_CONFIG
  • RMT : FSP_M_CONFIG
  • RMTLoopCount : FSP_M_CONFIG
  • RmtPerTask : FSP_M_CONFIG
  • RootPortIndex : FSP_M_CONFIG
  • Rsvd : CHIPSET_INIT_INFO
  • RsvdBits : GPIO_CONFIG
  • RsvdSmbusAddressTablePtr : FSP_M_CONFIG
  • RTL : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- s -

  • SafeMode : FSP_M_CONFIG
  • SaGv : FSP_M_CONFIG
  • SaIpuEnable : FSP_M_CONFIG
  • SaIpuImrConfiguration : FSP_M_CONFIG
  • SaOcSupport : FSP_M_CONFIG
  • SaPllVoltageOffset : FSP_M_CONFIG
  • SaPostMemProductionRsvd : FSP_S_CONFIG
  • SaPostMemTestRsvd : FSP_S_TEST_CONFIG
  • SaPreMemProductionRsvd : FSP_M_CONFIG
  • SaPreMemTestRsvd : FSP_M_TEST_CONFIG
  • SaRtd3Pcie0Gpio : FSP_M_CONFIG
  • SaRtd3Pcie1Gpio : FSP_M_CONFIG
  • SaRtd3Pcie2Gpio : FSP_M_CONFIG
  • SaRtd3Pcie3Gpio : FSP_M_CONFIG
  • SataEnable : FSP_S_CONFIG
  • SataLedEnable : FSP_S_CONFIG
  • SataMode : FSP_S_CONFIG
  • SataP0T1M : FSP_S_CONFIG
  • SataP0T2M : FSP_S_CONFIG
  • SataP0T3M : FSP_S_CONFIG
  • SataP0TDisp : FSP_S_CONFIG
  • SataP0TDispFinit : FSP_S_CONFIG
  • SataP0Tinact : FSP_S_CONFIG
  • SataP1T1M : FSP_S_CONFIG
  • SataP1T2M : FSP_S_CONFIG
  • SataP1T3M : FSP_S_CONFIG
  • SataP1TDisp : FSP_S_CONFIG
  • SataP1TDispFinit : FSP_S_CONFIG
  • SataP1Tinact : FSP_S_CONFIG
  • SataPortsDevSlp : FSP_S_CONFIG
  • SataPortsDitoVal : FSP_S_CONFIG
  • SataPortsDmVal : FSP_S_CONFIG
  • SataPortsEnable : FSP_S_CONFIG
  • SataPortsEnableDitoConfig : FSP_S_CONFIG
  • SataPortsExternal : FSP_S_CONFIG
  • SataPortsHotPlug : FSP_S_CONFIG
  • SataPortsInterlockSw : FSP_S_CONFIG
  • SataPortsSolidStateDrive : FSP_S_CONFIG
  • SataPortsSpinUp : FSP_S_CONFIG
  • SataPortsZpOdd : FSP_S_CONFIG
  • SataPwrOptEnable : FSP_S_CONFIG
  • SataRstCpuAttachedStorage : FSP_S_CONFIG
  • SataRstHddUnlock : FSP_S_CONFIG
  • SataRstInterrupt : FSP_S_CONFIG
  • SataRstIrrt : FSP_S_CONFIG
  • SataRstIrrtOnly : FSP_S_CONFIG
  • SataRstLedLocate : FSP_S_CONFIG
  • SataRstLegacyOrom : FSP_S_CONFIG
  • SataRstOptaneMemory : FSP_S_CONFIG
  • SataRstOromUiBanner : FSP_S_CONFIG
  • SataRstOromUiDelay : FSP_S_CONFIG
  • SataRstPcieDeviceResetDelay : FSP_S_CONFIG
  • SataRstPcieEnable : FSP_S_CONFIG
  • SataRstPcieStoragePort : FSP_S_CONFIG
  • SataRstRaid0 : FSP_S_CONFIG
  • SataRstRaid1 : FSP_S_CONFIG
  • SataRstRaid10 : FSP_S_CONFIG
  • SataRstRaid5 : FSP_S_CONFIG
  • SataRstRaidDeviceId : FSP_S_CONFIG
  • SataRstSmartStorage : FSP_S_CONFIG
  • SataSalpSupport : FSP_S_CONFIG
  • SataSpeedLimit : FSP_S_CONFIG
  • SataTestMode : FSP_S_TEST_CONFIG
  • SataThermalSuggestedSetting : FSP_S_CONFIG
  • SaVoltageOffset : FSP_M_CONFIG
  • ScanExtGfxForLegacyOpRom : FSP_M_TEST_CONFIG
  • SciIrqSelect : FSP_S_CONFIG
  • ScramblerSupport : FSP_M_CONFIG
  • ScsEmmcEnabled : FSP_S_CONFIG
  • ScsEmmcHs400Enabled : FSP_S_CONFIG
  • ScsSdCardEnabled : FSP_S_CONFIG
  • ScsUfsEnabled : FSP_S_CONFIG
  • SdCardPowerEnableActiveHigh : FSP_S_CONFIG
  • SdiNum : AZALIA_HEADER
  • SecurityTestRsvd : FSP_M_TEST_CONFIG
  • SendDidMsg : FSP_M_TEST_CONFIG
  • SendEcCmd : FSP_S_CONFIG
  • SendVrMbxCmd : FSP_S_CONFIG
  • SerialIoDebugUartNumber : FSP_S_CONFIG
  • SerialIoDevMode : FSP_S_CONFIG
  • SerialIoEnableDebugUartAfterPost : FSP_S_CONFIG
  • SerialIoSpiCsPolarity : FSP_S_CONFIG
  • SerialIoUart0PinMuxing : FSP_S_CONFIG
  • SerialIoUartHwFlowCtrl : FSP_S_CONFIG
  • SevenCoreRatioLimit : FSP_S_TEST_CONFIG
  • SgDelayAfterHoldReset : FSP_M_CONFIG
  • SgDelayAfterPwrEn : FSP_M_CONFIG
  • SgxEpoch0 : FSP_S_CONFIG
  • SgxEpoch1 : FSP_S_CONFIG
  • SgxSinitDataFromTpm : FSP_S_TEST_CONFIG
  • SgxSinitNvsData : FSP_S_CONFIG
  • ShowSpiController : FSP_S_CONFIG
  • SiCsmFlag : FSP_S_CONFIG
  • Signature : FSP_M_TEST_CONFIG , FSP_S_TEST_CONFIG
  • SinitMemorySize : FSP_M_CONFIG
  • SiNumberOfSsidTableEntry : FSP_S_CONFIG
  • SiSsidTablePtr : FSP_S_CONFIG
  • SixCoreRatioLimit : FSP_S_TEST_CONFIG
  • SkipExtGfxScan : FSP_M_TEST_CONFIG
  • SkipMbpHob : FSP_M_TEST_CONFIG
  • SkipMpInit : FSP_M_CONFIG , FSP_S_CONFIG
  • SkipPamLock : FSP_S_TEST_CONFIG
  • SkipPostBootSai : FSP_S_TEST_CONFIG
  • SkipS3CdClockInit : FSP_S_CONFIG
  • SkipStopPbet : FSP_M_CONFIG
  • SlowSlewRateForFivr : FSP_S_CONFIG
  • SlowSlewRateForGt : FSP_S_CONFIG
  • SlowSlewRateForIa : FSP_S_CONFIG
  • SlowSlewRateForSa : FSP_S_CONFIG
  • SlpS0DisQForDebug : FSP_S_CONFIG
  • SlpS0Override : FSP_S_CONFIG
  • SlpS0WithGbeSupport : FSP_S_CONFIG
  • SmbiosData : FIRMWARE_VERSION_INFO_HOB
  • SmbusArpEnable : FSP_M_CONFIG
  • SmbusDynamicPowerGating : FSP_M_TEST_CONFIG
  • SmbusEnable : FSP_M_CONFIG
  • SmbusSpdWriteDisable : FSP_M_TEST_CONFIG
  • SmramMask : FSP_M_CONFIG
  • SocketDesignationStrIndex : SMBIOS_CACHE_INFO
  • SOT : FSP_M_CONFIG
  • SpdAddressTable : FSP_M_CONFIG
  • SpdDramDeviceType : DIMM_INFO
  • SpdModuleMemoryBusWidth : DIMM_INFO
  • SpdModuleType : DIMM_INFO
  • SpdProfileSelected : FSP_M_CONFIG
  • SpdSave : DIMM_INFO
  • Speed : DIMM_INFO
  • SrefCfgEna : FSP_M_CONFIG
  • StateRatio : FSP_S_TEST_CONFIG
  • StateRatioMax16 : FSP_S_TEST_CONFIG
  • Status : DIMM_INFO , SMBIOS_PROCESSOR_INFO
  • SupportedSramType : SMBIOS_CACHE_INFO
  • SystemCacheType : SMBIOS_CACHE_INFO


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
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Here is a list of all documented class members with links to the class documentation for each member:

- t -

  • TAT : FSP_M_CONFIG
  • TccActivationOffset : FSP_S_TEST_CONFIG
  • TccOffsetClamp : FSP_S_TEST_CONFIG
  • TccOffsetLock : FSP_S_TEST_CONFIG
  • TccOffsetTimeWindowForRatl : FSP_S_TEST_CONFIG
  • tCL : FSP_M_CONFIG
  • TcoIrqEnable : FSP_S_CONFIG
  • TcoIrqSelect : FSP_S_CONFIG
  • tCWL : FSP_M_CONFIG
  • TdcEnable : FSP_S_CONFIG
  • TdcLock : FSP_S_CONFIG
  • TdcPowerLimit : FSP_S_CONFIG
  • TdcTimeWindow : FSP_S_CONFIG
  • TetonGlacierCR : FSP_S_CONFIG
  • TetonGlacierSupport : FSP_S_CONFIG
  • tFAW : FSP_M_CONFIG
  • TgaSize : FSP_M_CONFIG
  • ThermalMonitor : FSP_S_TEST_CONFIG
  • ThreadCount : SMBIOS_PROCESSOR_INFO
  • ThreeCoreRatioLimit : FSP_S_TEST_CONFIG
  • ThreeStrikeCounterDisable : FSP_S_TEST_CONFIG
  • ThrtCkeMinDefeat : FSP_M_CONFIG
  • ThrtCkeMinDefeatLpddr : FSP_M_CONFIG
  • ThrtCkeMinTmr : FSP_M_CONFIG
  • ThrtCkeMinTmrLpddr : FSP_M_CONFIG
  • TimedMwait : FSP_S_TEST_CONFIG
  • TjMaxOffset : FSP_M_CONFIG
  • TotalFlashSize : FSP_M_TEST_CONFIG
  • TraceHubMemBase : FSP_S_CONFIG
  • TrainTrace : FSP_M_CONFIG
  • tRAS : FSP_M_CONFIG
  • tRCDtRP : FSP_M_CONFIG
  • tRd2RdDD : FSP_M_TEST_CONFIG
  • tRd2RdDG : FSP_M_TEST_CONFIG
  • tRd2RdDR : FSP_M_TEST_CONFIG
  • tRd2RdSG : FSP_M_TEST_CONFIG
  • tRd2WrDD : FSP_M_TEST_CONFIG
  • tRd2WrDG : FSP_M_TEST_CONFIG
  • tRd2WrDR : FSP_M_TEST_CONFIG
  • tRd2WrSG : FSP_M_TEST_CONFIG
  • tREFI : FSP_M_CONFIG
  • tRFC : FSP_M_CONFIG
  • tRRD : FSP_M_CONFIG
  • tRRD_L : FSP_M_TEST_CONFIG
  • tRRD_S : FSP_M_TEST_CONFIG
  • tRTP : FSP_M_CONFIG
  • TsegSize : FSP_M_CONFIG
  • TsodAlarmwindowLockBit : FSP_M_CONFIG
  • TsodCriticalEventOnly : FSP_M_CONFIG
  • TsodCriticaltripLockBit : FSP_M_CONFIG
  • TsodEventMode : FSP_M_CONFIG
  • TsodEventOutputControl : FSP_M_CONFIG
  • TsodEventPolarity : FSP_M_CONFIG
  • TsodManualEnable : FSP_M_CONFIG
  • TsodShutdownMode : FSP_M_CONFIG
  • TsodTcritMax : FSP_M_CONFIG
  • TsodThigMax : FSP_M_CONFIG
  • TStates : FSP_S_TEST_CONFIG
  • TTCrossThrottling : FSP_S_CONFIG
  • TTSuggestedSetting : FSP_S_CONFIG
  • TurboMode : FSP_S_CONFIG
  • TurboPowerLimitLock : FSP_S_TEST_CONFIG
  • TvbRatioClipping : FSP_M_CONFIG
  • TvbVoltageOptimization : FSP_M_CONFIG
  • TwoCoreRatioLimit : FSP_S_TEST_CONFIG
  • tWR : FSP_M_CONFIG
  • tWr2RdDD : FSP_M_TEST_CONFIG
  • tWr2RdDG : FSP_M_TEST_CONFIG
  • tWr2RdDR : FSP_M_TEST_CONFIG
  • tWr2RdSG : FSP_M_TEST_CONFIG
  • tWr2WrDD : FSP_M_TEST_CONFIG
  • tWr2WrDG : FSP_M_TEST_CONFIG
  • tWr2WrDR : FSP_M_TEST_CONFIG
  • tWr2WrSG : FSP_M_TEST_CONFIG
  • tWTR : FSP_M_CONFIG
  • tWTR_L : FSP_M_TEST_CONFIG
  • tWTR_S : FSP_M_TEST_CONFIG
  • Txt : FSP_M_CONFIG
  • TxtAcheckRequest : FSP_M_TEST_CONFIG
  • TxtDprMemoryBase : FSP_M_CONFIG
  • TxtDprMemorySize : FSP_M_CONFIG
  • TxtEnable : FSP_S_CONFIG
  • TxtHeapMemorySize : FSP_M_CONFIG
  • TxtImplemented : FSP_M_CONFIG
  • TxtLcpPdBase : FSP_M_CONFIG
  • TxtLcpPdSize : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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  • Variables
  • a
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Here is a list of all documented class members with links to the class documentation for each member:

- u -

  • UnusedUpdSpace0 : FSP_M_CONFIG , FSP_S_CONFIG , FSP_T_CONFIG
  • UnusedUpdSpace1 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace10 : FSP_S_CONFIG
  • UnusedUpdSpace11 : FSP_S_CONFIG
  • UnusedUpdSpace12 : FSP_S_CONFIG
  • UnusedUpdSpace13 : FSP_S_CONFIG
  • UnusedUpdSpace14 : FSP_S_CONFIG
  • UnusedUpdSpace15 : FSP_S_CONFIG
  • UnusedUpdSpace16 : FSP_S_CONFIG
  • UnusedUpdSpace17 : FSP_S_CONFIG
  • UnusedUpdSpace18 : FSP_S_CONFIG
  • UnusedUpdSpace19 : FSP_S_CONFIG
  • UnusedUpdSpace2 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace20 : FSP_S_CONFIG
  • UnusedUpdSpace21 : FSP_S_CONFIG
  • UnusedUpdSpace22 : FSP_S_CONFIG
  • UnusedUpdSpace23 : FSP_S_CONFIG
  • UnusedUpdSpace24 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace3 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace4 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace5 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace6 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace7 : FSP_S_CONFIG , FSPM_UPD
  • UnusedUpdSpace8 : FSP_M_TEST_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace9 : FSP_S_CONFIG
  • UpdTerminator : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Usb2AfePehalfbit : FSP_S_CONFIG
  • Usb2AfePetxiset : FSP_S_CONFIG
  • Usb2AfePredeemp : FSP_S_CONFIG
  • Usb2AfeTxiset : FSP_S_CONFIG
  • Usb2OverCurrentPin : FSP_S_CONFIG
  • Usb3HsioTxDeEmph : FSP_S_CONFIG
  • Usb3HsioTxDeEmphEnable : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmp : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmpEnable : FSP_S_CONFIG
  • Usb3OverCurrentPin : FSP_S_CONFIG
  • UsbPdoProgramming : FSP_S_CONFIG
  • UserBd : FSP_M_CONFIG
  • UserBudgetEnable : FSP_M_CONFIG
  • UserPowerWeightsEn : FSP_M_CONFIG
  • UserThresholdEnable : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
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Here is a list of all documented class members with links to the class documentation for each member:

- v -

  • VddVoltage : FSP_M_CONFIG
  • VendorId : AZALIA_HEADER
  • Version : FIRMWARE_VERSION_INFO
  • VersionStringIndex : FIRMWARE_VERSION_INFO
  • VmxEnable : FSP_M_CONFIG
  • Voltage : SMBIOS_PROCESSOR_INFO
  • VoltageOptimization : FSP_S_TEST_CONFIG
  • VrConfigEnable : FSP_S_CONFIG
  • VrPowerDeliveryDesign : FSP_S_CONFIG
  • VrVoltageLimit : FSP_S_CONFIG
  • VtdBaseAddress : FSP_S_CONFIG
  • VtdDisable : FSP_S_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

  • All
  • Variables
  • a
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  • x
Here is a list of all documented class members with links to the class documentation for each member:

- w -

  • WarmBudgetCh0Dimm0 : FSP_M_CONFIG
  • WarmBudgetCh0Dimm1 : FSP_M_CONFIG
  • WarmBudgetCh1Dimm0 : FSP_M_CONFIG
  • WarmBudgetCh1Dimm1 : FSP_M_CONFIG
  • WarmThresholdCh0Dimm0 : FSP_M_CONFIG
  • WarmThresholdCh0Dimm1 : FSP_M_CONFIG
  • WarmThresholdCh1Dimm0 : FSP_M_CONFIG
  • WarmThresholdCh1Dimm1 : FSP_M_CONFIG
  • WatchDog : FSP_S_CONFIG
  • WatchDogTimerBios : FSP_S_CONFIG
  • WatchDogTimerOs : FSP_S_CONFIG
  • WdtDisableAndLock : FSP_M_TEST_CONFIG
  • WRDSEQT : FSP_M_CONFIG
  • WRDSUDT : FSP_M_CONFIG
  • WrEnergyCh0Dimm0 : FSP_M_CONFIG
  • WrEnergyCh0Dimm1 : FSP_M_CONFIG
  • WrEnergyCh1Dimm0 : FSP_M_CONFIG
  • WrEnergyCh1Dimm1 : FSP_M_CONFIG
  • WRSRT : FSP_M_CONFIG
  • WRTC1D : FSP_M_CONFIG
  • WRTC2D : FSP_M_CONFIG
  • WRVC1D : FSP_M_CONFIG
  • WRVC2D : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- x -

  • X2ApicOptOut : FSP_S_CONFIG
  • XdciEnable : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- a -

  • AcLoadline : FSP_S_CONFIG
  • AcousticNoiseMitigation : FSP_S_CONFIG
  • ActEnergyCh0Dimm0 : FSP_M_CONFIG
  • ActEnergyCh0Dimm1 : FSP_M_CONFIG
  • ActEnergyCh1Dimm0 : FSP_M_CONFIG
  • ActEnergyCh1Dimm1 : FSP_M_CONFIG
  • ActiveCoreCount : FSP_M_CONFIG
  • AesEnable : FSP_S_CONFIG
  • ALIASCHK : FSP_M_CONFIG
  • AmtEnabled : FSP_S_CONFIG
  • AmtKvmEnabled : FSP_S_CONFIG
  • AmtSolEnabled : FSP_S_CONFIG
  • ApertureSize : FSP_M_CONFIG
  • ApIdleManner : FSP_S_TEST_CONFIG
  • ApStartupBase : FSP_M_CONFIG
  • AsfEnabled : FSP_S_CONFIG
  • Associativity : SMBIOS_CACHE_INFO
  • AutoThermalReporting : FSP_S_TEST_CONFIG
  • Avx2RatioOffset : FSP_M_CONFIG
  • Avx3RatioOffset : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- b -

  • BclkAdaptiveVoltage : FSP_M_CONFIG
  • BClkFrequency : FSP_M_CONFIG
  • BdatEnable : FSP_M_TEST_CONFIG
  • BdatTestType : FSP_M_TEST_CONFIG
  • BgpdtHash : FSP_S_CONFIG
  • BiosAcmBase : FSP_M_CONFIG
  • BiosAcmSize : FSP_M_CONFIG
  • BiosChipInitCrc : CHIPSET_INIT_INFO
  • BiosGuard : FSP_M_CONFIG
  • BiosGuardAttr : FSP_S_CONFIG
  • BiosGuardModulePtr : FSP_S_CONFIG
  • BiosGuardToolsInterface : FSP_M_CONFIG
  • BiosSize : FSP_M_TEST_CONFIG
  • BiProcHot : FSP_S_TEST_CONFIG
  • BistOnReset : FSP_M_CONFIG
  • BltBufferAddress : FSP_S_CONFIG
  • BltBufferSize : FSP_S_CONFIG
  • BootFrequency : FSP_M_CONFIG
  • BypassPhySyncReset : FSP_M_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- c -

  • C1e : FSP_S_TEST_CONFIG
  • C1StateAutoDemotion : FSP_S_TEST_CONFIG
  • C1StateUnDemotion : FSP_S_TEST_CONFIG
  • C3StateAutoDemotion : FSP_S_TEST_CONFIG
  • C3StateUnDemotion : FSP_S_TEST_CONFIG
  • CacheConfiguration : SMBIOS_CACHE_INFO
  • CacheSpeed : SMBIOS_CACHE_INFO
  • CaVrefConfig : FSP_M_CONFIG
  • CdClock : FSP_S_CONFIG
  • CdynmaxClampEnable : FSP_S_TEST_CONFIG
  • ChapDeviceEnable : FSP_S_TEST_CONFIG
  • ChHashEnable : FSP_M_CONFIG
  • ChHashInterleaveBit : FSP_M_CONFIG
  • ChHashMask : FSP_M_CONFIG
  • ChipsetInitBinLen : FSP_S_CONFIG
  • ChipsetInitBinPtr : FSP_S_CONFIG
  • ChipsetInitMessage : FSP_M_TEST_CONFIG
  • CkeRankMapping : FSP_M_CONFIG
  • CleanMemory : FSP_M_CONFIG
  • CMDDSEQ : FSP_M_CONFIG
  • CMDNORM : FSP_M_CONFIG
  • CmdRanksTerminated : FSP_M_CONFIG
  • CMDSR : FSP_M_CONFIG
  • CMDVC : FSP_M_CONFIG
  • CodeRegionBase : FSPT_CORE_UPD
  • CodeRegionSize : FSPT_CORE_UPD
  • ComponentNameIndex : FIRMWARE_VERSION_INFO
  • ConfigTdpBios : FSP_S_TEST_CONFIG
  • ConfigTdpLevel : FSP_S_TEST_CONFIG
  • ConfigTdpLock : FSP_S_TEST_CONFIG
  • CoreCount : SMBIOS_PROCESSOR_INFO
  • CoreMaxOcRatio : FSP_M_CONFIG
  • CorePllVoltageOffset : FSP_M_CONFIG
  • CoreVoltageAdaptive : FSP_M_CONFIG
  • CoreVoltageMode : FSP_M_CONFIG
  • CoreVoltageOffset : FSP_M_CONFIG
  • CoreVoltageOverride : FSP_M_CONFIG
  • Count : FIRMWARE_VERSION_INFO_HOB
  • CpuBistData : FSP_S_CONFIG
  • CpuMpHob : FSP_S_CONFIG
  • CpuMpPpi : FSP_S_CONFIG
  • CpuRatio : FSP_M_CONFIG
  • CpuTraceHubMemReg0Size : FSP_M_CONFIG
  • CpuTraceHubMemReg1Size : FSP_M_CONFIG
  • CpuTraceHubMode : FSP_M_CONFIG
  • CpuWakeUpTimer : FSP_S_TEST_CONFIG
  • CridEnable : FSP_S_CONFIG
  • CstateLatencyControl0Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl1Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl2Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl3Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl4Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : FSP_S_TEST_CONFIG
  • CstateLatencyControl5Irtl : FSP_S_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : FSP_S_TEST_CONFIG
  • CStatePreWake : FSP_S_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : FSP_S_TEST_CONFIG
  • CurrentSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • CurrentSramType : SMBIOS_CACHE_INFO
  • Custom1ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom1PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom1PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom1TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom2ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom2PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom2PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom2TurboActivationRatio : FSP_S_TEST_CONFIG
  • Custom3ConfigTdpControl : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1 : FSP_S_TEST_CONFIG
  • Custom3PowerLimit1Time : FSP_S_TEST_CONFIG
  • Custom3PowerLimit2 : FSP_S_TEST_CONFIG
  • Custom3TurboActivationRatio : FSP_S_TEST_CONFIG
  • Cx : FSP_S_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- d -

  • Data : AUDIO_AZALIA_VERB_TABLE
  • DataDwords : AZALIA_HEADER
  • DciUsb3TypecUfpDbg : FSP_M_CONFIG
  • DcLoadline : FSP_S_CONFIG
  • DdiPortBDdc : FSP_S_CONFIG
  • DdiPortBHpd : FSP_S_CONFIG
  • DdiPortCDdc : FSP_S_CONFIG
  • DdiPortCHpd : FSP_S_CONFIG
  • DdiPortDDdc : FSP_S_CONFIG
  • DdiPortDHpd : FSP_S_CONFIG
  • DdiPortEdp : FSP_S_CONFIG
  • DdiPortFDdc : FSP_S_CONFIG
  • DdiPortFHpd : FSP_S_CONFIG
  • Ddr4DdpSharedClock : FSP_M_CONFIG
  • Ddr4DdpSharedZq : FSP_M_CONFIG
  • Ddr4MixedUDimm2DpcLimit : FSP_M_CONFIG
  • DdrFreqLimit : FSP_M_CONFIG
  • DdrThermalSensor : FSP_M_CONFIG
  • DebugInterfaceEnable : FSP_S_CONFIG , FSP_S_TEST_CONFIG
  • DebugInterfaceLockEnable : FSP_S_TEST_CONFIG
  • DeltaT12PowerCycleDelay : FSP_S_CONFIG
  • Device : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Device4Enable : FSP_S_CONFIG
  • DeviceId : AZALIA_HEADER
  • DevIntConfigPtr : FSP_S_CONFIG
  • DidInitStat : FSP_M_TEST_CONFIG
  • DimmCapacity : DIMM_INFO
  • DIMMODTT : FSP_M_CONFIG
  • DIMMRONT : FSP_M_CONFIG
  • Direction : GPIO_CONFIG
  • DisableCpuReplacedPolling : FSP_M_TEST_CONFIG
  • DisableD0I3SettingForHeci : FSP_S_TEST_CONFIG
  • DisableDimmChannel0 : FSP_M_CONFIG
  • DisableDimmChannel1 : FSP_M_CONFIG
  • DisableHeciRetry : FSP_M_TEST_CONFIG
  • DisableMessageCheck : FSP_M_TEST_CONFIG
  • DisableMtrrProgram : FSP_M_CONFIG
  • DisableProcHotOut : FSP_S_TEST_CONFIG
  • DisableTurboGt : FSP_S_TEST_CONFIG
  • DisableVrThermalAlert : FSP_S_TEST_CONFIG
  • DllBwEn0 : FSP_M_CONFIG
  • DllBwEn1 : FSP_M_CONFIG
  • DllBwEn2 : FSP_M_CONFIG
  • DllBwEn3 : FSP_M_CONFIG
  • DmiAspm : FSP_S_CONFIG
  • DmiDeEmphasis : FSP_M_CONFIG
  • DmiExtSync : FSP_S_TEST_CONFIG
  • DmiGen3EndPointHint : FSP_M_CONFIG
  • DmiGen3EndPointPreset : FSP_M_CONFIG
  • DmiGen3EqPh2Enable : FSP_M_TEST_CONFIG
  • DmiGen3EqPh3Method : FSP_M_TEST_CONFIG
  • DmiGen3ProgramStaticEq : FSP_M_CONFIG
  • DmiGen3RootPortPreset : FSP_M_CONFIG
  • DmiGen3RxCtlePeaking : FSP_M_CONFIG
  • DmiIot : FSP_S_TEST_CONFIG
  • DmiMaxLinkSpeed : FSP_M_TEST_CONFIG
  • DmiSuggestedSetting : FSP_S_CONFIG
  • DmiTS0TW : FSP_S_CONFIG
  • DmiTS1TW : FSP_S_CONFIG
  • DmiTS2TW : FSP_S_CONFIG
  • DmiTS3TW : FSP_S_CONFIG
  • DqByteMapCh0 : FSP_M_CONFIG
  • DqByteMapCh1 : FSP_M_CONFIG
  • DqPinsInterleaved : FSP_M_CONFIG
  • DqsMapCpu2DramCh0 : FSP_M_CONFIG
  • DqsMapCpu2DramCh1 : FSP_M_CONFIG
  • DualDimmPerChannelBoardType : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- e -

  • EcCmdLock : FSP_S_CONFIG
  • EcCmdProvisionEav : FSP_S_CONFIG
  • EccSupport : FSP_M_CONFIG
  • ECT : FSP_M_CONFIG
  • EdramTestMode : FSP_S_TEST_CONFIG
  • EightCoreRatioLimit : FSP_S_TEST_CONFIG
  • Eist : FSP_S_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • Enable8254ClockGating : FSP_S_CONFIG
  • Enable8254ClockGatingOnS3 : FSP_S_CONFIG
  • EnableC6Dram : FSP_M_CONFIG
  • EnableCltm : FSP_M_CONFIG
  • EnabledCoreCount : SMBIOS_PROCESSOR_INFO
  • EnableExtts : FSP_M_CONFIG
  • EnableItbm : FSP_S_TEST_CONFIG
  • EnableItbmDriver : FSP_S_TEST_CONFIG
  • EnableOltm : FSP_M_CONFIG
  • EnablePwrDn : FSP_M_CONFIG
  • EnablePwrDnLpddr : FSP_M_CONFIG
  • EnableSgx : FSP_M_CONFIG
  • EnableTcoTimer : FSP_S_CONFIG
  • EnBER : FSP_M_CONFIG
  • EnCmdRate : FSP_M_CONFIG
  • EndOfPostMessage : FSP_S_TEST_CONFIG
  • EnergyEfficientPState : FSP_S_TEST_CONFIG
  • EnergyEfficientTurbo : FSP_S_TEST_CONFIG
  • EnergyScaleFact : FSP_M_CONFIG
  • EnhancedInterleave : FSP_M_CONFIG
  • EpgEnable : FSP_M_CONFIG
  • ERDMPRTC2D : FSP_M_CONFIG
  • ERDTC2D : FSP_M_CONFIG
  • ErrorCorrectionType : SMBIOS_CACHE_INFO
  • EsataSpeedLimit : FSP_S_CONFIG
  • EWRDSEQ : FSP_M_CONFIG
  • EWRTC2D : FSP_M_CONFIG
  • ExitOnFailure : FSP_M_CONFIG
  • ExternalClockInMHz : SMBIOS_PROCESSOR_INFO


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- f -

  • FastPkgCRampDisableFivr : FSP_S_CONFIG
  • FastPkgCRampDisableGt : FSP_S_CONFIG
  • FastPkgCRampDisableIa : FSP_S_CONFIG
  • FastPkgCRampDisableSa : FSP_S_CONFIG
  • FClkFrequency : FSP_M_CONFIG
  • FiveCoreRatioLimit : FSP_S_TEST_CONFIG
  • FivrEfficiency : FSP_M_CONFIG
  • FivrFaults : FSP_M_CONFIG
  • FivrRfiFrequency : FSP_S_CONFIG
  • FivrSpreadSpectrum : FSP_S_CONFIG
  • ForceOltmOrRefresh2x : FSP_M_CONFIG
  • ForcMebxSyncUp : FSP_S_CONFIG
  • FourCoreRatioLimit : FSP_S_TEST_CONFIG
  • FreqSaGvLow : FSP_M_CONFIG
  • FreqSaGvMid : FSP_M_CONFIG
  • FspmArchUpd : FSPM_UPD
  • FspmConfig : FSPM_UPD
  • FspmTestConfig : FSPM_UPD
  • FspsConfig : FSPS_UPD
  • FspsTestConfig : FSPS_UPD
  • FsptConfig : FSPT_UPD
  • FsptCoreUpd : FSPT_UPD
  • FspUpdHeader : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Function : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • FwProgress : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- g -

  • GdxcEnable : FSP_M_CONFIG
  • GdxcIotSize : FSP_M_CONFIG
  • GdxcMotSize : FSP_M_CONFIG
  • Gen3SwEqAlwaysAttempt : FSP_M_TEST_CONFIG
  • Gen3SwEqEnableVocTest : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqJitterErrorTarget : FSP_M_TEST_CONFIG
  • Gen3SwEqNumberOfPresets : FSP_M_TEST_CONFIG
  • Gen3SwEqVocDwellTime : FSP_M_TEST_CONFIG
  • Gen3SwEqVocErrorTarget : FSP_M_TEST_CONFIG
  • GmAdr : FSP_M_CONFIG
  • GnaEnable : FSP_S_CONFIG
  • GpioIrqRoute : FSP_S_CONFIG
  • GraphicsConfigPtr : FSP_S_CONFIG
  • GtExtraTurboVoltage : FSP_M_CONFIG
  • GtFreqMax : FSP_S_TEST_CONFIG
  • GtMaxOcRatio : FSP_M_CONFIG
  • GtPllVoltageOffset : FSP_M_CONFIG
  • GtPsmiSupport : FSP_M_CONFIG
  • GttMmAdr : FSP_M_CONFIG
  • GttSize : FSP_M_CONFIG
  • GtusExtraTurboVoltage : FSP_M_CONFIG
  • GtusMaxOcRatio : FSP_M_CONFIG
  • GtusVoltageMode : FSP_M_CONFIG
  • GtusVoltageOffset : FSP_M_CONFIG
  • GtusVoltageOverride : FSP_M_CONFIG
  • GtVoltageMode : FSP_M_CONFIG
  • GtVoltageOffset : FSP_M_CONFIG
  • GtVoltageOverride : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- h -

  • HdcControl : FSP_S_TEST_CONFIG
  • Header : AUDIO_AZALIA_VERB_TABLE , FIRMWARE_VERSION_INFO_HOB
  • Heci1BarAddress : FSP_M_CONFIG
  • Heci2BarAddress : FSP_M_CONFIG
  • Heci3BarAddress : FSP_M_CONFIG
  • Heci3Enabled : FSP_S_CONFIG
  • HeciCommunication2 : FSP_M_TEST_CONFIG
  • HeciTimeouts : FSP_M_CONFIG
  • HobBufferSize : FSP_M_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • HotBudgetCh0Dimm0 : FSP_M_CONFIG
  • HotBudgetCh0Dimm1 : FSP_M_CONFIG
  • HotBudgetCh1Dimm0 : FSP_M_CONFIG
  • HotBudgetCh1Dimm1 : FSP_M_CONFIG
  • HotThresholdCh0Dimm0 : FSP_M_CONFIG
  • HotThresholdCh0Dimm1 : FSP_M_CONFIG
  • HotThresholdCh1Dimm0 : FSP_M_CONFIG
  • HotThresholdCh1Dimm1 : FSP_M_CONFIG
  • Hwp : FSP_S_TEST_CONFIG
  • HwpInterruptControl : FSP_S_TEST_CONFIG
  • HyperThreading : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- i -

  • IccMax : FSP_S_CONFIG
  • Idd3n : FSP_M_CONFIG
  • Idd3p : FSP_M_CONFIG
  • IdleEnergyCh0Dimm0 : FSP_M_CONFIG
  • IdleEnergyCh0Dimm1 : FSP_M_CONFIG
  • IdleEnergyCh1Dimm0 : FSP_M_CONFIG
  • IdleEnergyCh1Dimm1 : FSP_M_CONFIG
  • IedSize : FSP_M_CONFIG
  • IgdDvmt50PreAlloc : FSP_M_CONFIG
  • ImonOffset : FSP_S_CONFIG
  • ImonSlope : FSP_S_CONFIG
  • ImonSlope1 : FSP_S_CONFIG
  • ImrRpSelection : FSP_M_CONFIG
  • InitPcieAspmAfterOprom : FSP_M_CONFIG
  • InstalledSize : SMBIOS_CACHE_INFO
  • InstalledSize2 : SMBIOS_CACHE_INFO
  • InternalGfx : FSP_M_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • IntX : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • Irq : SI_PCH_DEVICE_INTERRUPT_CONFIG
  • IslVrCmd : FSP_S_CONFIG
  • IsTPMPresence : FSP_M_CONFIG
  • IsvtIoPort : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- j -

  • JtagC10PowerGateDisable : FSP_M_CONFIG
  • JWRL : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- k -

  • KtDeviceEnable : FSP_M_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- l -

  • LCT : FSP_M_CONFIG
  • LockConfig : GPIO_CONFIG
  • LockPTMregs : FSP_M_TEST_CONFIG
  • LogoPtr : FSP_S_CONFIG
  • LogoSize : FSP_S_CONFIG
  • LpDdrDqDqsReTraining : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- m -

  • MachineCheckEnable : FSP_S_TEST_CONFIG
  • ManageabilityMode : FSP_S_CONFIG
  • MaxCacheSize : SMBIOS_CACHE_INFO
  • MaximumCacheSize2 : SMBIOS_CACHE_INFO
  • MaxRatio : FSP_S_TEST_CONFIG
  • MaxRingRatioLimit : FSP_S_TEST_CONFIG
  • McivrRfiFrequencyAdjust : FSP_S_CONFIG
  • McivrRfiFrequencyPrefix : FSP_S_CONFIG
  • McivrSpreadSpectrum : FSP_S_CONFIG
  • McPllVoltageOffset : FSP_M_CONFIG
  • MctpBroadcastCycle : FSP_S_TEST_CONFIG
  • MeChipInitCrc : CHIPSET_INIT_INFO
  • MemorySpdDataLen : FSP_M_CONFIG
  • MemorySpdPtr00 : FSP_M_CONFIG
  • MemorySpdPtr01 : FSP_M_CONFIG
  • MemorySpdPtr10 : FSP_M_CONFIG
  • MemorySpdPtr11 : FSP_M_CONFIG
  • MemoryTrace : FSP_M_CONFIG
  • MemTestOnWarmBoot : FSP_M_CONFIG
  • MEMTST : FSP_M_CONFIG
  • MeUnconfigOnRtcClear : FSP_S_CONFIG
  • MicrocodeRegionBase : FSP_S_CONFIG , FSPT_CORE_UPD
  • MicrocodeRegionSize : FSP_S_CONFIG , FSPT_CORE_UPD
  • MinRingRatioLimit : FSP_S_TEST_CONFIG
  • MlcSpatialPrefetcher : FSP_S_TEST_CONFIG
  • MlcStreamerPrefetcher : FSP_S_TEST_CONFIG
  • MmioSize : FSP_M_CONFIG
  • MmioSizeAdjustment : FSP_M_CONFIG
  • ModulePartNum : DIMM_INFO
  • MonitorMwaitEnable : FSP_S_TEST_CONFIG
  • MrcFastBoot : FSP_M_CONFIG
  • MrcSafeConfig : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- n -

  • NModeSupport : FSP_M_CONFIG
  • NumberOfCacheLevels : SMBIOS_CACHE_INFO
  • NumberOfEntries : FSP_S_TEST_CONFIG
  • NumOfDevIntConfig : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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  • Variables
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- o -

  • OcLock : FSP_M_CONFIG
  • OcSupport : FSP_M_CONFIG
  • OddRatioMode : FSP_M_CONFIG
  • OneCoreRatioLimit : FSP_S_TEST_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputState : GPIO_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

  • All
  • Variables
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- p -

  • PadMode : GPIO_CONFIG
  • PanelPowerEnable : FSP_M_TEST_CONFIG
  • PavpEnable : FSP_S_CONFIG
  • PcdDebugInterfaceFlags : FSP_M_CONFIG
  • PcdIsaSerialUartBase : FSP_M_CONFIG
  • PcdPciExpressBaseAddress : FSP_T_CONFIG
  • PcdPciExpressRegionLength : FSP_T_CONFIG
  • PcdSerialDebugBaudRate : FSP_M_CONFIG
  • PcdSerialDebugLevel : FSP_M_CONFIG
  • PcdSerialIoUart0PinMuxing : FSP_T_CONFIG
  • PcdSerialIoUartDebugEnable : FSP_T_CONFIG
  • PcdSerialIoUartInputClock : FSP_T_CONFIG
  • PcdSerialIoUartNumber : FSP_M_CONFIG , FSP_T_CONFIG
  • PchCnviMfUart1Type : FSP_S_CONFIG
  • PchCnviMode : FSP_S_CONFIG
  • PchCrid : FSP_S_CONFIG
  • PchDmiAspm : FSP_S_CONFIG
  • PchDmiAspmCtrl : FSP_S_CONFIG
  • PchDmiTsawEn : FSP_S_CONFIG
  • PchEnableComplianceMode : FSP_S_CONFIG
  • PchEnableDbcObs : FSP_S_CONFIG
  • PchEspiBmeMasterSlaveEnabled : FSP_S_CONFIG
  • PchEspiLgmrEnable : FSP_S_CONFIG
  • PchHdaAudioLinkDmic0 : FSP_S_CONFIG
  • PchHdaAudioLinkDmic1 : FSP_S_CONFIG
  • PchHdaAudioLinkHda : FSP_S_CONFIG
  • PchHdaAudioLinkSndw1 : FSP_S_CONFIG
  • PchHdaAudioLinkSndw2 : FSP_S_CONFIG
  • PchHdaAudioLinkSndw3 : FSP_S_CONFIG
  • PchHdaAudioLinkSndw4 : FSP_S_CONFIG
  • PchHdaAudioLinkSsp0 : FSP_S_CONFIG
  • PchHdaAudioLinkSsp1 : FSP_S_CONFIG
  • PchHdaAudioLinkSsp2 : FSP_S_CONFIG
  • PchHdaCodecSxWakeCapability : FSP_S_CONFIG
  • PchHdaDspEnable : FSP_S_CONFIG
  • PchHdaDspUaaCompliance : FSP_S_CONFIG
  • PchHdaEnable : FSP_M_CONFIG
  • PchHdaIDispCodecDisconnect : FSP_S_CONFIG
  • PchHdaIDispLinkFrequency : FSP_S_CONFIG
  • PchHdaIDispLinkTmode : FSP_S_CONFIG
  • PchHdaLinkFrequency : FSP_S_CONFIG
  • PchHdaPme : FSP_S_CONFIG
  • PchHdaResetWaitTimer : FSP_S_TEST_CONFIG
  • PchHdaSndwBufferRcomp : FSP_S_CONFIG
  • PchHdaVcType : FSP_S_CONFIG
  • PchHdaVerbTableEntryNum : FSP_S_CONFIG
  • PchHdaVerbTablePtr : FSP_S_CONFIG
  • PchHotEnable : FSP_S_CONFIG
  • PchIoApicEntry24_119 : FSP_S_CONFIG
  • PchIoApicId : FSP_S_CONFIG
  • PchIshEnable : FSP_M_CONFIG
  • PchIshGp0GpioAssign : FSP_S_CONFIG
  • PchIshGp1GpioAssign : FSP_S_CONFIG
  • PchIshGp2GpioAssign : FSP_S_CONFIG
  • PchIshGp3GpioAssign : FSP_S_CONFIG
  • PchIshGp4GpioAssign : FSP_S_CONFIG
  • PchIshGp5GpioAssign : FSP_S_CONFIG
  • PchIshGp6GpioAssign : FSP_S_CONFIG
  • PchIshGp7GpioAssign : FSP_S_CONFIG
  • PchIshI2c0GpioAssign : FSP_S_CONFIG
  • PchIshI2c1GpioAssign : FSP_S_CONFIG
  • PchIshI2c2GpioAssign : FSP_S_CONFIG
  • PchIshPdtUnlock : FSP_S_CONFIG
  • PchIshSpiGpioAssign : FSP_S_CONFIG
  • PchIshUart0GpioAssign : FSP_S_CONFIG
  • PchIshUart1GpioAssign : FSP_S_CONFIG
  • PchLanEnable : FSP_S_CONFIG
  • PchLanLtrEnable : FSP_S_CONFIG
  • PchLockDownBiosInterface : FSP_S_TEST_CONFIG
  • PchLockDownBiosLock : FSP_S_CONFIG
  • PchLockDownGlobalSmi : FSP_S_TEST_CONFIG
  • PchLockDownRtcMemoryLock : FSP_S_CONFIG
  • PchLpcEnhancePort8xhDecoding : FSP_M_CONFIG
  • PchMemoryC0TransmitEnable : FSP_S_CONFIG
  • PchMemoryPinSelection : FSP_S_CONFIG
  • PchMemoryPmsyncEnable : FSP_S_CONFIG
  • PchMemoryThrottlingEnable : FSP_S_CONFIG
  • PchNumRsvdSmbusAddresses : FSP_M_CONFIG
  • PchPcieDeviceOverrideTablePtr : FSP_S_CONFIG
  • PchPcieHsioRxSetCtle : FSP_M_CONFIG
  • PchPcieHsioRxSetCtleEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchPcieHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph3p5Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0 : FSP_M_CONFIG
  • PchPcieHsioTxGen2DeEmph6p0Enable : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchPcieHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchPciePort8xhDecodePortIndex : FSP_S_TEST_CONFIG
  • PchPmDeepSxPol : FSP_S_CONFIG
  • PchPmDisableDsxAcPresentPulldown : FSP_S_CONFIG
  • PchPmDisableEnergyReport : FSP_S_TEST_CONFIG
  • PchPmDisableNativePowerButton : FSP_S_CONFIG
  • PchPmLanWakeFromDeepSx : FSP_S_CONFIG
  • PchPmLpcClockRun : FSP_S_CONFIG
  • PchPmMeWakeSts : FSP_S_CONFIG
  • PchPmPciePllSsc : FSP_S_CONFIG
  • PchPmPcieWakeFromDeepSx : FSP_S_CONFIG
  • PchPmPmeB0S5Dis : FSP_S_CONFIG
  • PchPmPwrBtnOverridePeriod : FSP_S_CONFIG
  • PchPmPwrCycDur : FSP_S_CONFIG
  • PchPmSlpAMinAssert : FSP_S_CONFIG
  • PchPmSlpLanLowDc : FSP_S_CONFIG
  • PchPmSlpS0Enable : FSP_S_CONFIG
  • PchPmSlpS0Vm070VSupport : FSP_S_CONFIG
  • PchPmSlpS0Vm075VSupport : FSP_S_CONFIG
  • PchPmSlpS0VmRuntimeControl : FSP_S_CONFIG
  • PchPmSlpS3MinAssert : FSP_S_CONFIG
  • PchPmSlpS4MinAssert : FSP_S_CONFIG
  • PchPmSlpStrchSusUp : FSP_S_CONFIG
  • PchPmSlpSusMinAssert : FSP_S_CONFIG
  • PchPmVrAlert : FSP_S_CONFIG
  • PchPmWolEnableOverride : FSP_S_CONFIG
  • PchPmWolOvrWkSts : FSP_S_CONFIG
  • PchPmWoWlanDeepSxEnable : FSP_S_CONFIG
  • PchPmWoWlanEnable : FSP_S_CONFIG
  • PchPort80Route : FSP_M_CONFIG
  • PchPostMemRsvd : FSP_S_CONFIG
  • PchPreMemRsvd : FSP_M_CONFIG
  • PchProtectedRangeBase : FSP_S_CONFIG
  • PchProtectedRangeLimit : FSP_S_CONFIG
  • PchPwrOptEnable : FSP_S_CONFIG
  • PchReadProtectionEnable : FSP_S_CONFIG
  • PchSataHsioRxGen1EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen1EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen2EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMag : FSP_M_CONFIG
  • PchSataHsioRxGen3EqBoostMagEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen1DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen1DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen2DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen2DownscaleAmpEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmph : FSP_M_CONFIG
  • PchSataHsioTxGen3DeEmphEnable : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmp : FSP_M_CONFIG
  • PchSataHsioTxGen3DownscaleAmpEnable : FSP_M_CONFIG
  • PchSbAccessUnlock : FSP_S_TEST_CONFIG
  • PchSbiUnlock : FSP_S_TEST_CONFIG
  • PchScsEmmcHs400DllDataValid : FSP_S_CONFIG
  • PchScsEmmcHs400DriverStrength : FSP_S_CONFIG
  • PchScsEmmcHs400RxStrobeDll1 : FSP_S_CONFIG
  • PchScsEmmcHs400TuningRequired : FSP_S_CONFIG
  • PchScsEmmcHs400TxDataDll : FSP_S_CONFIG
  • PchSerialIoI2cPadsTermination : FSP_S_CONFIG
  • PchSirqEnable : FSP_S_CONFIG
  • PchSirqMode : FSP_S_CONFIG
  • PchSmbAlertEnable : FSP_M_CONFIG
  • PchSmbusIoBase : FSP_M_CONFIG
  • PchStartFramePulse : FSP_S_CONFIG
  • PchT0Level : FSP_S_CONFIG
  • PchT1Level : FSP_S_CONFIG
  • PchT2Level : FSP_S_CONFIG
  • PchTemperatureHotLevel : FSP_S_CONFIG
  • PchTraceHubMemReg0Size : FSP_M_CONFIG
  • PchTraceHubMemReg1Size : FSP_M_CONFIG
  • PchTraceHubMode : FSP_M_CONFIG
  • PchTsmicLock : FSP_S_CONFIG
  • PchTTEnable : FSP_S_CONFIG
  • PchTTLock : FSP_S_CONFIG
  • PchTTState13Enable : FSP_S_CONFIG
  • PchUnlockGpioPads : FSP_S_TEST_CONFIG
  • PchUsb2PhySusPgEnable : FSP_S_CONFIG
  • PchUsbHsioFilterSel : FSP_S_CONFIG
  • PchUsbHsioRxTuningEnable : FSP_S_CONFIG
  • PchUsbHsioRxTuningParameters : FSP_S_CONFIG
  • PchUsbOverCurrentEnable : FSP_S_CONFIG
  • PchWriteProtectionEnable : FSP_S_CONFIG
  • PchXhciOcLock : FSP_S_TEST_CONFIG
  • PcieClkSrcClkReq : FSP_S_CONFIG
  • PcieClkSrcUsage : FSP_S_CONFIG
  • PcieComplianceTestMode : FSP_S_CONFIG
  • PcieDisableRootPortClockGating : FSP_S_CONFIG
  • PcieEnablePeerMemoryWrite : FSP_S_CONFIG
  • PcieEnablePort8xhDecode : FSP_S_TEST_CONFIG
  • PcieEqPh3LaneParamCm : FSP_S_CONFIG
  • PcieEqPh3LaneParamCp : FSP_S_CONFIG
  • PcieImrEnabled : FSP_M_CONFIG
  • PcieImrSize : FSP_M_CONFIG
  • PcieRootPortGen2PllL1CgDisable : FSP_S_CONFIG
  • PcieRpAcsEnabled : FSP_S_CONFIG
  • PcieRpAdvancedErrorReporting : FSP_S_CONFIG
  • PcieRpAspm : FSP_S_CONFIG
  • PcieRpClkReqDetect : FSP_S_CONFIG
  • PcieRpCompletionTimeout : FSP_S_CONFIG
  • PcieRpCorrectableErrorReport : FSP_S_CONFIG
  • PcieRpDetectTimeoutMs : FSP_S_CONFIG
  • PcieRpDpcExtensionsMask : FSP_S_CONFIG
  • PcieRpDpcMask : FSP_S_CONFIG
  • PcieRpDptp : FSP_S_TEST_CONFIG
  • PcieRpEnableCpm : FSP_S_CONFIG
  • PcieRpEnableMask : FSP_M_CONFIG
  • PcieRpExtSync : FSP_S_CONFIG
  • PcieRpFatalErrorReport : FSP_S_CONFIG
  • PcieRpFunctionSwap : FSP_S_CONFIG
  • PcieRpGen3EqPh3Method : FSP_S_CONFIG
  • PcieRpHotPlug : FSP_S_CONFIG
  • PcieRpImrEnabled : FSP_S_CONFIG
  • PcieRpImrSelection : FSP_S_CONFIG
  • PcieRpL1Substates : FSP_S_CONFIG
  • PcieRpLtrConfigLock : FSP_S_CONFIG
  • PcieRpLtrEnable : FSP_S_CONFIG
  • PcieRpLtrMaxNoSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpLtrMaxSnoopLatency : FSP_S_TEST_CONFIG
  • PcieRpMaxPayload : FSP_S_CONFIG
  • PcieRpNoFatalErrorReport : FSP_S_CONFIG
  • PcieRpNonSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpNonSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpPcieSpeed : FSP_S_CONFIG
  • PcieRpPhysicalSlotNumber : FSP_S_CONFIG
  • PcieRpPmSci : FSP_S_CONFIG
  • PcieRpPtmMask : FSP_S_CONFIG
  • PcieRpSlotImplemented : FSP_S_CONFIG
  • PcieRpSlotPowerLimitScale : FSP_S_TEST_CONFIG
  • PcieRpSlotPowerLimitValue : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMode : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideMultiplier : FSP_S_TEST_CONFIG
  • PcieRpSnoopLatencyOverrideValue : FSP_S_TEST_CONFIG
  • PcieRpSystemErrorOnCorrectableError : FSP_S_CONFIG
  • PcieRpSystemErrorOnFatalError : FSP_S_CONFIG
  • PcieRpSystemErrorOnNonFatalError : FSP_S_CONFIG
  • PcieRpTransmitterHalfSwing : FSP_S_CONFIG
  • PcieRpUnsupportedRequestReport : FSP_S_CONFIG
  • PcieRpUptp : FSP_S_TEST_CONFIG
  • PcieSwEqCoeffListCm : FSP_S_CONFIG
  • PcieSwEqCoeffListCp : FSP_S_CONFIG
  • PdEnergyCh0Dimm0 : FSP_M_CONFIG
  • PdEnergyCh0Dimm1 : FSP_M_CONFIG
  • PdEnergyCh1Dimm0 : FSP_M_CONFIG
  • PdEnergyCh1Dimm1 : FSP_M_CONFIG
  • PeciC10Reset : FSP_M_CONFIG
  • PeciSxReset : FSP_M_CONFIG
  • Peg0Enable : FSP_M_CONFIG
  • Peg0Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg0Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg0MaxLinkSpeed : FSP_M_CONFIG
  • Peg0MaxLinkWidth : FSP_M_CONFIG
  • Peg0PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg1Enable : FSP_M_CONFIG
  • Peg1Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg1Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg1MaxLinkSpeed : FSP_M_CONFIG
  • Peg1MaxLinkWidth : FSP_M_CONFIG
  • Peg1PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg2Enable : FSP_M_CONFIG
  • Peg2Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg2Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg2MaxLinkSpeed : FSP_M_CONFIG
  • Peg2MaxLinkWidth : FSP_M_CONFIG
  • Peg2PowerDownUnusedLanes : FSP_M_CONFIG
  • Peg3Enable : FSP_M_CONFIG
  • Peg3Gen3EqPh2Enable : FSP_M_TEST_CONFIG
  • Peg3Gen3EqPh3Method : FSP_M_TEST_CONFIG
  • Peg3MaxLinkSpeed : FSP_M_CONFIG
  • Peg3MaxLinkWidth : FSP_M_CONFIG
  • Peg3PowerDownUnusedLanes : FSP_M_CONFIG
  • PegDataPtr : FSP_M_CONFIG
  • PegDeEmphasis : FSP_S_CONFIG
  • PegDisableSpreadSpectrumClocking : FSP_M_CONFIG
  • PegGen3EndPointHint : FSP_M_TEST_CONFIG
  • PegGen3EndPointPreset : FSP_M_TEST_CONFIG
  • PegGen3ProgramStaticEq : FSP_M_TEST_CONFIG
  • PegGen3RootPortPreset : FSP_M_TEST_CONFIG
  • PegGen3Rsvd : FSP_M_TEST_CONFIG
  • PegGen3RxCtleOverride : FSP_M_TEST_CONFIG
  • PegGen3RxCtlePeaking : FSP_M_CONFIG
  • PegGenerateBdatMarginTable : FSP_M_TEST_CONFIG
  • PegGpioData : FSP_M_CONFIG
  • PegMaxPayload : FSP_S_TEST_CONFIG
  • PegPhysicalSlotNumber : FSP_S_CONFIG
  • PegRootPortHPE : FSP_M_CONFIG
  • PegRxCemLoopbackLane : FSP_M_TEST_CONFIG
  • PegRxCemNonProtocolAwareness : FSP_M_TEST_CONFIG
  • PegRxCemTestingMode : FSP_M_TEST_CONFIG
  • PegSlotPowerLimitScale : FSP_S_CONFIG
  • PegSlotPowerLimitValue : FSP_S_CONFIG
  • PeiGraphicsPeimInit : FSP_S_CONFIG
  • PkgCStateDemotion : FSP_S_TEST_CONFIG
  • PkgCStateLimit : FSP_S_TEST_CONFIG
  • PkgCStateUnDemotion : FSP_S_TEST_CONFIG
  • PlatformDebugConsent : FSP_M_CONFIG
  • PlatformMemorySize : FSP_M_CONFIG
  • PmcCpuC10GatePinEnable : FSP_S_CONFIG
  • PmcDbgMsgEn : FSP_S_CONFIG
  • PmcModPhySusPgEnable : FSP_S_CONFIG
  • PmcPowerButtonDebounce : FSP_S_CONFIG
  • PmgCstCfgCtrlLock : FSP_S_TEST_CONFIG
  • PmSupport : FSP_S_TEST_CONFIG
  • PortUsb20Enable : FSP_S_CONFIG
  • PortUsb30Enable : FSP_S_CONFIG
  • PostCodeOutputPort : FSP_M_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerLimit1 : FSP_S_TEST_CONFIG
  • PowerLimit1Time : FSP_S_TEST_CONFIG
  • PowerLimit2 : FSP_S_TEST_CONFIG
  • PowerLimit2Power : FSP_S_TEST_CONFIG
  • PowerLimit3 : FSP_S_TEST_CONFIG
  • PowerLimit3DutyCycle : FSP_S_TEST_CONFIG
  • PowerLimit3Lock : FSP_S_TEST_CONFIG
  • PowerLimit3Time : FSP_S_TEST_CONFIG
  • PowerLimit4 : FSP_S_TEST_CONFIG
  • PowerLimit4Lock : FSP_S_TEST_CONFIG
  • PpmIrmSetting : FSP_S_TEST_CONFIG
  • PreWake : FSP_S_CONFIG
  • PrimaryDisplay : FSP_M_CONFIG
  • PrmrrSize : FSP_M_CONFIG
  • ProbelessTrace : FSP_M_CONFIG
  • ProcessorCharacteristics : SMBIOS_PROCESSOR_INFO
  • ProcessorFamily : SMBIOS_PROCESSOR_INFO
  • ProcessorId : SMBIOS_PROCESSOR_INFO
  • ProcessorManufacturerStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcessorTraceEnable : FSP_S_TEST_CONFIG
  • ProcessorTraceMemBase : FSP_S_TEST_CONFIG
  • ProcessorTraceMemLength : FSP_S_TEST_CONFIG
  • ProcessorTraceOutputScheme : FSP_S_TEST_CONFIG
  • ProcessorType : SMBIOS_PROCESSOR_INFO
  • ProcessorUpgrade : SMBIOS_PROCESSOR_INFO
  • ProcessorVersionStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcHotLock : FSP_S_TEST_CONFIG
  • ProcHotResponse : FSP_S_TEST_CONFIG
  • Psi1Threshold : FSP_S_CONFIG
  • Psi2Threshold : FSP_S_CONFIG
  • Psi3Enable : FSP_S_CONFIG
  • Psi3Threshold : FSP_S_CONFIG
  • Psi4Enable : FSP_S_CONFIG
  • PsmiRegionSize : FSP_M_CONFIG
  • PsOnEnable : FSP_S_CONFIG
  • PsysOffset : FSP_S_CONFIG
  • PsysPmax : FSP_S_TEST_CONFIG
  • PsysPowerLimit1 : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Power : FSP_S_TEST_CONFIG
  • PsysPowerLimit1Time : FSP_S_TEST_CONFIG
  • PsysPowerLimit2 : FSP_S_TEST_CONFIG
  • PsysPowerLimit2Power : FSP_S_TEST_CONFIG
  • PsysSlope : FSP_S_CONFIG
  • PwdwnIdleCounter : FSP_M_CONFIG
  • PxRcConfig : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

  • All
  • Variables
  • a
  • b
  • c
  • d
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  • f
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  • i
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  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x

- r -

  • RaceToHalt : FSP_S_TEST_CONFIG
  • RampDown : FSP_S_CONFIG
  • RampUp : FSP_S_CONFIG
  • RankInDimm : DIMM_INFO
  • RankInterleave : FSP_M_CONFIG
  • RaplLim1Ena : FSP_M_CONFIG
  • RaplLim1Pwr : FSP_M_CONFIG
  • RaplLim1WindX : FSP_M_CONFIG
  • RaplLim1WindY : FSP_M_CONFIG
  • RaplLim2Ena : FSP_M_CONFIG
  • RaplLim2Lock : FSP_M_CONFIG
  • RaplLim2Pwr : FSP_M_CONFIG
  • RaplLim2WindX : FSP_M_CONFIG
  • RaplLim2WindY : FSP_M_CONFIG
  • RaplPwrFlCh0 : FSP_M_CONFIG
  • RaplPwrFlCh1 : FSP_M_CONFIG
  • Ratio : FSP_M_CONFIG
  • RcompResistor : FSP_M_CONFIG
  • RcompTarget : FSP_M_CONFIG
  • RCVENC1D : FSP_M_CONFIG
  • RCVET : FSP_M_CONFIG
  • RDAPT : FSP_M_CONFIG
  • RdEnergyCh0Dimm0 : FSP_M_CONFIG
  • RdEnergyCh0Dimm1 : FSP_M_CONFIG
  • RdEnergyCh1Dimm0 : FSP_M_CONFIG
  • RdEnergyCh1Dimm1 : FSP_M_CONFIG
  • RDEQT : FSP_M_CONFIG
  • RDMPRT : FSP_M_CONFIG
  • RDODTT : FSP_M_CONFIG
  • RDTC1D : FSP_M_CONFIG
  • RDTC2D : FSP_M_CONFIG
  • RDVC2D : FSP_M_CONFIG
  • RealtimeMemoryTiming : FSP_M_CONFIG
  • RefClk : FSP_M_CONFIG
  • Refresh2X : FSP_M_CONFIG
  • RemapEnable : FSP_M_CONFIG
  • RemoteAssistance : FSP_S_CONFIG
  • RenderStandby : FSP_S_TEST_CONFIG
  • Reserved : AZALIA_HEADER , FSPT_CORE_UPD
  • Reserved2 : FSP_S_CONFIG
  • ReservedCpuPostMemProduction : FSP_S_CONFIG
  • ReservedCpuPostMemTest : FSP_S_TEST_CONFIG
  • ReservedForFuture1 : FSP_S_CONFIG
  • ReservedFspmTestUpd : FSP_M_TEST_CONFIG
  • ReservedFspmUpd : FSP_M_CONFIG
  • ReservedFspmUpdCfl : FSP_M_CONFIG
  • ReservedFspsTestUpd : FSP_S_TEST_CONFIG
  • ReservedFspsUpd : FSP_S_CONFIG
  • ReservedFsptUpd1 : FSP_T_CONFIG
  • ReservedPchPreMem : FSP_M_CONFIG
  • ReservedSecurityPreMem : FSP_M_CONFIG
  • Revision : CHIPSET_INIT_INFO
  • RevisionId : AZALIA_HEADER
  • RhActProbability : FSP_M_CONFIG
  • RhPrevention : FSP_M_CONFIG
  • RhSolution : FSP_M_CONFIG
  • RingDownBin : FSP_M_CONFIG
  • RingMaxOcRatio : FSP_M_CONFIG
  • RingPllVoltageOffset : FSP_M_CONFIG
  • RingVoltageAdaptive : FSP_M_CONFIG
  • RingVoltageMode : FSP_M_CONFIG
  • RingVoltageOffset : FSP_M_CONFIG
  • RingVoltageOverride : FSP_M_CONFIG
  • RMC : FSP_M_CONFIG
  • RMT : FSP_M_CONFIG
  • RMTLoopCount : FSP_M_CONFIG
  • RmtPerTask : FSP_M_CONFIG
  • RootPortIndex : FSP_M_CONFIG
  • Rsvd : CHIPSET_INIT_INFO
  • RsvdBits : GPIO_CONFIG
  • RsvdSmbusAddressTablePtr : FSP_M_CONFIG
  • RTL : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- s -

  • SafeMode : FSP_M_CONFIG
  • SaGv : FSP_M_CONFIG
  • SaIpuEnable : FSP_M_CONFIG
  • SaIpuImrConfiguration : FSP_M_CONFIG
  • SaOcSupport : FSP_M_CONFIG
  • SaPllVoltageOffset : FSP_M_CONFIG
  • SaPostMemProductionRsvd : FSP_S_CONFIG
  • SaPostMemTestRsvd : FSP_S_TEST_CONFIG
  • SaPreMemProductionRsvd : FSP_M_CONFIG
  • SaPreMemTestRsvd : FSP_M_TEST_CONFIG
  • SaRtd3Pcie0Gpio : FSP_M_CONFIG
  • SaRtd3Pcie1Gpio : FSP_M_CONFIG
  • SaRtd3Pcie2Gpio : FSP_M_CONFIG
  • SaRtd3Pcie3Gpio : FSP_M_CONFIG
  • SataEnable : FSP_S_CONFIG
  • SataLedEnable : FSP_S_CONFIG
  • SataMode : FSP_S_CONFIG
  • SataP0T1M : FSP_S_CONFIG
  • SataP0T2M : FSP_S_CONFIG
  • SataP0T3M : FSP_S_CONFIG
  • SataP0TDisp : FSP_S_CONFIG
  • SataP0TDispFinit : FSP_S_CONFIG
  • SataP0Tinact : FSP_S_CONFIG
  • SataP1T1M : FSP_S_CONFIG
  • SataP1T2M : FSP_S_CONFIG
  • SataP1T3M : FSP_S_CONFIG
  • SataP1TDisp : FSP_S_CONFIG
  • SataP1TDispFinit : FSP_S_CONFIG
  • SataP1Tinact : FSP_S_CONFIG
  • SataPortsDevSlp : FSP_S_CONFIG
  • SataPortsDitoVal : FSP_S_CONFIG
  • SataPortsDmVal : FSP_S_CONFIG
  • SataPortsEnable : FSP_S_CONFIG
  • SataPortsEnableDitoConfig : FSP_S_CONFIG
  • SataPortsExternal : FSP_S_CONFIG
  • SataPortsHotPlug : FSP_S_CONFIG
  • SataPortsInterlockSw : FSP_S_CONFIG
  • SataPortsSolidStateDrive : FSP_S_CONFIG
  • SataPortsSpinUp : FSP_S_CONFIG
  • SataPortsZpOdd : FSP_S_CONFIG
  • SataPwrOptEnable : FSP_S_CONFIG
  • SataRstCpuAttachedStorage : FSP_S_CONFIG
  • SataRstHddUnlock : FSP_S_CONFIG
  • SataRstInterrupt : FSP_S_CONFIG
  • SataRstIrrt : FSP_S_CONFIG
  • SataRstIrrtOnly : FSP_S_CONFIG
  • SataRstLedLocate : FSP_S_CONFIG
  • SataRstLegacyOrom : FSP_S_CONFIG
  • SataRstOptaneMemory : FSP_S_CONFIG
  • SataRstOromUiBanner : FSP_S_CONFIG
  • SataRstOromUiDelay : FSP_S_CONFIG
  • SataRstPcieDeviceResetDelay : FSP_S_CONFIG
  • SataRstPcieEnable : FSP_S_CONFIG
  • SataRstPcieStoragePort : FSP_S_CONFIG
  • SataRstRaid0 : FSP_S_CONFIG
  • SataRstRaid1 : FSP_S_CONFIG
  • SataRstRaid10 : FSP_S_CONFIG
  • SataRstRaid5 : FSP_S_CONFIG
  • SataRstRaidDeviceId : FSP_S_CONFIG
  • SataRstSmartStorage : FSP_S_CONFIG
  • SataSalpSupport : FSP_S_CONFIG
  • SataSpeedLimit : FSP_S_CONFIG
  • SataTestMode : FSP_S_TEST_CONFIG
  • SataThermalSuggestedSetting : FSP_S_CONFIG
  • SaVoltageOffset : FSP_M_CONFIG
  • ScanExtGfxForLegacyOpRom : FSP_M_TEST_CONFIG
  • SciIrqSelect : FSP_S_CONFIG
  • ScramblerSupport : FSP_M_CONFIG
  • ScsEmmcEnabled : FSP_S_CONFIG
  • ScsEmmcHs400Enabled : FSP_S_CONFIG
  • ScsSdCardEnabled : FSP_S_CONFIG
  • ScsUfsEnabled : FSP_S_CONFIG
  • SdCardPowerEnableActiveHigh : FSP_S_CONFIG
  • SdiNum : AZALIA_HEADER
  • SecurityTestRsvd : FSP_M_TEST_CONFIG
  • SendDidMsg : FSP_M_TEST_CONFIG
  • SendEcCmd : FSP_S_CONFIG
  • SendVrMbxCmd : FSP_S_CONFIG
  • SerialIoDebugUartNumber : FSP_S_CONFIG
  • SerialIoDevMode : FSP_S_CONFIG
  • SerialIoEnableDebugUartAfterPost : FSP_S_CONFIG
  • SerialIoSpiCsPolarity : FSP_S_CONFIG
  • SerialIoUart0PinMuxing : FSP_S_CONFIG
  • SerialIoUartHwFlowCtrl : FSP_S_CONFIG
  • SevenCoreRatioLimit : FSP_S_TEST_CONFIG
  • SgDelayAfterHoldReset : FSP_M_CONFIG
  • SgDelayAfterPwrEn : FSP_M_CONFIG
  • SgxEpoch0 : FSP_S_CONFIG
  • SgxEpoch1 : FSP_S_CONFIG
  • SgxSinitDataFromTpm : FSP_S_TEST_CONFIG
  • SgxSinitNvsData : FSP_S_CONFIG
  • ShowSpiController : FSP_S_CONFIG
  • SiCsmFlag : FSP_S_CONFIG
  • Signature : FSP_M_TEST_CONFIG , FSP_S_TEST_CONFIG
  • SinitMemorySize : FSP_M_CONFIG
  • SiNumberOfSsidTableEntry : FSP_S_CONFIG
  • SiSsidTablePtr : FSP_S_CONFIG
  • SixCoreRatioLimit : FSP_S_TEST_CONFIG
  • SkipExtGfxScan : FSP_M_TEST_CONFIG
  • SkipMbpHob : FSP_M_TEST_CONFIG
  • SkipMpInit : FSP_M_CONFIG , FSP_S_CONFIG
  • SkipPamLock : FSP_S_TEST_CONFIG
  • SkipPostBootSai : FSP_S_TEST_CONFIG
  • SkipS3CdClockInit : FSP_S_CONFIG
  • SkipStopPbet : FSP_M_CONFIG
  • SlowSlewRateForFivr : FSP_S_CONFIG
  • SlowSlewRateForGt : FSP_S_CONFIG
  • SlowSlewRateForIa : FSP_S_CONFIG
  • SlowSlewRateForSa : FSP_S_CONFIG
  • SlpS0DisQForDebug : FSP_S_CONFIG
  • SlpS0Override : FSP_S_CONFIG
  • SlpS0WithGbeSupport : FSP_S_CONFIG
  • SmbiosData : FIRMWARE_VERSION_INFO_HOB
  • SmbusArpEnable : FSP_M_CONFIG
  • SmbusDynamicPowerGating : FSP_M_TEST_CONFIG
  • SmbusEnable : FSP_M_CONFIG
  • SmbusSpdWriteDisable : FSP_M_TEST_CONFIG
  • SmramMask : FSP_M_CONFIG
  • SocketDesignationStrIndex : SMBIOS_CACHE_INFO
  • SOT : FSP_M_CONFIG
  • SpdAddressTable : FSP_M_CONFIG
  • SpdDramDeviceType : DIMM_INFO
  • SpdModuleMemoryBusWidth : DIMM_INFO
  • SpdModuleType : DIMM_INFO
  • SpdProfileSelected : FSP_M_CONFIG
  • SpdSave : DIMM_INFO
  • Speed : DIMM_INFO
  • SrefCfgEna : FSP_M_CONFIG
  • StateRatio : FSP_S_TEST_CONFIG
  • StateRatioMax16 : FSP_S_TEST_CONFIG
  • Status : DIMM_INFO , SMBIOS_PROCESSOR_INFO
  • SupportedSramType : SMBIOS_CACHE_INFO
  • SystemCacheType : SMBIOS_CACHE_INFO


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- t -

  • TAT : FSP_M_CONFIG
  • TccActivationOffset : FSP_S_TEST_CONFIG
  • TccOffsetClamp : FSP_S_TEST_CONFIG
  • TccOffsetLock : FSP_S_TEST_CONFIG
  • TccOffsetTimeWindowForRatl : FSP_S_TEST_CONFIG
  • tCL : FSP_M_CONFIG
  • TcoIrqEnable : FSP_S_CONFIG
  • TcoIrqSelect : FSP_S_CONFIG
  • tCWL : FSP_M_CONFIG
  • TdcEnable : FSP_S_CONFIG
  • TdcLock : FSP_S_CONFIG
  • TdcPowerLimit : FSP_S_CONFIG
  • TdcTimeWindow : FSP_S_CONFIG
  • TetonGlacierCR : FSP_S_CONFIG
  • TetonGlacierSupport : FSP_S_CONFIG
  • tFAW : FSP_M_CONFIG
  • TgaSize : FSP_M_CONFIG
  • ThermalMonitor : FSP_S_TEST_CONFIG
  • ThreadCount : SMBIOS_PROCESSOR_INFO
  • ThreeCoreRatioLimit : FSP_S_TEST_CONFIG
  • ThreeStrikeCounterDisable : FSP_S_TEST_CONFIG
  • ThrtCkeMinDefeat : FSP_M_CONFIG
  • ThrtCkeMinDefeatLpddr : FSP_M_CONFIG
  • ThrtCkeMinTmr : FSP_M_CONFIG
  • ThrtCkeMinTmrLpddr : FSP_M_CONFIG
  • TimedMwait : FSP_S_TEST_CONFIG
  • TjMaxOffset : FSP_M_CONFIG
  • TotalFlashSize : FSP_M_TEST_CONFIG
  • TraceHubMemBase : FSP_S_CONFIG
  • TrainTrace : FSP_M_CONFIG
  • tRAS : FSP_M_CONFIG
  • tRCDtRP : FSP_M_CONFIG
  • tRd2RdDD : FSP_M_TEST_CONFIG
  • tRd2RdDG : FSP_M_TEST_CONFIG
  • tRd2RdDR : FSP_M_TEST_CONFIG
  • tRd2RdSG : FSP_M_TEST_CONFIG
  • tRd2WrDD : FSP_M_TEST_CONFIG
  • tRd2WrDG : FSP_M_TEST_CONFIG
  • tRd2WrDR : FSP_M_TEST_CONFIG
  • tRd2WrSG : FSP_M_TEST_CONFIG
  • tREFI : FSP_M_CONFIG
  • tRFC : FSP_M_CONFIG
  • tRRD : FSP_M_CONFIG
  • tRRD_L : FSP_M_TEST_CONFIG
  • tRRD_S : FSP_M_TEST_CONFIG
  • tRTP : FSP_M_CONFIG
  • TsegSize : FSP_M_CONFIG
  • TsodAlarmwindowLockBit : FSP_M_CONFIG
  • TsodCriticalEventOnly : FSP_M_CONFIG
  • TsodCriticaltripLockBit : FSP_M_CONFIG
  • TsodEventMode : FSP_M_CONFIG
  • TsodEventOutputControl : FSP_M_CONFIG
  • TsodEventPolarity : FSP_M_CONFIG
  • TsodManualEnable : FSP_M_CONFIG
  • TsodShutdownMode : FSP_M_CONFIG
  • TsodTcritMax : FSP_M_CONFIG
  • TsodThigMax : FSP_M_CONFIG
  • TStates : FSP_S_TEST_CONFIG
  • TTCrossThrottling : FSP_S_CONFIG
  • TTSuggestedSetting : FSP_S_CONFIG
  • TurboMode : FSP_S_CONFIG
  • TurboPowerLimitLock : FSP_S_TEST_CONFIG
  • TvbRatioClipping : FSP_M_CONFIG
  • TvbVoltageOptimization : FSP_M_CONFIG
  • TwoCoreRatioLimit : FSP_S_TEST_CONFIG
  • tWR : FSP_M_CONFIG
  • tWr2RdDD : FSP_M_TEST_CONFIG
  • tWr2RdDG : FSP_M_TEST_CONFIG
  • tWr2RdDR : FSP_M_TEST_CONFIG
  • tWr2RdSG : FSP_M_TEST_CONFIG
  • tWr2WrDD : FSP_M_TEST_CONFIG
  • tWr2WrDG : FSP_M_TEST_CONFIG
  • tWr2WrDR : FSP_M_TEST_CONFIG
  • tWr2WrSG : FSP_M_TEST_CONFIG
  • tWTR : FSP_M_CONFIG
  • tWTR_L : FSP_M_TEST_CONFIG
  • tWTR_S : FSP_M_TEST_CONFIG
  • Txt : FSP_M_CONFIG
  • TxtAcheckRequest : FSP_M_TEST_CONFIG
  • TxtDprMemoryBase : FSP_M_CONFIG
  • TxtDprMemorySize : FSP_M_CONFIG
  • TxtEnable : FSP_S_CONFIG
  • TxtHeapMemorySize : FSP_M_CONFIG
  • TxtImplemented : FSP_M_CONFIG
  • TxtLcpPdBase : FSP_M_CONFIG
  • TxtLcpPdSize : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- u -

  • UnusedUpdSpace0 : FSP_M_CONFIG , FSP_S_CONFIG , FSP_T_CONFIG
  • UnusedUpdSpace1 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace10 : FSP_S_CONFIG
  • UnusedUpdSpace11 : FSP_S_CONFIG
  • UnusedUpdSpace12 : FSP_S_CONFIG
  • UnusedUpdSpace13 : FSP_S_CONFIG
  • UnusedUpdSpace14 : FSP_S_CONFIG
  • UnusedUpdSpace15 : FSP_S_CONFIG
  • UnusedUpdSpace16 : FSP_S_CONFIG
  • UnusedUpdSpace17 : FSP_S_CONFIG
  • UnusedUpdSpace18 : FSP_S_CONFIG
  • UnusedUpdSpace19 : FSP_S_CONFIG
  • UnusedUpdSpace2 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace20 : FSP_S_CONFIG
  • UnusedUpdSpace21 : FSP_S_CONFIG
  • UnusedUpdSpace22 : FSP_S_CONFIG
  • UnusedUpdSpace23 : FSP_S_CONFIG
  • UnusedUpdSpace24 : FSP_S_TEST_CONFIG
  • UnusedUpdSpace3 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace4 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace5 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace6 : FSP_M_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace7 : FSP_S_CONFIG , FSPM_UPD
  • UnusedUpdSpace8 : FSP_M_TEST_CONFIG , FSP_S_CONFIG
  • UnusedUpdSpace9 : FSP_S_CONFIG
  • UpdTerminator : FSPM_UPD , FSPS_UPD , FSPT_UPD
  • Usb2AfePehalfbit : FSP_S_CONFIG
  • Usb2AfePetxiset : FSP_S_CONFIG
  • Usb2AfePredeemp : FSP_S_CONFIG
  • Usb2AfeTxiset : FSP_S_CONFIG
  • Usb2OverCurrentPin : FSP_S_CONFIG
  • Usb3HsioTxDeEmph : FSP_S_CONFIG
  • Usb3HsioTxDeEmphEnable : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmp : FSP_S_CONFIG
  • Usb3HsioTxDownscaleAmpEnable : FSP_S_CONFIG
  • Usb3OverCurrentPin : FSP_S_CONFIG
  • UsbPdoProgramming : FSP_S_CONFIG
  • UserBd : FSP_M_CONFIG
  • UserBudgetEnable : FSP_M_CONFIG
  • UserPowerWeightsEn : FSP_M_CONFIG
  • UserThresholdEnable : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- v -

  • VddVoltage : FSP_M_CONFIG
  • VendorId : AZALIA_HEADER
  • Version : FIRMWARE_VERSION_INFO
  • VersionStringIndex : FIRMWARE_VERSION_INFO
  • VmxEnable : FSP_M_CONFIG
  • Voltage : SMBIOS_PROCESSOR_INFO
  • VoltageOptimization : FSP_S_TEST_CONFIG
  • VrConfigEnable : FSP_S_CONFIG
  • VrPowerDeliveryDesign : FSP_S_CONFIG
  • VrVoltageLimit : FSP_S_CONFIG
  • VtdBaseAddress : FSP_S_CONFIG
  • VtdDisable : FSP_S_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- w -

  • WarmBudgetCh0Dimm0 : FSP_M_CONFIG
  • WarmBudgetCh0Dimm1 : FSP_M_CONFIG
  • WarmBudgetCh1Dimm0 : FSP_M_CONFIG
  • WarmBudgetCh1Dimm1 : FSP_M_CONFIG
  • WarmThresholdCh0Dimm0 : FSP_M_CONFIG
  • WarmThresholdCh0Dimm1 : FSP_M_CONFIG
  • WarmThresholdCh1Dimm0 : FSP_M_CONFIG
  • WarmThresholdCh1Dimm1 : FSP_M_CONFIG
  • WatchDog : FSP_S_CONFIG
  • WatchDogTimerBios : FSP_S_CONFIG
  • WatchDogTimerOs : FSP_S_CONFIG
  • WdtDisableAndLock : FSP_M_TEST_CONFIG
  • WRDSEQT : FSP_M_CONFIG
  • WRDSUDT : FSP_M_CONFIG
  • WrEnergyCh0Dimm0 : FSP_M_CONFIG
  • WrEnergyCh0Dimm1 : FSP_M_CONFIG
  • WrEnergyCh1Dimm0 : FSP_M_CONFIG
  • WrEnergyCh1Dimm1 : FSP_M_CONFIG
  • WRSRT : FSP_M_CONFIG
  • WRTC1D : FSP_M_CONFIG
  • WRTC2D : FSP_M_CONFIG
  • WRVC1D : FSP_M_CONFIG
  • WRVC2D : FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Class Members - Variables

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- x -

  • X2ApicOptOut : FSP_S_CONFIG
  • XdciEnable : FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: File List

  • File List
  • File Members
File List
Here is a list of all documented files with brief descriptions:
FirmwareVersionInfoHob.h | Header file for Firmware Version Information
FspFixedPcds.h | This file lists all FixedAtBuild PCDs referenced in FSP integration guide
FspInfoHob.h | Header file for FSP Information HOB
FspmUpd.h | Copyright (c) 2018, Intel Corporation
FspsUpd.h | Copyright (c) 2018, Intel Corporation
FsptUpd.h | Copyright (c) 2018, Intel Corporation
FspUpd.h | Copyright (c) 2018, Intel Corporation
GpioConfig.h | Header file for GpioConfig structure used by GPIO library
GpioSampleDef.h | Sample enum definitions for GPIO table
HobUsageDataHob.h | Definitions for Hob Usage data HOB
MemInfoHob.h | This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs
SmbiosCacheInfoHob.h | Header file for SMBIOS Cache Info HOB
SmbiosProcessorInfoHob.h | Header file for SMBIOS Processor Info HOB


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FirmwareVersionInfoHob.h File Reference

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  • Include
Classes
FirmwareVersionInfoHob.h File Reference

Header file for Firmware Version Information. More...

#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
Include dependency graph for FirmwareVersionInfoHob.h:

Go to the source code of this file.

Classes

struct | FIRMWARE_VERSION
Firmware Version Structure. More...
struct | FIRMWARE_VERSION_INFO
Firmware Version Information Structure. More...
struct | SMBIOS_STRUCTURE
The Smbios structure header. More...
struct | FIRMWARE_VERSION_INFO_HOB
Firmware Version Information HOB Structure. More...

Detailed Description

Header file for Firmware Version Information.

Copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file FirmwareVersionInfoHob.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspFixedPcds.h File Reference

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Macros
FspFixedPcds.h File Reference

This file lists all FixedAtBuild PCDs referenced in FSP integration guide. More...

Go to the source code of this file.

Macros

#define | PcdFspAreaBaseAddress 0xFFF30000
FspAreaBaseAddress.
#define | PcdFspImageIdString $CFLFSP$
FspImageIdString.
#define | PcdSiliconInitVersionMajor 0x07
SiliconInitVersionMajor.
#define | PcdSiliconInitVersionMinor 0x00
SiliconInitVersionMinor.
#define | PcdSiliconInitVersionRevision 0x3D
SiliconInitVersionRevision.
#define | PcdSiliconInitVersionBuild 0x60
SiliconInitVersionBuild.
#define | PcdGlobalDataPointerAddress 0xFED00148
GlobalDataPointerAddress.
#define | PcdTemporaryRamBase 0xFEF00000
TemporaryRamBase.
#define | PcdTemporaryRamSize 0x00040000
TemporaryRamSize.
#define | PcdFspReservedBufferSize 0x100
FspReservedBufferSize.

Detailed Description

This file lists all FixedAtBuild PCDs referenced in FSP integration guide.

Those value may vary in different FSP revision to meet different requirements.

Definition in file FspFixedPcds.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspInfoHob.h File Reference

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FspInfoHob.h File Reference

Header file for FSP Information HOB. More...

Go to the source code of this file.

Detailed Description

Header file for FSP Information HOB.

Copyright
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Specification Reference:

Definition in file FspInfoHob.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspmUpd.h File Reference

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Classes
FspmUpd.h File Reference

Copyright (c) 2018, Intel Corporation. More...

#include <FspUpd.h>
#include <MemInfoHob.h>
Include dependency graph for FspmUpd.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | CHIPSET_INIT_INFO
The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. More...
struct | FSP_M_CONFIG
Fsp M Configuration. More...
struct | FSP_M_TEST_CONFIG
Fsp M Test Configuration. More...
struct | FSPM_UPD
Fsp M UPD Configuration. More...

Detailed Description

Copyright (c) 2018, Intel Corporation.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FspmUpd.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspsUpd.h File Reference

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FspsUpd.h File Reference

Copyright (c) 2018, Intel Corporation. More...

#include <FspUpd.h>
Include dependency graph for FspsUpd.h:
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Classes

struct | AZALIA_HEADER
Azalia Header structure. More...
struct | AUDIO_AZALIA_VERB_TABLE
Audio Azalia Verb Table structure. More...
struct | SI_PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...
struct | FSP_S_CONFIG
Fsp S Configuration. More...
struct | FSP_S_TEST_CONFIG
Fsp S Test Configuration. More...
struct | FSPS_UPD
Fsp S UPD Configuration. More...

Macros

#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64
Number of all PCH devices.

Enumerations

enum SI_PCH_INT_PIN
Refer to the definition of PCH_INT_PIN. More...

Detailed Description

Copyright (c) 2018, Intel Corporation.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FspsUpd.h.

Enumeration Type Documentation

enum SI_PCH_INT_PIN

Refer to the definition of PCH_INT_PIN.

Enumerator
SiPchNoInt

No Interrupt Pin.

Definition at line 64 of file FspsUpd.h.

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FsptUpd.h File Reference

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FsptUpd.h File Reference

Copyright (c) 2018, Intel Corporation. More...

#include <FspUpd.h>
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Classes

struct | FSPT_CORE_UPD
Fsp T Core UPD. More...
struct | FSP_T_CONFIG
Fsp T Configuration. More...
struct | FSPT_UPD
Fsp T UPD Configuration. More...

Detailed Description

Copyright (c) 2018, Intel Corporation.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FsptUpd.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspUpd.h File Reference

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FspUpd.h File Reference

Copyright (c) 2018, Intel Corporation. More...

#include <FspEas.h>
Include dependency graph for FspUpd.h:
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Detailed Description

Copyright (c) 2018, Intel Corporation.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file FspUpd.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: GpioConfig.h File Reference

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GpioConfig.h File Reference

Header file for GpioConfig structure used by GPIO library. More...

Go to the source code of this file.

Classes

struct GPIO_CONFIG
GPIO configuration structure used for pin programming. More...

Macros

#define | B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F
Mask for GPIO_INT_CONFIG for interrupt source.
#define | B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0
Mask for GPIO_INT_CONFIG for interrupt type.
#define | B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F
Mask for GPIO_ELECTRICAL_CONFIG for termination value.
#define | B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3
Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock.
#define | B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC
Mask for GPIO_LOCK_CONFIG for Pad Output Lock.
#define | B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3
Mask for GPIO_OTHER_CONFIG for RxRaw1 setting.

Typedefs

typedef UINT32 | GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
typedef UINT32 | GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.

Enumerations

enum | GPIO_HARDWARE_DEFAULT
enum | GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad. More...
enum | GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers. More...
enum | GPIO_DIRECTION
GPIO Direction. More...
enum | GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled. More...
enum | GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled. More...
enum | GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings. More...
enum | GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Configuration options for GPIO termination setting. More...
enum | GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock. More...
enum | GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings: More...

Detailed Description

Header file for GpioConfig structure used by GPIO library.

Copyright
Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:

Definition in file GpioConfig.h.

Enumeration Type Documentation

enum GPIO_DIRECTION

GPIO Direction.

Enumerator
GpioDirDefault | Leave pad direction setting unmodified.
GpioDirInOut | Set pad for both output and input.
GpioDirInInvOut | Set pad for both output and input with inversion.
GpioDirIn | Set pad for input only.
GpioDirInInv | Set pad for input with inversion.
GpioDirOut | Set pad for output only.
GpioDirNone | Disable both output and input.

Definition at line 149 of file GpioConfig.h.

enum GPIO_ELECTRICAL_CONFIG

GPIO Electrical Configuration Configuration options for GPIO termination setting.

Enumerator
GpioTermDefault | Leave termination setting unmodified.
GpioTermNone | none
GpioTermWpd5K | 5kOhm weak pull-down
GpioTermWpd20K | 20kOhm weak pull-down
GpioTermWpu1K | 1kOhm weak pull-up
GpioTermWpu2K | 2kOhm weak pull-up
GpioTermWpu5K | 5kOhm weak pull-up
GpioTermWpu20K | 20kOhm weak pull-up
GpioTermWpu1K2K | 1kOhm & 2kOhm weak pull-up
GpioTermNative | Native function controls pads termination This setting is applicable only to some native modes. Please check EDS to determine which native functionality can control pads termination

Definition at line 264 of file GpioConfig.h.

enum GPIO_HARDWARE_DEFAULT
Enumerator
GpioHardwareDefault

Leave setting unmodified.

Definition at line 99 of file GpioConfig.h.

enum GPIO_HOSTSW_OWN

Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.

Depending on chosen ownership some GPIO Interrupt status register get updated and other masked. Please refer to EDS for HOSTSW_OWN register description.

Enumerator
GpioHostOwnDefault | Leave ownership value unmodified.
GpioHostOwnAcpi | Set HOST ownership to ACPI. Use this setting if pad is not going to be used by GPIO OS driver. If GPIO is configured to generate SCI/SMI/NMI then this setting must be used for interrupts to work
GpioHostOwnGpio | Set HOST ownership to GPIO Driver mode. Use this setting only if GPIO pad should be controlled by GPIO OS Driver. GPIO OS Driver will be able to control the pad if appropriate entry in ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)

Definition at line 128 of file GpioConfig.h.

enum GPIO_INT_CONFIG

GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled.

GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in EDS for details on this settings. Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge to describe an interrupt e.g. GpioIntApic | GpioIntLevel If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. Not all GPIO are capable of generating an SMI or NMI interrupt. When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this interrupt cannot be shared and its IRQn number is not configurable. Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). This type of GPIO Driver interrupt doesn't have any additional routing setting required to be set by BIOS. Interrupt is handled by GPIO OS Driver.

Enumerator
GpioIntDefault | Leave value of interrupt routing unmodified.
GpioIntDis | Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
GpioIntNmi | Enable NMI interrupt only.
GpioIntSmi | Enable SMI interrupt only.
GpioIntSci | Enable SCI interrupt only.
GpioIntApic | Enable IOxAPIC interrupt only.
GpioIntLevel | Set interrupt as level triggered.
GpioIntEdge | Set interrupt as edge triggered (type of edge depends on input inversion)
GpioIntLvlEdgDis | Disable interrupt trigger.
GpioIntBothEdge | Set interrupt as both edge triggered.

Definition at line 189 of file GpioConfig.h.

enum GPIO_LOCK_CONFIG

GPIO LockConfiguration Set GPIO configuration lock and output state lock.

GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. By default GPIO pads will be locked unless GPIO lib is explicitly informed that certain pad is to be left unlocked. Lock settings reset is in Powergood domain. Care must be taken when using this setting as fields it locks may be reset by a different signal and can be controlled by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock an already locked pad upon request for reconfiguration

Enumerator
GpioLockDefault

Perform default action.

  • if pad is an GPO, lock configuration but leave output unlocked
  • if pad is an GPI, lock everything
  • if pad is in native, lock everything
GpioPadConfigUnlock

Leave Pad configuration unlocked.

GpioPadConfigLock

Lock Pad configuration.

GpioOutputStateUnlock

Leave Pad output control unlocked.

GpioPadUnlock

Leave both Pad configuration and output control unlocked.

GpioPadLock

Lock both Pad configuration and output control.

Definition at line 297 of file GpioConfig.h.

enum GPIO_OTHER_CONFIG

Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings:

  • RX raw override to '1' - allows to override input value to '1' This setting is applicable only if in input mode (both in GPIO and native usage). The override takes place at the internal pad state directly from buffer and before the RXINV.
Enumerator
GpioRxRaw1Default | Use default input override value.
GpioRxRaw1Dis | Don't override input.
GpioRxRaw1En | Override input to '1'.

Definition at line 323 of file GpioConfig.h.

enum GPIO_OUTPUT_STATE

GPIO Output State This field is relevant only if output is enabled.

Enumerator
GpioOutDefault | Leave output value unmodified.
GpioOutLow | Set output to low.
GpioOutHigh | Set output to high.

Definition at line 163 of file GpioConfig.h.

enum GPIO_PAD_MODE

GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.

If GPIO is set to one of NativeX modes then following settings are not applicable and can be skipped:

  • Interrupt related settings
  • Host Software Ownership
  • Output/Input enabling/disabling
  • Output lock

Definition at line 113 of file GpioConfig.h.

enum GPIO_RESET_CONFIG

GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings.

Refer to EDS for settings that are controllable by PadRstCfg.

Enumerator
GpioResetDefault

Leave value of pad reset unmodified.

GpioResumeReset

Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad setting will reset on:

  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
GpioHostDeepReset

Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:

  • Warm/Cold/Global reset
  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
GpioPlatformReset

Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:

  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition
  • G3
GpioDswReset

Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings will reset on:

  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition

Definition at line 211 of file GpioConfig.h.

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: GpioSampleDef.h File Reference

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GpioSampleDef.h File Reference

Sample enum definitions for GPIO table. More...

#include <FsptUpd.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
Include dependency graph for GpioSampleDef.h:

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Detailed Description

Sample enum definitions for GPIO table.

Copyright
Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Specification Reference:

Definition in file GpioSampleDef.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: HobUsageDataHob.h File Reference

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HobUsageDataHob.h File Reference

Definitions for Hob Usage data HOB. More...

Go to the source code of this file.

Classes

struct HOB_USAGE_DATA_HOB
Hob Usage Data Hob. More...

Detailed Description

Definitions for Hob Usage data HOB.

Copyright
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:

Definition in file HobUsageDataHob.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: MemInfoHob.h File Reference

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MemInfoHob.h File Reference

This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs. More...

#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
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Classes

struct | DIMM_INFO
Memory SMBIOS & OC Memory Data Hob. More...
struct | MEMORY_PLATFORM_DATA
Memory Platform Data Hob. More...

Macros

#define | WARM_BOOT 2
Host reset states from MRC.
#define | MAX_SPD_SAVE 29
Defines taken from MRC so avoid having to include MrcInterface.h.

Detailed Description

This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs.

Copyright
Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:

Definition in file MemInfoHob.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SmbiosCacheInfoHob.h File Reference

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SmbiosCacheInfoHob.h File Reference

Header file for SMBIOS Cache Info HOB. More...

#include <Uefi.h>
#include <Pi/PiHob.h>
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Classes

struct SMBIOS_CACHE_INFO
SMBIOS Cache Info HOB Structure. More...

Detailed Description

Header file for SMBIOS Cache Info HOB.

Copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

System Management BIOS (SMBIOS) Reference Specification v3.1.0 dated 2016-Nov-16 (DSP0134) http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf

Definition in file SmbiosCacheInfoHob.h.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SmbiosProcessorInfoHob.h File Reference

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SmbiosProcessorInfoHob.h File Reference

Header file for SMBIOS Processor Info HOB. More...

#include <Uefi.h>
#include <Pi/PiHob.h>
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Classes

struct SMBIOS_PROCESSOR_INFO
SMBIOS Processor Info HOB Structure. More...

Detailed Description

Header file for SMBIOS Processor Info HOB.

Copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

System Management BIOS (SMBIOS) Reference Specification v3.1.0 dated 2016-Nov-16 (DSP0134) http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf

Definition in file SmbiosProcessorInfoHob.h.

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

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  • All
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • b
  • g
  • m
  • p
  • s
  • w
Here is a list of all documented file members with links to the documentation:

- b -

  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h

- g -

  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_GROUP : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateUnlock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPadConfigUnlock : GpioConfig.h
  • GpioPadLock : GpioConfig.h
  • GpioPadUnlock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h

- m -

  • MAX_SPD_SAVE : MemInfoHob.h

- p -

  • PcdFspAreaBaseAddress : FspFixedPcds.h
  • PcdFspImageIdString : FspFixedPcds.h
  • PcdFspReservedBufferSize : FspFixedPcds.h
  • PcdGlobalDataPointerAddress : FspFixedPcds.h
  • PcdSiliconInitVersionBuild : FspFixedPcds.h
  • PcdSiliconInitVersionMajor : FspFixedPcds.h
  • PcdSiliconInitVersionMinor : FspFixedPcds.h
  • PcdSiliconInitVersionRevision : FspFixedPcds.h
  • PcdTemporaryRamBase : FspFixedPcds.h
  • PcdTemporaryRamSize : FspFixedPcds.h

- s -

  • SI_PCH_INT_PIN : FspsUpd.h
  • SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG : FspsUpd.h
  • SiPchNoInt : FspsUpd.h

- w -

  • WARM_BOOT : MemInfoHob.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

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  • Typedefs
  • Enumerations
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  • GPIO_GROUP : GpioConfig.h
  • GPIO_PAD : GpioConfig.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

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  • Typedefs
  • Enumerations
  • Enumerator
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  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • SI_PCH_INT_PIN : FspsUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

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  • g
  • s

- g -

  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateUnlock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPadConfigUnlock : GpioConfig.h
  • GpioPadLock : GpioConfig.h
  • GpioPadUnlock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h

- s -

  • SiPchNoInt : FspsUpd.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: File Members

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  • Enumerations
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  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • MAX_SPD_SAVE : MemInfoHob.h
  • PcdFspAreaBaseAddress : FspFixedPcds.h
  • PcdFspImageIdString : FspFixedPcds.h
  • PcdFspReservedBufferSize : FspFixedPcds.h
  • PcdGlobalDataPointerAddress : FspFixedPcds.h
  • PcdSiliconInitVersionBuild : FspFixedPcds.h
  • PcdSiliconInitVersionMajor : FspFixedPcds.h
  • PcdSiliconInitVersionMinor : FspFixedPcds.h
  • PcdSiliconInitVersionRevision : FspFixedPcds.h
  • PcdTemporaryRamBase : FspFixedPcds.h
  • PcdTemporaryRamSize : FspFixedPcds.h
  • SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG : FspsUpd.h
  • WARM_BOOT : MemInfoHob.h


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FirmwareVersionInfoHob.h Source File

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FirmwareVersionInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for Firmware Version Information
3
4 @copyright
5 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
6
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License which accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _FIRMWARE_VERSION_INFO_HOB_H_
18 #define _FIRMWARE_VERSION_INFO_HOB_H_
19
20 #include <Uefi/UefiMultiPhase.h>
21 #include <Pi/PiBootMode.h>
22 #include <Pi/PiHob.h>
23
24 #pragma pack(1)
25 ///
26 /// Firmware Version Structure
27 ///
28 typedef struct {
29 UINT8 MajorVersion;
30 UINT8 MinorVersion;
31 UINT8 Revision;
32 UINT16 BuildNumber;
33 } FIRMWARE_VERSION;
34
35 ///
36 /// Firmware Version Information Structure
37 ///
38 typedef struct {
39 UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
40 UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
41 FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
42 } FIRMWARE_VERSION_INFO;
43
44 #ifndef __SMBIOS_STANDARD_H__
45 ///
46 /// The Smbios structure header.
47 ///
48 typedef struct {
49 UINT8 Type;
50 UINT8 Length;
51 UINT16 Handle;
52 } SMBIOS_STRUCTURE;
53 #endif
54
55 ///
56 /// Firmware Version Information HOB Structure
57 ///
58 typedef struct {
59 EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
60 SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
61 UINT8 Count; ///< Offset 28 Number of FVI elements included.
62 ///
63 /// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
64 ///
65 } FIRMWARE_VERSION_INFO_HOB;
66 #pragma pack()
67
68 #endif // _FIRMWARE_VERSION_INFO_HOB_H_
FIRMWARE_VERSION_INFO_HOB::Count
UINT8 Count
Offset 28 Number of FVI elements included.
Definition: FirmwareVersionInfoHob.h:61
FIRMWARE_VERSION_INFO
Firmware Version Information Structure.
Definition: FirmwareVersionInfoHob.h:38
FIRMWARE_VERSION
Firmware Version Structure.
Definition: FirmwareVersionInfoHob.h:28
SMBIOS_STRUCTURE
The Smbios structure header.
Definition: FirmwareVersionInfoHob.h:48
FIRMWARE_VERSION_INFO_HOB::Header
EFI_HOB_GUID_TYPE Header
Offset 0-23 The header of FVI HOB.
Definition: FirmwareVersionInfoHob.h:59
FIRMWARE_VERSION_INFO::VersionStringIndex
UINT8 VersionStringIndex
Offset 1 Index of Version String.
Definition: FirmwareVersionInfoHob.h:40
FIRMWARE_VERSION_INFO::ComponentNameIndex
UINT8 ComponentNameIndex
Offset 0 Index of Component Name.
Definition: FirmwareVersionInfoHob.h:39
FIRMWARE_VERSION_INFO::Version
FIRMWARE_VERSION Version
Offset 2-6 Firmware version.
Definition: FirmwareVersionInfoHob.h:41
FIRMWARE_VERSION_INFO_HOB::SmbiosData
SMBIOS_STRUCTURE SmbiosData
Offset 24-27 The SMBIOS header of FVI HOB.
Definition: FirmwareVersionInfoHob.h:60
FIRMWARE_VERSION_INFO_HOB
Firmware Version Information HOB Structure.
Definition: FirmwareVersionInfoHob.h:58
Generated on Wed Aug 22 2018 17:48:54 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspFixedPcds.h Source File

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FspFixedPcds.h
Go to the documentation of this file.
1 /** @file
2
3 This file lists all FixedAtBuild PCDs referenced in FSP integration guide.
4 Those value may vary in different FSP revision to meet different requirements.
5
6 **/
7
8 #ifndef __FSPFIXEDPCDS_H__
9 #define __FSPFIXEDPCDS_H__
10
11 #pragma pack(1)
12
13 #define PcdFspAreaBaseAddress 0xFFF30000 ///< FspAreaBaseAddress
14 #define PcdFspImageIdString $CFLFSP$ ///< FspImageIdString
15 #define PcdSiliconInitVersionMajor 0x07 ///< SiliconInitVersionMajor
16 #define PcdSiliconInitVersionMinor 0x00 ///< SiliconInitVersionMinor
17 #define PcdSiliconInitVersionRevision 0x3D ///< SiliconInitVersionRevision
18 #define PcdSiliconInitVersionBuild 0x60 ///< SiliconInitVersionBuild
19 #define PcdGlobalDataPointerAddress 0xFED00148 ///< GlobalDataPointerAddress
20 #define PcdTemporaryRamBase 0xFEF00000 ///< TemporaryRamBase
21 #define PcdTemporaryRamSize 0x00040000 ///< TemporaryRamSize
22 #define PcdFspReservedBufferSize 0x100 ///< FspReservedBufferSize
23 #pragma pack()
24
25 #endif
Generated on Wed Aug 22 2018 17:48:54 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspInfoHob.h Source File

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FspInfoHob.h
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1 /** @file
2 Header file for FSP Information HOB.
3
4 @copyright
5 Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 @par Specification Reference:
14 **/
15
16 #ifndef _FSP_INFO_HOB_H_
17 #define _FSP_INFO_HOB_H_
18
19 extern EFI_GUID gFspInfoGuid;
20
21 #pragma pack (push, 1)
22
23 typedef struct {
24 UINT8 SiliconInitVersionMajor;
25 UINT8 SiliconInitVersionMinor;
26 UINT8 SiliconInitVersionRevision;
27 UINT8 SiliconInitVersionBuild;
28 UINT8 FspVersionRevision;
29 UINT8 FspVersionBuild;
30 UINT8 TimeStamp [12];
31 } FSP_INFO_HOB;
32
33 #pragma pack (pop)
34
35 #endif // _FSP_INFO_HOB_H_
Generated on Wed Aug 22 2018 17:48:54 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspUpd.h Source File

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FspUpd.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31 **/
32
33 #ifndef __FSPUPD_H__
34 #define __FSPUPD_H__
35
36 #include <FspEas.h>
37
38 #pragma pack(1)
39
40 #define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */
41
42 #define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */
43
44 #define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */
45
46 #pragma pack()
47
48 #endif
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspmUpd.h Source File

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FspmUpd.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31 **/
32
33 #ifndef __FSPMUPD_H__
34 #define __FSPMUPD_H__
35
36 #include <FspUpd.h>
37
38 #pragma pack(1)
39
40
41 #include <MemInfoHob.h>
42
43 ///
44 /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
45 ///
46 typedef struct {
47 UINT8 Revision; ///< Chipset Init Info Revision
48 UINT8 Rsvd[3]; ///< Reserved
49 UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
50 UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
51 } CHIPSET_INIT_INFO;
52
53
54 /** Fsp M Configuration
55 **/
56 typedef struct {
57
58 /** Offset 0x0040 - Platform Reserved Memory Size
59 The minimum platform memory size required to pass control into DXE
60 **/
61 UINT64 PlatformMemorySize;
62
63 /** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0
64 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
65 **/
66 UINT32 MemorySpdPtr00;
67
68 /** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1
69 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
70 **/
71 UINT32 MemorySpdPtr01;
72
73 /** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0
74 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
75 **/
76 UINT32 MemorySpdPtr10;
77
78 /** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1
79 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
80 **/
81 UINT32 MemorySpdPtr11;
82
83 /** Offset 0x0058 - SPD Data Length
84 Length of SPD Data
85 0x100:256 Bytes, 0x200:512 Bytes
86 **/
87 UINT16 MemorySpdDataLen;
88
89 /** Offset 0x005A - Dq Byte Map CH0
90 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
91 **/
92 UINT8 DqByteMapCh0[12];
93
94 /** Offset 0x0066 - Dq Byte Map CH1
95 Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
96 **/
97 UINT8 DqByteMapCh1[12];
98
99 /** Offset 0x0072 - Dqs Map CPU to DRAM CH 0
100 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
101 **/
102 UINT8 DqsMapCpu2DramCh0[8];
103
104 /** Offset 0x007A - Dqs Map CPU to DRAM CH 1
105 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
106 **/
107 UINT8 DqsMapCpu2DramCh1[8];
108
109 /** Offset 0x0082 - RcompResister settings
110 Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design
111 Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide
112 the appropriate values.
113 **/
114 UINT16 RcompResistor[3];
115
116 /** Offset 0x0088 - RcompTarget settings
117 RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines,
118 otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values.
119 **/
120 UINT16 RcompTarget[5];
121
122 /** Offset 0x0092 - Dqs Pins Interleaved Setting
123 Indicates DqPinsInterleaved setting: board-dependent
124 $EN_DIS
125 **/
126 UINT8 DqPinsInterleaved;
127
128 /** Offset 0x0093 - VREF_CA
129 CA Vref routing: board-dependent
130 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
131 2:VREF_CA to CH_A and VREF_DQ_B to CH_B
132 **/
133 UINT8 CaVrefConfig;
134
135 /** Offset 0x0094 - Smram Mask
136 The SMM Regions AB-SEG and/or H-SEG reserved
137 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
138 **/
139 UINT8 SmramMask;
140
141 /** Offset 0x0095 - MRC Fast Boot
142 Enables/Disable the MRC fast path thru the MRC
143 $EN_DIS
144 **/
145 UINT8 MrcFastBoot;
146
147 /** Offset 0x0096 - Rank Margin Tool per Task
148 This option enables the user to execute Rank Margin Tool per major training step
149 in the MRC.
150 $EN_DIS
151 **/
152 UINT8 RmtPerTask;
153
154 /** Offset 0x0097 - Training Trace
155 This option enables the trained state tracing feature in MRC. This feature will
156 print out the key training parameters state across major training steps.
157 $EN_DIS
158 **/
159 UINT8 TrainTrace;
160
161 /** Offset 0x0098 - Intel Enhanced Debug
162 Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
163 0 : Disable, 0x400000 : Enable
164 **/
165 UINT32 IedSize;
166
167 /** Offset 0x009C - Tseg Size
168 Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
169 0x0400000:4MB, 0x01000000:16MB
170 **/
171 UINT32 TsegSize;
172
173 /** Offset 0x00A0 - MMIO Size
174 Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
175 **/
176 UINT16 MmioSize;
177
178 /** Offset 0x00A2 - Probeless Trace
179 Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
180 This also requires IED to be enabled.
181 $EN_DIS
182 **/
183 UINT8 ProbelessTrace;
184
185 /** Offset 0x00A3 - GDXC IOT SIZE
186 Size of IOT and MOT is in 8 MB chunks
187 **/
188 UINT8 GdxcIotSize;
189
190 /** Offset 0x00A4 - GDXC MOT SIZE
191 Size of IOT and MOT is in 8 MB chunks
192 **/
193 UINT8 GdxcMotSize;
194
195 /** Offset 0x00A5 - Enable SMBus
196 Enable/disable SMBus controller.
197 $EN_DIS
198 **/
199 UINT8 SmbusEnable;
200
201 /** Offset 0x00A6 - Spd Address Tabl
202 Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
203 if SPD Address is 00
204 **/
205 UINT8 SpdAddressTable[4];
206
207 /** Offset 0x00AA - Platform Debug Consent
208 To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
209 Enabling this BIOS option may alter the default value of other debug-related BIOS
210 options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]
211 have the same setting
212 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
213 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)
214 **/
215 UINT8 PlatformDebugConsent;
216
217 /** Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
218 This BIOS option enables kernel and platform debug for USB3 interface over a UFP
219 Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
220 0:Disabled, 1:Enabled, 2:No Change
221 **/
222 UINT8 DciUsb3TypecUfpDbg;
223
224 /** Offset 0x00AC - PCH Trace Hub Mode
225 Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
226 if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
227 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
228 **/
229 UINT8 PchTraceHubMode;
230
231 /** Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size
232 Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
233 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
234 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
235 **/
236 UINT8 PchTraceHubMemReg0Size;
237
238 /** Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size
239 Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
240 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
241 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
242 **/
243 UINT8 PchTraceHubMemReg1Size;
244
245 /** Offset 0x00AF - PchPreMemRsvd
246 Reserved for PCH Pre-Mem Reserved
247 $EN_DIS
248 **/
249 UINT8 PchPreMemRsvd[9];
250
251 /** Offset 0x00B8 - Internal Graphics Pre-allocated Memory
252 Size of memory preallocated for internal graphics.
253 0x00:0 MB, 0x01:32 MB, 0x02:64 MB
254 **/
255 UINT8 IgdDvmt50PreAlloc;
256
257 /** Offset 0x00B9 - Internal Graphics
258 Enable/disable internal graphics.
259 $EN_DIS
260 **/
261 UINT8 InternalGfx;
262
263 /** Offset 0x00BA - Aperture Size
264 Select the Aperture Size.
265 0:128 MB, 1:256 MB, 2:512 MB
266 **/
267 UINT8 ApertureSize;
268
269 /** Offset 0x00BB - Board Type
270 MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
271 Halo, 7=UP Server
272 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
273 **/
274 UINT8 UserBd;
275
276 /** Offset 0x00BC - SA GV
277 System Agent dynamic frequency support and when enabled memory will be training
278 at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
279 2=FixedHigh, and 3=Enabled.
280 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
281 **/
282 UINT8 SaGv;
283
284 /** Offset 0x00BD
285 **/
286 UINT8 UnusedUpdSpace0;
287
288 /** Offset 0x00BE - DDR Frequency Limit
289 Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
290 i.e. divide by 133 or 100
291 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133,
292 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto
293 **/
294 UINT16 DdrFreqLimit;
295
296 /** Offset 0x00C0 - Low Frequency
297 SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
298 2400, 2667, 2933 and 0 for Auto.
299 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
300 **/
301 UINT16 FreqSaGvLow;
302
303 /** Offset 0x00C2 - Mid Frequency
304 SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
305 2400, 2667, 2933 and 0 for Auto.
306 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
307 **/
308 UINT16 FreqSaGvMid;
309
310 /** Offset 0x00C4 - Rank Margin Tool
311 Enable/disable Rank Margin Tool.
312 $EN_DIS
313 **/
314 UINT8 RMT;
315
316 /** Offset 0x00C5 - Channel A DIMM Control
317 Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
318 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
319 **/
320 UINT8 DisableDimmChannel0;
321
322 /** Offset 0x00C6 - Channel B DIMM Control
323 Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
324 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
325 **/
326 UINT8 DisableDimmChannel1;
327
328 /** Offset 0x00C7 - Scrambler Support
329 This option enables data scrambling in memory.
330 $EN_DIS
331 **/
332 UINT8 ScramblerSupport;
333
334 /** Offset 0x00C8 - Skip Multi-Processor Initialization
335 When this is skipped, boot loader must initialize processors before SilicionInit
336 API. </b>0: Initialize; <b>1: Skip
337 $EN_DIS
338 **/
339 UINT8 SkipMpInit;
340
341 /** Offset 0x00C9
342 **/
343 UINT8 UnusedUpdSpace1[15];
344
345 /** Offset 0x00D8 - SPD Profile Selected
346 Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
347 Profile 1, 3=XMP Profile 2
348 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
349 **/
350 UINT8 SpdProfileSelected;
351
352 /** Offset 0x00D9 - Memory Reference Clock
353 100MHz, 133MHz.
354 0:133MHz, 1:100MHz
355 **/
356 UINT8 RefClk;
357
358 /** Offset 0x00DA - Memory Voltage
359 Memory Voltage Override (Vddq). Default = no override
360 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
361 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
362 **/
363 UINT16 VddVoltage;
364
365 /** Offset 0x00DC - Memory Ratio
366 Automatic or the frequency will equal ratio times reference clock. Set to Auto to
367 recalculate memory timings listed below.
368 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
369 **/
370 UINT8 Ratio;
371
372 /** Offset 0x00DD - QCLK Odd Ratio
373 Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
374 $EN_DIS
375 **/
376 UINT8 OddRatioMode;
377
378 /** Offset 0x00DE - tCL
379 CAS Latency, 0: AUTO, max: 31
380 **/
381 UINT8 tCL;
382
383 /** Offset 0x00DF - tCWL
384 Min CAS Write Latency Delay Time, 0: AUTO, max: 34
385 **/
386 UINT8 tCWL;
387
388 /** Offset 0x00E0 - tRCD/tRP
389 RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
390 **/
391 UINT8 tRCDtRP;
392
393 /** Offset 0x00E1 - tRRD
394 Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
395 **/
396 UINT8 tRRD;
397
398 /** Offset 0x00E2 - tFAW
399 Min Four Activate Window Delay Time, 0: AUTO, max: 63
400 **/
401 UINT16 tFAW;
402
403 /** Offset 0x00E4 - tRAS
404 RAS Active Time, 0: AUTO, max: 64
405 **/
406 UINT16 tRAS;
407
408 /** Offset 0x00E6 - tREFI
409 Refresh Interval, 0: AUTO, max: 65535
410 **/
411 UINT16 tREFI;
412
413 /** Offset 0x00E8 - tRFC
414 Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
415 **/
416 UINT16 tRFC;
417
418 /** Offset 0x00EA - tRTP
419 Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
420 values: 5, 6, 7, 8, 9, 10, 12
421 **/
422 UINT8 tRTP;
423
424 /** Offset 0x00EB - tWR
425 Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
426 20, 24, 30, 34, 40
427 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
428 34:34, 40:40
429 **/
430 UINT8 tWR;
431
432 /** Offset 0x00EC - tWTR
433 Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
434 **/
435 UINT8 tWTR;
436
437 /** Offset 0x00ED - NMode
438 System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
439 **/
440 UINT8 NModeSupport;
441
442 /** Offset 0x00EE - DllBwEn[0]
443 DllBwEn[0], for 1067 (0..7)
444 **/
445 UINT8 DllBwEn0;
446
447 /** Offset 0x00EF - DllBwEn[1]
448 DllBwEn[1], for 1333 (0..7)
449 **/
450 UINT8 DllBwEn1;
451
452 /** Offset 0x00F0 - DllBwEn[2]
453 DllBwEn[2], for 1600 (0..7)
454 **/
455 UINT8 DllBwEn2;
456
457 /** Offset 0x00F1 - DllBwEn[3]
458 DllBwEn[3], for 1867 and up (0..7)
459 **/
460 UINT8 DllBwEn3;
461
462 /** Offset 0x00F2 - ISVT IO Port Address
463 ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
464 **/
465 UINT8 IsvtIoPort;
466
467 /** Offset 0x00F3 - CPU Trace Hub Mode
468 Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable'
469 trace hub functionality.
470 0: Disable, 1:Target Debugger Mode
471 **/
472 UINT8 CpuTraceHubMode;
473
474 /** Offset 0x00F4 - CPU Trace Hub Memory Region 0
475 CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
476 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
477 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
478 **/
479 UINT8 CpuTraceHubMemReg0Size;
480
481 /** Offset 0x00F5 - CPU Trace Hub Memory Region 1
482 CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
483 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
484 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
485 **/
486 UINT8 CpuTraceHubMemReg1Size;
487
488 /** Offset 0x00F6 - Enable or Disable Peci C10 Reset command
489 Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message
490 to disable peci reset on C10 exit. The default value is <b>0: Disable</b> for CNL,
491 and <b>1: Enable</b> for all other CPU's
492 $EN_DIS
493 **/
494 UINT8 PeciC10Reset;
495
496 /** Offset 0x00F7 - Enable or Disable Peci Sx Reset command
497 Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
498 $EN_DIS
499 **/
500 UINT8 PeciSxReset;
501
502 /** Offset 0x00F8
503 **/
504 UINT8 UnusedUpdSpace2[4];
505
506 /** Offset 0x00FC - Enable Intel HD Audio (Azalia)
507 0: Disable, 1: Enable (Default) Azalia controller
508 $EN_DIS
509 **/
510 UINT8 PchHdaEnable;
511
512 /** Offset 0x00FD - Enable PCH ISH Controller
513 0: Disable, 1: Enable (Default) ISH Controller
514 $EN_DIS
515 **/
516 UINT8 PchIshEnable;
517
518 /** Offset 0x00FE - HECI Timeouts
519 0: Disable, 1: Enable (Default) timeout check for HECI
520 $EN_DIS
521 **/
522 UINT8 HeciTimeouts;
523
524 /** Offset 0x00FF
525 **/
526 UINT8 UnusedUpdSpace3;
527
528 /** Offset 0x0100 - HECI1 BAR address
529 BAR address of HECI1
530 **/
531 UINT32 Heci1BarAddress;
532
533 /** Offset 0x0104 - HECI2 BAR address
534 BAR address of HECI2
535 **/
536 UINT32 Heci2BarAddress;
537
538 /** Offset 0x0108 - HECI3 BAR address
539 BAR address of HECI3
540 **/
541 UINT32 Heci3BarAddress;
542
543 /** Offset 0x010C - SG dGPU Power Delay
544 SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
545 300=300 microseconds
546 **/
547 UINT16 SgDelayAfterPwrEn;
548
549 /** Offset 0x010E - SG dGPU Reset Delay
550 SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
551 microseconds
552 **/
553 UINT16 SgDelayAfterHoldReset;
554
555 /** Offset 0x0110 - MMIO size adjustment for AUTO mode
556 Positive number means increasing MMIO size, Negative value means decreasing MMIO
557 size: 0 (Default)=no change to AUTO mode MMIO size
558 **/
559 UINT16 MmioSizeAdjustment;
560
561 /** Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
562 Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
563 Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
564 $EN_DIS
565 **/
566 UINT8 DmiGen3ProgramStaticEq;
567
568 /** Offset 0x0113 - Enable/Disable PEG 0
569 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
570 it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
571 0:Disable, 1:Enable, 2:AUTO
572 **/
573 UINT8 Peg0Enable;
574
575 /** Offset 0x0114 - Enable/Disable PEG 1
576 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
577 it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
578 0:Disable, 1:Enable, 2:AUTO
579 **/
580 UINT8 Peg1Enable;
581
582 /** Offset 0x0115 - Enable/Disable PEG 2
583 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
584 it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
585 0:Disable, 1:Enable, 2:AUTO
586 **/
587 UINT8 Peg2Enable;
588
589 /** Offset 0x0116 - Enable/Disable PEG 3
590 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
591 it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
592 0:Disable, 1:Enable, 2:AUTO
593 **/
594 UINT8 Peg3Enable;
595
596 /** Offset 0x0117 - PEG 0 Max Link Speed
597 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
598 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
599 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
600 **/
601 UINT8 Peg0MaxLinkSpeed;
602
603 /** Offset 0x0118 - PEG 1 Max Link Speed
604 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
605 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
606 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
607 **/
608 UINT8 Peg1MaxLinkSpeed;
609
610 /** Offset 0x0119 - PEG 2 Max Link Speed
611 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
612 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
613 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
614 **/
615 UINT8 Peg2MaxLinkSpeed;
616
617 /** Offset 0x011A - PEG 3 Max Link Speed
618 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
619 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
620 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
621 **/
622 UINT8 Peg3MaxLinkSpeed;
623
624 /** Offset 0x011B - PEG 0 Max Link Width
625 Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
626 Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
627 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
628 **/
629 UINT8 Peg0MaxLinkWidth;
630
631 /** Offset 0x011C - PEG 1 Max Link Width
632 Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
633 Limit Link to x2, (0x3):Limit Link to x4
634 0:Auto, 1:x1, 2:x2, 3:x4
635 **/
636 UINT8 Peg1MaxLinkWidth;
637
638 /** Offset 0x011D - PEG 2 Max Link Width
639 Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
640 Limit Link to x2
641 0:Auto, 1:x1, 2:x2
642 **/
643 UINT8 Peg2MaxLinkWidth;
644
645 /** Offset 0x011E - PEG 3 Max Link Width
646 Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
647 Limit Link to x2
648 0:Auto, 1:x1, 2:x2
649 **/
650 UINT8 Peg3MaxLinkWidth;
651
652 /** Offset 0x011F - Power down unused lanes on PEG 0
653 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
654 on the max possible link width
655 0:No power saving, 1:Auto
656 **/
657 UINT8 Peg0PowerDownUnusedLanes;
658
659 /** Offset 0x0120 - Power down unused lanes on PEG 1
660 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
661 on the max possible link width
662 0:No power saving, 1:Auto
663 **/
664 UINT8 Peg1PowerDownUnusedLanes;
665
666 /** Offset 0x0121 - Power down unused lanes on PEG 2
667 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
668 on the max possible link width
669 0:No power saving, 1:Auto
670 **/
671 UINT8 Peg2PowerDownUnusedLanes;
672
673 /** Offset 0x0122 - Power down unused lanes on PEG 3
674 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
675 on the max possible link width
676 0:No power saving, 1:Auto
677 **/
678 UINT8 Peg3PowerDownUnusedLanes;
679
680 /** Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom
681 Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
682 Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
683 Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
684 0:Before, 1:After
685 **/
686 UINT8 InitPcieAspmAfterOprom;
687
688 /** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking
689 PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
690 Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
691 0:Normal Operation, 1:Disable SSC
692 **/
693 UINT8 PegDisableSpreadSpectrumClocking;
694
695 /** Offset 0x0125
696 **/
697 UINT8 UnusedUpdSpace4[3];
698
699 /** Offset 0x0128 - DMI Gen3 Root port preset values per lane
700 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
701 **/
702 UINT8 DmiGen3RootPortPreset[8];
703
704 /** Offset 0x0130 - DMI Gen3 End port preset values per lane
705 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
706 **/
707 UINT8 DmiGen3EndPointPreset[8];
708
709 /** Offset 0x0138 - DMI Gen3 End port Hint values per lane
710 Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
711 **/
712 UINT8 DmiGen3EndPointHint[8];
713
714 /** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control
715 Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
716 **/
717 UINT8 DmiGen3RxCtlePeaking[4];
718
719 /** Offset 0x0144 - Thermal Velocity Boost Ratio clipping
720 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
721 caused by high package temperatures for processors that implement the Intel Thermal
722 Velocity Boost (TVB) feature
723 0: Disabled, 1: Enabled
724 **/
725 UINT8 TvbRatioClipping;
726
727 /** Offset 0x0145 - Thermal Velocity Boost voltage optimization
728 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
729 for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
730 0: Disabled, 1: Enabled
731 **/
732 UINT8 TvbVoltageOptimization;
733
734 /** Offset 0x0146
735 **/
736 UINT8 UnusedUpdSpace5[2];
737
738 /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
739 Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
740 **/
741 UINT8 PegGen3RxCtlePeaking[10];
742
743 /** Offset 0x0152 - Memory data pointer for saved preset search results
744 The reference code will store the Gen3 Preset Search results in the SaDataHob's
745 PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
746 skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
747 **/
748 UINT32 PegDataPtr;
749
750 /** Offset 0x0156 - PEG PERST# GPIO information
751 The reference code will use the information in this structure in order to reset
752 PCIe Gen3 devices during equalization, if necessary
753 **/
754 UINT8 PegGpioData[28];
755
756 /** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port
757 0(Default): Disable, 1: Enable
758 **/
759 UINT8 PegRootPortHPE[4];
760
761 /** Offset 0x0176 - DeEmphasis control for DMI
762 DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
763 0: -6dB, 1: -3.5dB
764 **/
765 UINT8 DmiDeEmphasis;
766
767 /** Offset 0x0177 - Selection of the primary display device
768 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
769 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
770 **/
771 UINT8 PrimaryDisplay;
772
773 /** Offset 0x0178 - Selection of iGFX GTT Memory size
774 1=2MB, 2=4MB, 3=8MB, Default is 3
775 1:2MB, 2:4MB, 3:8MB
776 **/
777 UINT16 GttSize;
778
779 /** Offset 0x017A - Temporary MMIO address for GMADR
780 The reference code will use this as Temporary MMIO address space to access GMADR
781 Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
782 (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
783 - 0x1) (Where ApertureSize = 256MB)
784 **/
785 UINT32 GmAdr;
786
787 /** Offset 0x017E - Temporary MMIO address for GTTMMADR
788 The reference code will use this as Temporary MMIO address space to access GTTMMADR
789 Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
790 to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
791 + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
792 **/
793 UINT32 GttMmAdr;
794
795 /** Offset 0x0182 - Selection of PSMI Region size
796 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
797 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
798 **/
799 UINT8 PsmiRegionSize;
800
801 /** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0
802 Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
803 **/
804 UINT8 SaRtd3Pcie0Gpio[24];
805
806 /** Offset 0x019B - Switchable Graphics GPIO information for PEG 1
807 Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
808 **/
809 UINT8 SaRtd3Pcie1Gpio[24];
810
811 /** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2
812 Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
813 **/
814 UINT8 SaRtd3Pcie2Gpio[24];
815
816 /** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3
817 Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
818 **/
819 UINT8 SaRtd3Pcie3Gpio[24];
820
821 /** Offset 0x01E3 - Enable/Disable MRC TXT dependency
822 When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
823 MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
824 $EN_DIS
825 **/
826 UINT8 TxtImplemented;
827
828 /** Offset 0x01E4 - Enable/Disable SA OcSupport
829 Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
830 $EN_DIS
831 **/
832 UINT8 SaOcSupport;
833
834 /** Offset 0x01E5 - GT slice Voltage Mode
835 0(Default): Adaptive, 1: Override
836 0: Adaptive, 1: Override
837 **/
838 UINT8 GtVoltageMode;
839
840 /** Offset 0x01E6 - Maximum GTs turbo ratio override
841 0(Default)=Minimal/Auto, 60=Maximum
842 **/
843 UINT8 GtMaxOcRatio;
844
845 /** Offset 0x01E7 - The voltage offset applied to GT slice
846 0(Default)=Minimal, 1000=Maximum
847 **/
848 UINT16 GtVoltageOffset;
849
850 /** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies
851 0(Default)=Minimal, 2000=Maximum
852 **/
853 UINT16 GtVoltageOverride;
854
855 /** Offset 0x01EB - adaptive voltage applied during turbo frequencies
856 0(Default)=Minimal, 2000=Maximum
857 **/
858 UINT16 GtExtraTurboVoltage;
859
860 /** Offset 0x01ED - voltage offset applied to the SA
861 0(Default)=Minimal, 1000=Maximum
862 **/
863 UINT16 SaVoltageOffset;
864
865 /** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU
866 Root port Index number to indicate which PCIe root port has dGPU
867 **/
868 UINT8 RootPortIndex;
869
870 /** Offset 0x01F0 - Realtime Memory Timing
871 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
872 realtime memory timing changes after MRC_DONE.
873 0: Disabled, 1: Enabled
874 **/
875 UINT8 RealtimeMemoryTiming;
876
877 /** Offset 0x01F1 - Enable/Disable SA IPU
878 Enable(Default): Enable SA IPU, Disable: Disable SA IPU
879 $EN_DIS
880 **/
881 UINT8 SaIpuEnable;
882
883 /** Offset 0x01F2 - IPU IMR Configuration
884 0:IPU Camera, 1:IPU Gen Default is 0
885 0:IPU Camera, 1:IPU Gen
886 **/
887 UINT8 SaIpuImrConfiguration;
888
889 /** Offset 0x01F3 - Selection of PSMI Support On/Off
890 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
891 $EN_DIS
892 **/
893 UINT8 GtPsmiSupport;
894
895 /** Offset 0x01F4 - GT unslice Voltage Mode
896 0(Default): Adaptive, 1: Override
897 0: Adaptive, 1: Override
898 **/
899 UINT8 GtusVoltageMode;
900
901 /** Offset 0x01F5 - voltage offset applied to GT unslice
902 0(Default)=Minimal, 2000=Maximum
903 **/
904 UINT16 GtusVoltageOffset;
905
906 /** Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies
907 0(Default)=Minimal, 2000=Maximum
908 **/
909 UINT16 GtusVoltageOverride;
910
911 /** Offset 0x01F9 - adaptive voltage applied during turbo frequencies
912 0(Default)=Minimal, 2000=Maximum
913 **/
914 UINT16 GtusExtraTurboVoltage;
915
916 /** Offset 0x01FB - Maximum GTus turbo ratio override
917 0(Default)=Minimal, 60=Maximum
918 **/
919 UINT8 GtusMaxOcRatio;
920
921 /** Offset 0x01FC - SaPreMemProductionRsvd
922 Reserved for SA Pre-Mem Production
923 $EN_DIS
924 **/
925 UINT8 SaPreMemProductionRsvd[4];
926
927 /** Offset 0x0200 - BIST on Reset
928 Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
929 $EN_DIS
930 **/
931 UINT8 BistOnReset;
932
933 /** Offset 0x0201 - Skip Stop PBET Timer Enable/Disable
934 Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
935 $EN_DIS
936 **/
937 UINT8 SkipStopPbet;
938
939 /** Offset 0x0202 - C6DRAM power gating feature
940 This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
941 power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
942 feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
943 $EN_DIS
944 **/
945 UINT8 EnableC6Dram;
946
947 /** Offset 0x0203 - Over clocking support
948 Over clocking support; <b>0: Disable</b>; 1: Enable
949 $EN_DIS
950 **/
951 UINT8 OcSupport;
952
953 /** Offset 0x0204 - Over clocking Lock
954 Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
955 $EN_DIS
956 **/
957 UINT8 OcLock;
958
959 /** Offset 0x0205 - Maximum Core Turbo Ratio Override
960 Maximum core turbo ratio override allows to increase CPU core frequency beyond the
961 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
962 **/
963 UINT8 CoreMaxOcRatio;
964
965 /** Offset 0x0206 - Core voltage mode
966 Core voltage mode; <b>0: Adaptive</b>; 1: Override.
967 $EN_DIS
968 **/
969 UINT8 CoreVoltageMode;
970
971 /** Offset 0x0207 - Program Cache Attributes
972 Program Cache Attributes; <b>0: Program</b>; 1: Disable Program.
973 $EN_DIS
974 **/
975 UINT8 DisableMtrrProgram;
976
977 /** Offset 0x0208 - Maximum clr turbo ratio override
978 Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
979 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
980 **/
981 UINT8 RingMaxOcRatio;
982
983 /** Offset 0x0209 - Hyper Threading Enable/Disable
984 Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
985 $EN_DIS
986 **/
987 UINT8 HyperThreading;
988
989 /** Offset 0x020A - CPU ratio value
990 CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled.
991 **/
992 UINT8 CpuRatio;
993
994 /** Offset 0x020B - Boot frequency
995 Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
996 <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
997 is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
998 0:0, 1:1, 2:2
999 **/
1000 UINT8 BootFrequency;
1001
1002 /** Offset 0x020C - Number of active cores
1003 Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
1004 2 </b>;<b>3: 3 </b>
1005 0:All, 1:1, 2:2, 3:3
1006 **/
1007 UINT8 ActiveCoreCount;
1008
1009 /** Offset 0x020D - Processor Early Power On Configuration FCLK setting
1010 <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
1011 2: 400 MHz. - 3: Reserved
1012 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
1013 **/
1014 UINT8 FClkFrequency;
1015
1016 /** Offset 0x020E - Set JTAG power in C10 and deeper power states
1017 False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
1018 and deeper power states for debug purpose. <b>0: False</b>; 1: True.
1019 0: False, 1: True
1020 **/
1021 UINT8 JtagC10PowerGateDisable;
1022
1023 /** Offset 0x020F - Enable or Disable VMX
1024 Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
1025 $EN_DIS
1026 **/
1027 UINT8 VmxEnable;
1028
1029 /** Offset 0x0210 - AVX2 Ratio Offset
1030 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
1031 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
1032 **/
1033 UINT8 Avx2RatioOffset;
1034
1035 /** Offset 0x0211 - AVX3 Ratio Offset
1036 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
1037 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
1038 **/
1039 UINT8 Avx3RatioOffset;
1040
1041 /** Offset 0x0212 - BCLK Adaptive Voltage Enable
1042 When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
1043 Disable;<b> 1: Enable
1044 $EN_DIS
1045 **/
1046 UINT8 BclkAdaptiveVoltage;
1047
1048 /** Offset 0x0213 - Core PLL voltage offset
1049 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1050 **/
1051 UINT8 CorePllVoltageOffset;
1052
1053 /** Offset 0x0214 - core voltage override
1054 The core voltage override which is applied to the entire range of cpu core frequencies.
1055 Valid Range 0 to 2000
1056 **/
1057 UINT16 CoreVoltageOverride;
1058
1059 /** Offset 0x0216 - Core Turbo voltage Adaptive
1060 Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
1061 Valid Range 0 to 2000
1062 **/
1063 UINT16 CoreVoltageAdaptive;
1064
1065 /** Offset 0x0218 - Core Turbo voltage Offset
1066 The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
1067 **/
1068 UINT16 CoreVoltageOffset;
1069
1070 /** Offset 0x021A - Ring Downbin
1071 Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
1072 lower than the core ratio.0: Disable; <b>1: Enable.</b>
1073 $EN_DIS
1074 **/
1075 UINT8 RingDownBin;
1076
1077 /** Offset 0x021B - Ring voltage mode
1078 Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
1079 $EN_DIS
1080 **/
1081 UINT8 RingVoltageMode;
1082
1083 /** Offset 0x021C - Ring voltage override
1084 The ring voltage override which is applied to the entire range of cpu ring frequencies.
1085 Valid Range 0 to 2000
1086 **/
1087 UINT16 RingVoltageOverride;
1088
1089 /** Offset 0x021E - Ring Turbo voltage Adaptive
1090 Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
1091 Valid Range 0 to 2000
1092 **/
1093 UINT16 RingVoltageAdaptive;
1094
1095 /** Offset 0x0220 - Ring Turbo voltage Offset
1096 The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
1097 **/
1098 UINT16 RingVoltageOffset;
1099
1100 /** Offset 0x0222 - TjMax Offset
1101 TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
1102 TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
1103 **/
1104 UINT8 TjMaxOffset;
1105
1106 /** Offset 0x0223 - BiosGuard
1107 Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
1108 $EN_DIS
1109 **/
1110 UINT8 BiosGuard;
1111
1112 /** Offset 0x0224
1113 **/
1114 UINT8 BiosGuardToolsInterface;
1115
1116 /** Offset 0x0225 - EnableSgx
1117 Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
1118 0: Disable, 1: Enable, 2: Software Control
1119 **/
1120 UINT8 EnableSgx;
1121
1122 /** Offset 0x0226 - Txt
1123 Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
1124 $EN_DIS
1125 **/
1126 UINT8 Txt;
1127
1128 /** Offset 0x0227
1129 **/
1130 UINT8 UnusedUpdSpace6;
1131
1132 /** Offset 0x0228 - PrmrrSize
1133 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
1134 **/
1135 UINT32 PrmrrSize;
1136
1137 /** Offset 0x022C - SinitMemorySize
1138 Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
1139 **/
1140 UINT32 SinitMemorySize;
1141
1142 /** Offset 0x0230 - TxtHeapMemorySize
1143 Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
1144 **/
1145 UINT32 TxtHeapMemorySize;
1146
1147 /** Offset 0x0234 - TxtDprMemorySize
1148 Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
1149 **/
1150 UINT32 TxtDprMemorySize;
1151
1152 /** Offset 0x0238 - TxtDprMemoryBase
1153 Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
1154 **/
1155 UINT64 TxtDprMemoryBase;
1156
1157 /** Offset 0x0240 - BiosAcmBase
1158 Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
1159 **/
1160 UINT32 BiosAcmBase;
1161
1162 /** Offset 0x0244 - BiosAcmSize
1163 Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
1164 **/
1165 UINT32 BiosAcmSize;
1166
1167 /** Offset 0x0248 - ApStartupBase
1168 Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
1169 **/
1170 UINT32 ApStartupBase;
1171
1172 /** Offset 0x024C - TgaSize
1173 Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
1174 **/
1175 UINT32 TgaSize;
1176
1177 /** Offset 0x0250 - TxtLcpPdBase
1178 Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
1179 **/
1180 UINT64 TxtLcpPdBase;
1181
1182 /** Offset 0x0258 - TxtLcpPdSize
1183 Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
1184 **/
1185 UINT64 TxtLcpPdSize;
1186
1187 /** Offset 0x0260 - IsTPMPresence
1188 IsTPMPresence default values
1189 **/
1190 UINT8 IsTPMPresence;
1191
1192 /** Offset 0x0261 - ReservedSecurityPreMem
1193 Reserved for Security Pre-Mem
1194 $EN_DIS
1195 **/
1196 UINT8 ReservedSecurityPreMem[15];
1197
1198 /** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle
1199 Enable PCH PCIe Gen 3 Set CTLE Value.
1200 **/
1201 UINT8 PchPcieHsioRxSetCtleEnable[24];
1202
1203 /** Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value
1204 PCH PCIe Gen 3 Set CTLE Value.
1205 **/
1206 UINT8 PchPcieHsioRxSetCtle[24];
1207
1208 /** Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
1209 0: Disable; 1: Enable.
1210 **/
1211 UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
1212
1213 /** Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
1214 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
1215 **/
1216 UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
1217
1218 /** Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
1219 0: Disable; 1: Enable.
1220 **/
1221 UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
1222
1223 /** Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
1224 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
1225 **/
1226 UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
1227
1228 /** Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
1229 0: Disable; 1: Enable.
1230 **/
1231 UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
1232
1233 /** Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
1234 PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
1235 **/
1236 UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
1237
1238 /** Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
1239 0: Disable; 1: Enable.
1240 **/
1241 UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
1242
1243 /** Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
1244 PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
1245 **/
1246 UINT8 PchPcieHsioTxGen1DeEmph[24];
1247
1248 /** Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
1249 0: Disable; 1: Enable.
1250 **/
1251 UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
1252
1253 /** Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
1254 PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
1255 **/
1256 UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
1257
1258 /** Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
1259 0: Disable; 1: Enable.
1260 **/
1261 UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
1262
1263 /** Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
1264 PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
1265 **/
1266 UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
1267
1268 /** Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1269 0: Disable; 1: Enable.
1270 **/
1271 UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
1272
1273 /** Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1274 PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1275 **/
1276 UINT8 PchSataHsioRxGen1EqBoostMag[8];
1277
1278 /** Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1279 0: Disable; 1: Enable.
1280 **/
1281 UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
1282
1283 /** Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1284 PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1285 **/
1286 UINT8 PchSataHsioRxGen2EqBoostMag[8];
1287
1288 /** Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1289 0: Disable; 1: Enable.
1290 **/
1291 UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
1292
1293 /** Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1294 PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1295 **/
1296 UINT8 PchSataHsioRxGen3EqBoostMag[8];
1297
1298 /** Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
1299 0: Disable; 1: Enable.
1300 **/
1301 UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
1302
1303 /** Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
1304 PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
1305 **/
1306 UINT8 PchSataHsioTxGen1DownscaleAmp[8];
1307
1308 /** Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
1309 0: Disable; 1: Enable.
1310 **/
1311 UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
1312
1313 /** Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
1314 PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
1315 **/
1316 UINT8 PchSataHsioTxGen2DownscaleAmp[8];
1317
1318 /** Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
1319 0: Disable; 1: Enable.
1320 **/
1321 UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
1322
1323 /** Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
1324 PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
1325 **/
1326 UINT8 PchSataHsioTxGen3DownscaleAmp[8];
1327
1328 /** Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
1329 0: Disable; 1: Enable.
1330 **/
1331 UINT8 PchSataHsioTxGen1DeEmphEnable[8];
1332
1333 /** Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
1334 PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
1335 **/
1336 UINT8 PchSataHsioTxGen1DeEmph[8];
1337
1338 /** Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
1339 0: Disable; 1: Enable.
1340 **/
1341 UINT8 PchSataHsioTxGen2DeEmphEnable[8];
1342
1343 /** Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
1344 PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
1345 **/
1346 UINT8 PchSataHsioTxGen2DeEmph[8];
1347
1348 /** Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
1349 0: Disable; 1: Enable.
1350 **/
1351 UINT8 PchSataHsioTxGen3DeEmphEnable[8];
1352
1353 /** Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
1354 PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
1355 **/
1356 UINT8 PchSataHsioTxGen3DeEmph[8];
1357
1358 /** Offset 0x0450 - PCH LPC Enhance the port 8xh decoding
1359 Original LPC only decodes one byte of port 80h.
1360 $EN_DIS
1361 **/
1362 UINT8 PchLpcEnhancePort8xhDecoding;
1363
1364 /** Offset 0x0451 - PCH Port80 Route
1365 Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
1366 $EN_DIS
1367 **/
1368 UINT8 PchPort80Route;
1369
1370 /** Offset 0x0452 - Enable SMBus ARP support
1371 Enable SMBus ARP support.
1372 $EN_DIS
1373 **/
1374 UINT8 SmbusArpEnable;
1375
1376 /** Offset 0x0453 - Number of RsvdSmbusAddressTable.
1377 The number of elements in the RsvdSmbusAddressTable.
1378 **/
1379 UINT8 PchNumRsvdSmbusAddresses;
1380
1381 /** Offset 0x0454 - SMBUS Base Address
1382 SMBUS Base Address (IO space).
1383 **/
1384 UINT16 PchSmbusIoBase;
1385
1386 /** Offset 0x0456 - Size of PCIe IMR.
1387 Size of PCIe IMR in megabytes
1388 **/
1389 UINT16 PcieImrSize;
1390
1391 /** Offset 0x0458 - Point of RsvdSmbusAddressTable
1392 Array of addresses reserved for non-ARP-capable SMBus devices.
1393 **/
1394 UINT32 RsvdSmbusAddressTablePtr;
1395
1396 /** Offset 0x045C - Enable PCIE RP Mask
1397 Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
1398 for port1, bit1 for port2, and so on.
1399 **/
1400 UINT32 PcieRpEnableMask;
1401
1402 /** Offset 0x0460 - Enable PCIe IMR
1403 0:Disable, 1:Enable
1404 $EN_DIS
1405 **/
1406 UINT8 PcieImrEnabled;
1407
1408 /** Offset 0x0461 - Root port number for IMR.
1409 Root port number for IMR.
1410 **/
1411 UINT8 ImrRpSelection;
1412
1413 /** Offset 0x0462 - Enable SMBus Alert Pin
1414 Enable SMBus Alert Pin.
1415 $EN_DIS
1416 **/
1417 UINT8 PchSmbAlertEnable;
1418
1419 /** Offset 0x0463 - ReservedPchPreMem
1420 Reserved for Pch Pre-Mem
1421 $EN_DIS
1422 **/
1423 UINT8 ReservedPchPreMem[13];
1424
1425 /** Offset 0x0470 - Debug Interfaces
1426 Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
1427 BIT2 - Not used.
1428 **/
1429 UINT8 PcdDebugInterfaceFlags;
1430
1431 /** Offset 0x0471 - PcdSerialIoUartNumber
1432 Select SerialIo Uart Controller for debug.
1433 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
1434 **/
1435 UINT8 PcdSerialIoUartNumber;
1436
1437 /** Offset 0x0472 - ISA Serial Base selection
1438 Select ISA Serial Base address. Default is 0x3F8.
1439 0:0x3F8, 1:0x2F8
1440 **/
1441 UINT8 PcdIsaSerialUartBase;
1442
1443 /** Offset 0x0473 - GT PLL voltage offset
1444 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1445 **/
1446 UINT8 GtPllVoltageOffset;
1447
1448 /** Offset 0x0474 - Ring PLL voltage offset
1449 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1450 **/
1451 UINT8 RingPllVoltageOffset;
1452
1453 /** Offset 0x0475 - System Agent PLL voltage offset
1454 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1455 **/
1456 UINT8 SaPllVoltageOffset;
1457
1458 /** Offset 0x0476 - Memory Controller PLL voltage offset
1459 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1460 **/
1461 UINT8 McPllVoltageOffset;
1462
1463 /** Offset 0x0477 - MRC Safe Config
1464 Enables/Disable MRC Safe Config
1465 $EN_DIS
1466 **/
1467 UINT8 MrcSafeConfig;
1468
1469 /** Offset 0x0478 - PcdSerialDebugBaudRate
1470 Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
1471 3:9600, 4:19200, 6:56700, 7:115200
1472 **/
1473 UINT8 PcdSerialDebugBaudRate;
1474
1475 /** Offset 0x0479 - HobBufferSize
1476 Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
1477 total HOB size).
1478 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
1479 **/
1480 UINT8 HobBufferSize;
1481
1482 /** Offset 0x047A - Early Command Training
1483 Enables/Disable Early Command Training
1484 $EN_DIS
1485 **/
1486 UINT8 ECT;
1487
1488 /** Offset 0x047B - SenseAmp Offset Training
1489 Enables/Disable SenseAmp Offset Training
1490 $EN_DIS
1491 **/
1492 UINT8 SOT;
1493
1494 /** Offset 0x047C - Early ReadMPR Timing Centering 2D
1495 Enables/Disable Early ReadMPR Timing Centering 2D
1496 $EN_DIS
1497 **/
1498 UINT8 ERDMPRTC2D;
1499
1500 /** Offset 0x047D - Read MPR Training
1501 Enables/Disable Read MPR Training
1502 $EN_DIS
1503 **/
1504 UINT8 RDMPRT;
1505
1506 /** Offset 0x047E - Receive Enable Training
1507 Enables/Disable Receive Enable Training
1508 $EN_DIS
1509 **/
1510 UINT8 RCVET;
1511
1512 /** Offset 0x047F - Jedec Write Leveling
1513 Enables/Disable Jedec Write Leveling
1514 $EN_DIS
1515 **/
1516 UINT8 JWRL;
1517
1518 /** Offset 0x0480 - Early Write Time Centering 2D
1519 Enables/Disable Early Write Time Centering 2D
1520 $EN_DIS
1521 **/
1522 UINT8 EWRTC2D;
1523
1524 /** Offset 0x0481 - Early Read Time Centering 2D
1525 Enables/Disable Early Read Time Centering 2D
1526 $EN_DIS
1527 **/
1528 UINT8 ERDTC2D;
1529
1530 /** Offset 0x0482 - Write Timing Centering 1D
1531 Enables/Disable Write Timing Centering 1D
1532 $EN_DIS
1533 **/
1534 UINT8 WRTC1D;
1535
1536 /** Offset 0x0483 - Write Voltage Centering 1D
1537 Enables/Disable Write Voltage Centering 1D
1538 $EN_DIS
1539 **/
1540 UINT8 WRVC1D;
1541
1542 /** Offset 0x0484 - Read Timing Centering 1D
1543 Enables/Disable Read Timing Centering 1D
1544 $EN_DIS
1545 **/
1546 UINT8 RDTC1D;
1547
1548 /** Offset 0x0485 - Dimm ODT Training
1549 Enables/Disable Dimm ODT Training
1550 $EN_DIS
1551 **/
1552 UINT8 DIMMODTT;
1553
1554 /** Offset 0x0486 - DIMM RON Training
1555 Enables/Disable DIMM RON Training
1556 $EN_DIS
1557 **/
1558 UINT8 DIMMRONT;
1559
1560 /** Offset 0x0487 - Write Drive Strength/Equalization 2D
1561 Enables/Disable Write Drive Strength/Equalization 2D
1562 $EN_DIS
1563 **/
1564 UINT8 WRDSEQT;
1565
1566 /** Offset 0x0488 - Write Slew Rate Training
1567 Enables/Disable Write Slew Rate Training
1568 $EN_DIS
1569 **/
1570 UINT8 WRSRT;
1571
1572 /** Offset 0x0489 - Read ODT Training
1573 Enables/Disable Read ODT Training
1574 $EN_DIS
1575 **/
1576 UINT8 RDODTT;
1577
1578 /** Offset 0x048A - Read Equalization Training
1579 Enables/Disable Read Equalization Training
1580 $EN_DIS
1581 **/
1582 UINT8 RDEQT;
1583
1584 /** Offset 0x048B - Read Amplifier Training
1585 Enables/Disable Read Amplifier Training
1586 $EN_DIS
1587 **/
1588 UINT8 RDAPT;
1589
1590 /** Offset 0x048C - Write Timing Centering 2D
1591 Enables/Disable Write Timing Centering 2D
1592 $EN_DIS
1593 **/
1594 UINT8 WRTC2D;
1595
1596 /** Offset 0x048D - Read Timing Centering 2D
1597 Enables/Disable Read Timing Centering 2D
1598 $EN_DIS
1599 **/
1600 UINT8 RDTC2D;
1601
1602 /** Offset 0x048E - Write Voltage Centering 2D
1603 Enables/Disable Write Voltage Centering 2D
1604 $EN_DIS
1605 **/
1606 UINT8 WRVC2D;
1607
1608 /** Offset 0x048F - Read Voltage Centering 2D
1609 Enables/Disable Read Voltage Centering 2D
1610 $EN_DIS
1611 **/
1612 UINT8 RDVC2D;
1613
1614 /** Offset 0x0490 - Command Voltage Centering
1615 Enables/Disable Command Voltage Centering
1616 $EN_DIS
1617 **/
1618 UINT8 CMDVC;
1619
1620 /** Offset 0x0491 - Late Command Training
1621 Enables/Disable Late Command Training
1622 $EN_DIS
1623 **/
1624 UINT8 LCT;
1625
1626 /** Offset 0x0492 - Round Trip Latency Training
1627 Enables/Disable Round Trip Latency Training
1628 $EN_DIS
1629 **/
1630 UINT8 RTL;
1631
1632 /** Offset 0x0493 - Turn Around Timing Training
1633 Enables/Disable Turn Around Timing Training
1634 $EN_DIS
1635 **/
1636 UINT8 TAT;
1637
1638 /** Offset 0x0494 - Memory Test
1639 Enables/Disable Memory Test
1640 $EN_DIS
1641 **/
1642 UINT8 MEMTST;
1643
1644 /** Offset 0x0495 - DIMM SPD Alias Test
1645 Enables/Disable DIMM SPD Alias Test
1646 $EN_DIS
1647 **/
1648 UINT8 ALIASCHK;
1649
1650 /** Offset 0x0496 - Receive Enable Centering 1D
1651 Enables/Disable Receive Enable Centering 1D
1652 $EN_DIS
1653 **/
1654 UINT8 RCVENC1D;
1655
1656 /** Offset 0x0497 - Retrain Margin Check
1657 Enables/Disable Retrain Margin Check
1658 $EN_DIS
1659 **/
1660 UINT8 RMC;
1661
1662 /** Offset 0x0498 - Write Drive Strength Up/Dn independently
1663 Enables/Disable Write Drive Strength Up/Dn independently
1664 $EN_DIS
1665 **/
1666 UINT8 WRDSUDT;
1667
1668 /** Offset 0x0499 - ECC Support
1669 Enables/Disable ECC Support
1670 $EN_DIS
1671 **/
1672 UINT8 EccSupport;
1673
1674 /** Offset 0x049A - Memory Remap
1675 Enables/Disable Memory Remap
1676 $EN_DIS
1677 **/
1678 UINT8 RemapEnable;
1679
1680 /** Offset 0x049B - Rank Interleave support
1681 Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
1682 the same time.
1683 $EN_DIS
1684 **/
1685 UINT8 RankInterleave;
1686
1687 /** Offset 0x049C - Enhanced Interleave support
1688 Enables/Disable Enhanced Interleave support
1689 $EN_DIS
1690 **/
1691 UINT8 EnhancedInterleave;
1692
1693 /** Offset 0x049D - Memory Trace
1694 Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of
1695 equal size. This option may change TOLUD and REMAP values as needed.
1696 $EN_DIS
1697 **/
1698 UINT8 MemoryTrace;
1699
1700 /** Offset 0x049E - Ch Hash Support
1701 Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
1702 $EN_DIS
1703 **/
1704 UINT8 ChHashEnable;
1705
1706 /** Offset 0x049F - Extern Therm Status
1707 Enables/Disable Extern Therm Status
1708 $EN_DIS
1709 **/
1710 UINT8 EnableExtts;
1711
1712 /** Offset 0x04A0 - Closed Loop Therm Manage
1713 Enables/Disable Closed Loop Therm Manage
1714 $EN_DIS
1715 **/
1716 UINT8 EnableCltm;
1717
1718 /** Offset 0x04A1 - Open Loop Therm Manage
1719 Enables/Disable Open Loop Therm Manage
1720 $EN_DIS
1721 **/
1722 UINT8 EnableOltm;
1723
1724 /** Offset 0x04A2 - DDR PowerDown and idle counter
1725 Enables/Disable DDR PowerDown and idle counter
1726 $EN_DIS
1727 **/
1728 UINT8 EnablePwrDn;
1729
1730 /** Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR
1731 Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
1732 $EN_DIS
1733 **/
1734 UINT8 EnablePwrDnLpddr;
1735
1736 /** Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values
1737 Enables/Disable Use user provided power weights, scale factor, and channel power
1738 floor values
1739 $EN_DIS
1740 **/
1741 UINT8 UserPowerWeightsEn;
1742
1743 /** Offset 0x04A5 - RAPL PL Lock
1744 Enables/Disable RAPL PL Lock
1745 $EN_DIS
1746 **/
1747 UINT8 RaplLim2Lock;
1748
1749 /** Offset 0x04A6 - RAPL PL 2 enable
1750 Enables/Disable RAPL PL 2 enable
1751 $EN_DIS
1752 **/
1753 UINT8 RaplLim2Ena;
1754
1755 /** Offset 0x04A7 - RAPL PL 1 enable
1756 Enables/Disable RAPL PL 1 enable
1757 $EN_DIS
1758 **/
1759 UINT8 RaplLim1Ena;
1760
1761 /** Offset 0x04A8 - SelfRefresh Enable
1762 Enables/Disable SelfRefresh Enable
1763 $EN_DIS
1764 **/
1765 UINT8 SrefCfgEna;
1766
1767 /** Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR
1768 Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
1769 $EN_DIS
1770 **/
1771 UINT8 ThrtCkeMinDefeatLpddr;
1772
1773 /** Offset 0x04AA - Throttler CKEMin Defeature
1774 Enables/Disable Throttler CKEMin Defeature
1775 $EN_DIS
1776 **/
1777 UINT8 ThrtCkeMinDefeat;
1778
1779 /** Offset 0x04AB - Enable RH Prevention
1780 Enables/Disable RH Prevention
1781 $EN_DIS
1782 **/
1783 UINT8 RhPrevention;
1784
1785 /** Offset 0x04AC - Exit On Failure (MRC)
1786 Enables/Disable Exit On Failure (MRC)
1787 $EN_DIS
1788 **/
1789 UINT8 ExitOnFailure;
1790
1791 /** Offset 0x04AD - LPDDR Thermal Sensor
1792 Enables/Disable LPDDR Thermal Sensor
1793 $EN_DIS
1794 **/
1795 UINT8 DdrThermalSensor;
1796
1797 /** Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
1798 Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
1799 $EN_DIS
1800 **/
1801 UINT8 Ddr4DdpSharedClock;
1802
1803 /** Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
1804 ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
1805 $EN_DIS
1806 **/
1807 UINT8 Ddr4DdpSharedZq;
1808
1809 /** Offset 0x04B0 - Ch Hash Mask
1810 Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
1811 BITS [19:6
1812 **/
1813 UINT16 ChHashMask;
1814
1815 /** Offset 0x04B2 - Base reference clock value
1816 Base reference clock value, in Hertz(Default is 125Hz)
1817 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
1818 **/
1819 UINT32 BClkFrequency;
1820
1821 /** Offset 0x04B6 - Ch Hash Interleaved Bit
1822 Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
1823 the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
1824 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
1825 **/
1826 UINT8 ChHashInterleaveBit;
1827
1828 /** Offset 0x04B7 - Energy Scale Factor
1829 Energy Scale Factor, Default is 4
1830 **/
1831 UINT8 EnergyScaleFact;
1832
1833 /** Offset 0x04B8 - EPG DIMM Idd3N
1834 Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
1835 a per DIMM basis. Default is 26
1836 **/
1837 UINT16 Idd3n;
1838
1839 /** Offset 0x04BA - EPG DIMM Idd3P
1840 Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
1841 on a per DIMM basis. Default is 11
1842 **/
1843 UINT16 Idd3p;
1844
1845 /** Offset 0x04BC - CMD Slew Rate Training
1846 Enable/Disable CMD Slew Rate Training
1847 $EN_DIS
1848 **/
1849 UINT8 CMDSR;
1850
1851 /** Offset 0x04BD - CMD Drive Strength and Tx Equalization
1852 Enable/Disable CMD Drive Strength and Tx Equalization
1853 $EN_DIS
1854 **/
1855 UINT8 CMDDSEQ;
1856
1857 /** Offset 0x04BE - CMD Normalization
1858 Enable/Disable CMD Normalization
1859 $EN_DIS
1860 **/
1861 UINT8 CMDNORM;
1862
1863 /** Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training
1864 Enable/Disable Early DQ Write Drive Strength and Equalization Training
1865 $EN_DIS
1866 **/
1867 UINT8 EWRDSEQ;
1868
1869 /** Offset 0x04C0 - RH Activation Probability
1870 RH Activation Probability, Probability value is 1/2^(inputvalue)
1871 **/
1872 UINT8 RhActProbability;
1873
1874 /** Offset 0x04C1 - RAPL PL 2 WindowX
1875 Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
1876 **/
1877 UINT8 RaplLim2WindX;
1878
1879 /** Offset 0x04C2 - RAPL PL 2 WindowY
1880 Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
1881 **/
1882 UINT8 RaplLim2WindY;
1883
1884 /** Offset 0x04C3 - RAPL PL 1 WindowX
1885 Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
1886 **/
1887 UINT8 RaplLim1WindX;
1888
1889 /** Offset 0x04C4 - RAPL PL 1 WindowY
1890 Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
1891 **/
1892 UINT8 RaplLim1WindY;
1893
1894 /** Offset 0x04C5 - RAPL PL 2 Power
1895 range[0;2^14-1]= [2047.875;0]in W, (222= Def)
1896 **/
1897 UINT16 RaplLim2Pwr;
1898
1899 /** Offset 0x04C7 - RAPL PL 1 Power
1900 range[0;2^14-1]= [2047.875;0]in W, (0= Def)
1901 **/
1902 UINT16 RaplLim1Pwr;
1903
1904 /** Offset 0x04C9 - Warm Threshold Ch0 Dimm0
1905 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1906 **/
1907 UINT8 WarmThresholdCh0Dimm0;
1908
1909 /** Offset 0x04CA - Warm Threshold Ch0 Dimm1
1910 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1911 **/
1912 UINT8 WarmThresholdCh0Dimm1;
1913
1914 /** Offset 0x04CB - Warm Threshold Ch1 Dimm0
1915 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1916 **/
1917 UINT8 WarmThresholdCh1Dimm0;
1918
1919 /** Offset 0x04CC - Warm Threshold Ch1 Dimm1
1920 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1921 **/
1922 UINT8 WarmThresholdCh1Dimm1;
1923
1924 /** Offset 0x04CD - Hot Threshold Ch0 Dimm0
1925 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1926 **/
1927 UINT8 HotThresholdCh0Dimm0;
1928
1929 /** Offset 0x04CE - Hot Threshold Ch0 Dimm1
1930 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1931 **/
1932 UINT8 HotThresholdCh0Dimm1;
1933
1934 /** Offset 0x04CF - Hot Threshold Ch1 Dimm0
1935 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1936 **/
1937 UINT8 HotThresholdCh1Dimm0;
1938
1939 /** Offset 0x04D0 - Hot Threshold Ch1 Dimm1
1940 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
1941 **/
1942 UINT8 HotThresholdCh1Dimm1;
1943
1944 /** Offset 0x04D1 - Warm Budget Ch0 Dimm0
1945 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1946 **/
1947 UINT8 WarmBudgetCh0Dimm0;
1948
1949 /** Offset 0x04D2 - Warm Budget Ch0 Dimm1
1950 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1951 **/
1952 UINT8 WarmBudgetCh0Dimm1;
1953
1954 /** Offset 0x04D3 - Warm Budget Ch1 Dimm0
1955 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1956 **/
1957 UINT8 WarmBudgetCh1Dimm0;
1958
1959 /** Offset 0x04D4 - Warm Budget Ch1 Dimm1
1960 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1961 **/
1962 UINT8 WarmBudgetCh1Dimm1;
1963
1964 /** Offset 0x04D5 - Hot Budget Ch0 Dimm0
1965 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1966 **/
1967 UINT8 HotBudgetCh0Dimm0;
1968
1969 /** Offset 0x04D6 - Hot Budget Ch0 Dimm1
1970 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1971 **/
1972 UINT8 HotBudgetCh0Dimm1;
1973
1974 /** Offset 0x04D7 - Hot Budget Ch1 Dimm0
1975 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1976 **/
1977 UINT8 HotBudgetCh1Dimm0;
1978
1979 /** Offset 0x04D8 - Hot Budget Ch1 Dimm1
1980 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
1981 **/
1982 UINT8 HotBudgetCh1Dimm1;
1983
1984 /** Offset 0x04D9 - Idle Energy Ch0Dimm0
1985 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
1986 **/
1987 UINT8 IdleEnergyCh0Dimm0;
1988
1989 /** Offset 0x04DA - Idle Energy Ch0Dimm1
1990 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
1991 **/
1992 UINT8 IdleEnergyCh0Dimm1;
1993
1994 /** Offset 0x04DB - Idle Energy Ch1Dimm0
1995 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
1996 **/
1997 UINT8 IdleEnergyCh1Dimm0;
1998
1999 /** Offset 0x04DC - Idle Energy Ch1Dimm1
2000 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
2001 **/
2002 UINT8 IdleEnergyCh1Dimm1;
2003
2004 /** Offset 0x04DD - PowerDown Energy Ch0Dimm0
2005 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2006 **/
2007 UINT8 PdEnergyCh0Dimm0;
2008
2009 /** Offset 0x04DE - PowerDown Energy Ch0Dimm1
2010 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2011 **/
2012 UINT8 PdEnergyCh0Dimm1;
2013
2014 /** Offset 0x04DF - PowerDown Energy Ch1Dimm0
2015 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2016 **/
2017 UINT8 PdEnergyCh1Dimm0;
2018
2019 /** Offset 0x04E0 - PowerDown Energy Ch1Dimm1
2020 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2021 **/
2022 UINT8 PdEnergyCh1Dimm1;
2023
2024 /** Offset 0x04E1 - Activate Energy Ch0Dimm0
2025 Activate Energy Contribution, range[255;0],(172= Def)
2026 **/
2027 UINT8 ActEnergyCh0Dimm0;
2028
2029 /** Offset 0x04E2 - Activate Energy Ch0Dimm1
2030 Activate Energy Contribution, range[255;0],(172= Def)
2031 **/
2032 UINT8 ActEnergyCh0Dimm1;
2033
2034 /** Offset 0x04E3 - Activate Energy Ch1Dimm0
2035 Activate Energy Contribution, range[255;0],(172= Def)
2036 **/
2037 UINT8 ActEnergyCh1Dimm0;
2038
2039 /** Offset 0x04E4 - Activate Energy Ch1Dimm1
2040 Activate Energy Contribution, range[255;0],(172= Def)
2041 **/
2042 UINT8 ActEnergyCh1Dimm1;
2043
2044 /** Offset 0x04E5 - Read Energy Ch0Dimm0
2045 Read Energy Contribution, range[255;0],(212= Def)
2046 **/
2047 UINT8 RdEnergyCh0Dimm0;
2048
2049 /** Offset 0x04E6 - Read Energy Ch0Dimm1
2050 Read Energy Contribution, range[255;0],(212= Def)
2051 **/
2052 UINT8 RdEnergyCh0Dimm1;
2053
2054 /** Offset 0x04E7 - Read Energy Ch1Dimm0
2055 Read Energy Contribution, range[255;0],(212= Def)
2056 **/
2057 UINT8 RdEnergyCh1Dimm0;
2058
2059 /** Offset 0x04E8 - Read Energy Ch1Dimm1
2060 Read Energy Contribution, range[255;0],(212= Def)
2061 **/
2062 UINT8 RdEnergyCh1Dimm1;
2063
2064 /** Offset 0x04E9 - Write Energy Ch0Dimm0
2065 Write Energy Contribution, range[255;0],(221= Def)
2066 **/
2067 UINT8 WrEnergyCh0Dimm0;
2068
2069 /** Offset 0x04EA - Write Energy Ch0Dimm1
2070 Write Energy Contribution, range[255;0],(221= Def)
2071 **/
2072 UINT8 WrEnergyCh0Dimm1;
2073
2074 /** Offset 0x04EB - Write Energy Ch1Dimm0
2075 Write Energy Contribution, range[255;0],(221= Def)
2076 **/
2077 UINT8 WrEnergyCh1Dimm0;
2078
2079 /** Offset 0x04EC - Write Energy Ch1Dimm1
2080 Write Energy Contribution, range[255;0],(221= Def)
2081 **/
2082 UINT8 WrEnergyCh1Dimm1;
2083
2084 /** Offset 0x04ED - Throttler CKEMin Timer
2085 Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
2086 Default is 0x30
2087 **/
2088 UINT8 ThrtCkeMinTmr;
2089
2090 /** Offset 0x04EE - Cke Rank Mapping
2091 Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
2092 which rank CKE[i] goes to.
2093 **/
2094 UINT8 CkeRankMapping;
2095
2096 /** Offset 0x04EF - Rapl Power Floor Ch0
2097 Power budget ,range[255;0],(0= 5.3W Def)
2098 **/
2099 UINT8 RaplPwrFlCh0;
2100
2101 /** Offset 0x04F0 - Rapl Power Floor Ch1
2102 Power budget ,range[255;0],(0= 5.3W Def)
2103 **/
2104 UINT8 RaplPwrFlCh1;
2105
2106 /** Offset 0x04F1 - Command Rate Support
2107 CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
2108 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS
2109 **/
2110 UINT8 EnCmdRate;
2111
2112 /** Offset 0x04F2 - REFRESH_2X_MODE
2113 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
2114 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
2115 **/
2116 UINT8 Refresh2X;
2117
2118 /** Offset 0x04F3 - Energy Performance Gain
2119 Enable/disable(default) Energy Performance Gain.
2120 $EN_DIS
2121 **/
2122 UINT8 EpgEnable;
2123
2124 /** Offset 0x04F4 - Row Hammer Solution
2125 Type of method used to prevent Row Hammer. Default is Hardware RHP
2126 0:Hardware RHP, 1:2x Refresh
2127 **/
2128 UINT8 RhSolution;
2129
2130 /** Offset 0x04F5 - User Manual Threshold
2131 Disabled: Predefined threshold will be used.\n
2132 Enabled: User Input will be used.
2133 $EN_DIS
2134 **/
2135 UINT8 UserThresholdEnable;
2136
2137 /** Offset 0x04F6 - User Manual Budget
2138 Disabled: Configuration of memories will defined the Budget value.\n
2139 Enabled: User Input will be used.
2140 $EN_DIS
2141 **/
2142 UINT8 UserBudgetEnable;
2143
2144 /** Offset 0x04F7 - TcritMax
2145 Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
2146 has to be greater than THIGHMax .\n
2147 Critical temperature will be TcritMax
2148 **/
2149 UINT8 TsodTcritMax;
2150
2151 /** Offset 0x04F8 - Event mode
2152 Disable:Comparator mode.\n
2153 Enable:Interrupt mode
2154 $EN_DIS
2155 **/
2156 UINT8 TsodEventMode;
2157
2158 /** Offset 0x04F9 - EVENT polarity
2159 Disable:Active LOW.\n
2160 Enable:Active HIGH
2161 $EN_DIS
2162 **/
2163 UINT8 TsodEventPolarity;
2164
2165 /** Offset 0x04FA - Critical event only
2166 Disable:Trips on alarm or critical.\n
2167 Enable:Trips only if criticaal temperature is reached
2168 $EN_DIS
2169 **/
2170 UINT8 TsodCriticalEventOnly;
2171
2172 /** Offset 0x04FB - Event output control
2173 Disable:Event output disable.\n
2174 Enable:Event output enabled
2175 $EN_DIS
2176 **/
2177 UINT8 TsodEventOutputControl;
2178
2179 /** Offset 0x04FC - Alarm window lock bit
2180 Disable:Alarm trips are not locked and can be changed.\n
2181 Enable:Alarm trips are locked and cannot be changed
2182 $EN_DIS
2183 **/
2184 UINT8 TsodAlarmwindowLockBit;
2185
2186 /** Offset 0x04FD - Critical trip lock bit
2187 Disable:Critical trip is not locked and can be changed.\n
2188 Enable:Critical trip is locked and cannot be changed
2189 $EN_DIS
2190 **/
2191 UINT8 TsodCriticaltripLockBit;
2192
2193 /** Offset 0x04FE - Shutdown mode
2194 Disable:Temperature sensor enable.\n
2195 Enable:Temperature sensor disable
2196 $EN_DIS
2197 **/
2198 UINT8 TsodShutdownMode;
2199
2200 /** Offset 0x04FF - ThighMax
2201 Thigh = ThighMax (Default is 93)
2202 **/
2203 UINT8 TsodThigMax;
2204
2205 /** Offset 0x0500 - User Manual Thig and Tcrit
2206 Disabled(Default): Temperature will be given by the configuration of memories and
2207 1x or 2xrefresh rate.\n
2208 Enabled: User Input will define for Thigh and Tcrit.
2209 $EN_DIS
2210 **/
2211 UINT8 TsodManualEnable;
2212
2213 /** Offset 0x0501 - Force OLTM or 2X Refresh when needed
2214 Disabled(Default): = Force OLTM.\n
2215 Enabled: = Force 2x Refresh.
2216 $EN_DIS
2217 **/
2218 UINT8 ForceOltmOrRefresh2x;
2219
2220 /** Offset 0x0502 - Pwr Down Idle Timer
2221 The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
2222 AUTO: 64 for ULX/ULT, 128 for DT/Halo
2223 **/
2224 UINT8 PwdwnIdleCounter;
2225
2226 /** Offset 0x0503 - Bitmask of ranks that have CA bus terminated
2227 Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
2228 Rank0 is terminating and Rank1 is non-terminating</b>
2229 **/
2230 UINT8 CmdRanksTerminated;
2231
2232 /** Offset 0x0504 - GDXC MOT enable
2233 GDXC MOT enable.
2234 $EN_DIS
2235 **/
2236 UINT8 GdxcEnable;
2237
2238 /** Offset 0x0505 - PcdSerialDebugLevel
2239 Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
2240 Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
2241 Info & Verbose.
2242 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
2243 Error Warnings and Info, 5:Load Error Warnings Info and Verbose
2244 **/
2245 UINT8 PcdSerialDebugLevel;
2246
2247 /** Offset 0x0506 - Fivr Faults
2248 Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
2249 $EN_DIS
2250 **/
2251 UINT8 FivrFaults;
2252
2253 /** Offset 0x0507 - Fivr Efficiency
2254 Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
2255 $EN_DIS
2256 **/
2257 UINT8 FivrEfficiency;
2258
2259 /** Offset 0x0508 - Safe Mode Support
2260 This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
2261 $EN_DIS
2262 **/
2263 UINT8 SafeMode;
2264
2265 /** Offset 0x0509 - Ask MRC to clear memory content
2266 Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
2267 $EN_DIS
2268 **/
2269 UINT8 CleanMemory;
2270
2271 /** Offset 0x050A - LpDdrDqDqsReTraining
2272 Enables/Disable LpDdrDqDqsReTraining
2273 $EN_DIS
2274 **/
2275 UINT8 LpDdrDqDqsReTraining;
2276
2277 /** Offset 0x050B - Post Code Output Port
2278 This option configures Post Code Output Port
2279 **/
2280 UINT16 PostCodeOutputPort;
2281
2282 /** Offset 0x050D - RMTLoopCount
2283 Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
2284 **/
2285 UINT8 RMTLoopCount;
2286
2287 /** Offset 0x050E - BER Support
2288 Enable/Disable the Rank Margin Tool interpolation/extrapolation.
2289 0:Disable, 1:Enable
2290 **/
2291 UINT8 EnBER;
2292
2293 /** Offset 0x050F - Dual Dimm Per-Channel Board Type
2294 Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used
2295 to limit maximum frequency for some SKUs.
2296 0:1DPC, 1:2DPC
2297 **/
2298 UINT8 DualDimmPerChannelBoardType;
2299
2300 /** Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation
2301 Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population.
2302 Disable(Default)=0, Enable=1
2303 $EN_DIS
2304 **/
2305 UINT8 Ddr4MixedUDimm2DpcLimit;
2306
2307 /** Offset 0x0511 - CFL Reserved
2308 Reserved FspmConfig CFL
2309 $EN_DIS
2310 **/
2311 UINT8 ReservedFspmUpdCfl[2];
2312
2313 /** Offset 0x0513 - Memory Test on Warm Boot
2314 Run Base Memory Test on Warm Boot
2315 0:Disable, 1:Enable
2316 **/
2317 UINT8 MemTestOnWarmBoot;
2318
2319 /** Offset 0x0514 - Throttler CKEMin Timer - LPDDR
2320 Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T +
2321 BYTE_LENGTH (4). Default is 0x40
2322 **/
2323 UINT8 ThrtCkeMinTmrLpddr;
2324
2325 /** Offset 0x0515
2326 **/
2327 UINT8 ReservedFspmUpd[10];
2328 } FSP_M_CONFIG;
2329
2330 /** Fsp M Test Configuration
2331 **/
2332 typedef struct {
2333
2334 /** Offset 0x0520
2335 **/
2336 UINT32 Signature;
2337
2338 /** Offset 0x0524 - Skip external display device scanning
2339 Enable: Do not scan for external display device, Disable (Default): Scan external
2340 display devices
2341 $EN_DIS
2342 **/
2343 UINT8 SkipExtGfxScan;
2344
2345 /** Offset 0x0525 - Generate BIOS Data ACPI Table
2346 Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
2347 $EN_DIS
2348 **/
2349 UINT8 BdatEnable;
2350
2351 /** Offset 0x0526 - Detect External Graphics device for LegacyOpROM
2352 Detect and report if external graphics device only support LegacyOpROM or not (to
2353 support CSM auto-enable). Enable(Default)=1, Disable=0
2354 $EN_DIS
2355 **/
2356 UINT8 ScanExtGfxForLegacyOpRom;
2357
2358 /** Offset 0x0527 - Lock PCU Thermal Management registers
2359 Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
2360 $EN_DIS
2361 **/
2362 UINT8 LockPTMregs;
2363
2364 /** Offset 0x0528 - DMI Max Link Speed
2365 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
2366 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
2367 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
2368 **/
2369 UINT8 DmiMaxLinkSpeed;
2370
2371 /** Offset 0x0529 - DMI Equalization Phase 2
2372 DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
2373 AUTO - Use the current default method
2374 0:Disable phase2, 1:Enable phase2, 2:Auto
2375 **/
2376 UINT8 DmiGen3EqPh2Enable;
2377
2378 /** Offset 0x052A - DMI Gen3 Equalization Phase3
2379 DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
2380 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
2381 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
2382 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
2383 Phase1), Disabled(0x4): Bypass Equalization Phase 3
2384 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
2385 **/
2386 UINT8 DmiGen3EqPh3Method;
2387
2388 /** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0.
2389 Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
2390 Enable phase 2, Auto(0x2)(Default): Use the current default method
2391 0:Disable, 1:Enable, 2:Auto
2392 **/
2393 UINT8 Peg0Gen3EqPh2Enable;
2394
2395 /** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1.
2396 Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
2397 Enable phase 2, Auto(0x2)(Default): Use the current default method
2398 0:Disable, 1:Enable, 2:Auto
2399 **/
2400 UINT8 Peg1Gen3EqPh2Enable;
2401
2402 /** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2.
2403 Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
2404 Enable phase 2, Auto(0x2)(Default): Use the current default method
2405 0:Disable, 1:Enable, 2:Auto
2406 **/
2407 UINT8 Peg2Gen3EqPh2Enable;
2408
2409 /** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3.
2410 Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
2411 Enable phase 2, Auto(0x2)(Default): Use the current default method
2412 0:Disable, 1:Enable, 2:Auto
2413 **/
2414 UINT8 Peg3Gen3EqPh2Enable;
2415
2416 /** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0.
2417 PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
2418 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
2419 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
2420 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
2421 Phase1), Disabled(0x4): Bypass Equalization Phase 3
2422 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
2423 **/
2424 UINT8 Peg0Gen3EqPh3Method;
2425
2426 /** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1.
2427 PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
2428 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
2429 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
2430 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
2431 Phase1), Disabled(0x4): Bypass Equalization Phase 3
2432 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
2433 **/
2434 UINT8 Peg1Gen3EqPh3Method;
2435
2436 /** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2.
2437 PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
2438 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
2439 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
2440 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
2441 Phase1), Disabled(0x4): Bypass Equalization Phase 3
2442 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
2443 **/
2444 UINT8 Peg2Gen3EqPh3Method;
2445
2446 /** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3.
2447 PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
2448 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
2449 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
2450 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
2451 Phase1), Disabled(0x4): Bypass Equalization Phase 3
2452 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
2453 **/
2454 UINT8 Peg3Gen3EqPh3Method;
2455
2456 /** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
2457 Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
2458 Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
2459 $EN_DIS
2460 **/
2461 UINT8 PegGen3ProgramStaticEq;
2462
2463 /** Offset 0x0534 - PEG Gen3 SwEq Always Attempt
2464 Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
2465 Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
2466 and generate new EQ values every boot, not recommended
2467 0:Disable, 1:Enable
2468 **/
2469 UINT8 Gen3SwEqAlwaysAttempt;
2470
2471 /** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq
2472 Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
2473 Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
2474 current default method (Default)Auto will test Presets 7, 3, and 5. It is possible
2475 for this default to change over time;using Auto will ensure Reference Code always
2476 uses the latest default settings
2477 0:P7 P3 P5, 1:P0 to P9, 2:Auto
2478 **/
2479 UINT8 Gen3SwEqNumberOfPresets;
2480
2481 /** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
2482 Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
2483 Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
2484 Use the current default
2485 0:Disable, 1:Enable, 2:Auto
2486 **/
2487 UINT8 Gen3SwEqEnableVocTest;
2488
2489 /** Offset 0x0537 - PCIe Rx Compliance Testing Mode
2490 Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
2491 PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
2492 it should only be set when doing PCIe compliance testing
2493 $EN_DIS
2494 **/
2495 UINT8 PegRxCemTestingMode;
2496
2497 /** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
2498 the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0
2499 **/
2500 UINT8 PegRxCemLoopbackLane;
2501
2502 /** Offset 0x0539 - Generate PCIe BDAT Margin Table
2503 Set this policy to enable the generation and addition of PCIe margin data to the
2504 BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
2505 data generation, Enable(0x1): Generate PCIe BDAT margin data
2506 $EN_DIS
2507 **/
2508 UINT8 PegGenerateBdatMarginTable;
2509
2510 /** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing
2511 Set this policy to enable the generation and addition of PCIe margin data to the
2512 BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
2513 Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
2514 compliance testing
2515 $EN_DIS
2516 **/
2517 UINT8 PegRxCemNonProtocolAwareness;
2518
2519 /** Offset 0x053B - PCIe Override RxCTLE
2520 Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
2521 Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
2522 peak values unmodified
2523 $EN_DIS
2524 **/
2525 UINT8 PegGen3RxCtleOverride;
2526
2527 /** Offset 0x053C - Rsvd
2528 Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
2529 Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
2530 peak values unmodified
2531 $EN_DIS
2532 **/
2533 UINT8 PegGen3Rsvd;
2534
2535 /** Offset 0x053D - PEG Gen3 Root port preset values per lane
2536 Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
2537 **/
2538 UINT8 PegGen3RootPortPreset[20];
2539
2540 /** Offset 0x0551 - PEG Gen3 End port preset values per lane
2541 Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
2542 **/
2543 UINT8 PegGen3EndPointPreset[20];
2544
2545 /** Offset 0x0565 - PEG Gen3 End port Hint values per lane
2546 Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
2547 **/
2548 UINT8 PegGen3EndPointHint[20];
2549
2550 /** Offset 0x0579
2551 **/
2552 UINT8 UnusedUpdSpace8;
2553
2554 /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
2555 Range: 0-65535, default is 1000. @warning Do not change from the default
2556 **/
2557 UINT16 Gen3SwEqJitterDwellTime;
2558
2559 /** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization
2560 Range: 0-65535, default is 1. @warning Do not change from the default
2561 **/
2562 UINT16 Gen3SwEqJitterErrorTarget;
2563
2564 /** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization
2565 Range: 0-65535, default is 10000. @warning Do not change from the default
2566 **/
2567 UINT16 Gen3SwEqVocDwellTime;
2568
2569 /** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization
2570 Range: 0-65535, default is 2. @warning Do not change from the default
2571 **/
2572 UINT16 Gen3SwEqVocErrorTarget;
2573
2574 /** Offset 0x0582 - Panel Power Enable
2575 Control for enabling/disabling VDD force bit (Required only for early enabling of
2576 eDP panel). 0=Disable, 1(Default)=Enable
2577 $EN_DIS
2578 **/
2579 UINT8 PanelPowerEnable;
2580
2581 /** Offset 0x0583 - BdatTestType
2582 Indicates the type of Memory Training data to populate into the BDAT ACPI table.
2583 0:Rank Margin Tool, 1:Margin2D
2584 **/
2585 UINT8 BdatTestType;
2586
2587 /** Offset 0x0584 - SaPreMemTestRsvd
2588 Reserved for SA Pre-Mem Test
2589 $EN_DIS
2590 **/
2591 UINT8 SaPreMemTestRsvd[12];
2592
2593 /** Offset 0x0590 - TotalFlashSize
2594 Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
2595 **/
2596 UINT16 TotalFlashSize;
2597
2598 /** Offset 0x0592 - BiosSize
2599 Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
2600 **/
2601 UINT16 BiosSize;
2602
2603 /** Offset 0x0594 - TxtAcheckRequest
2604 Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
2605 $EN_DIS
2606 **/
2607 UINT8 TxtAcheckRequest;
2608
2609 /** Offset 0x0595 - SecurityTestRsvd
2610 Reserved for SA Pre-Mem Test
2611 $EN_DIS
2612 **/
2613 UINT8 SecurityTestRsvd[3];
2614
2615 /** Offset 0x0598 - Smbus dynamic power gating
2616 Disable or Enable Smbus dynamic power gating.
2617 $EN_DIS
2618 **/
2619 UINT8 SmbusDynamicPowerGating;
2620
2621 /** Offset 0x0599 - Disable and Lock Watch Dog Register
2622 Set 1 to clear WDT status, then disable and lock WDT registers.
2623 $EN_DIS
2624 **/
2625 UINT8 WdtDisableAndLock;
2626
2627 /** Offset 0x059A - SMBUS SPD Write Disable
2628 Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
2629 Disable bit. For security recommendations, SPD write disable bit must be set.
2630 $EN_DIS
2631 **/
2632 UINT8 SmbusSpdWriteDisable;
2633
2634 /** Offset 0x059B - ChipsetInit HECI message
2635 DEPRECATED
2636 $EN_DIS
2637 **/
2638 UINT8 ChipsetInitMessage;
2639
2640 /** Offset 0x059C - Bypass ChipsetInit sync reset.
2641 DEPRECATED
2642 $EN_DIS
2643 **/
2644 UINT8 BypassPhySyncReset;
2645
2646 /** Offset 0x059D - Force ME DID Init Status
2647 Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
2648 ME DID init stat value
2649 $EN_DIS
2650 **/
2651 UINT8 DidInitStat;
2652
2653 /** Offset 0x059E - CPU Replaced Polling Disable
2654 Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
2655 $EN_DIS
2656 **/
2657 UINT8 DisableCpuReplacedPolling;
2658
2659 /** Offset 0x059F - ME DID Message
2660 Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
2661 the DID message from being sent)
2662 $EN_DIS
2663 **/
2664 UINT8 SendDidMsg;
2665
2666 /** Offset 0x05A0 - Retry mechanism for HECI APIs
2667 Test, 0: disable, 1: enable, Enable/Disable HECI retry.
2668 $EN_DIS
2669 **/
2670 UINT8 DisableHeciRetry;
2671
2672 /** Offset 0x05A1 - Check HECI message before send
2673 Test, 0: disable, 1: enable, Enable/Disable message check.
2674 $EN_DIS
2675 **/
2676 UINT8 DisableMessageCheck;
2677
2678 /** Offset 0x05A2 - Skip MBP HOB
2679 Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
2680 $EN_DIS
2681 **/
2682 UINT8 SkipMbpHob;
2683
2684 /** Offset 0x05A3 - HECI2 Interface Communication
2685 Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
2686 $EN_DIS
2687 **/
2688 UINT8 HeciCommunication2;
2689
2690 /** Offset 0x05A4 - Enable KT device
2691 Test, 0: disable, 1: enable, Enable or Disable KT device.
2692 $EN_DIS
2693 **/
2694 UINT8 KtDeviceEnable;
2695
2696 /** Offset 0x05A5 - tRd2RdSG
2697 Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54.
2698 **/
2699 UINT8 tRd2RdSG;
2700
2701 /** Offset 0x05A6 - tRd2RdDG
2702 Delay between Read-to-Read commands in different Bank Group for DDR4. All other
2703 DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
2704 **/
2705 UINT8 tRd2RdDG;
2706
2707 /** Offset 0x05A7 - tRd2RdDR
2708 Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.
2709 **/
2710 UINT8 tRd2RdDR;
2711
2712 /** Offset 0x05A8 - tRd2RdDD
2713 Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
2714 **/
2715 UINT8 tRd2RdDD;
2716
2717 /** Offset 0x05A9 - tWr2RdSG
2718 Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86.
2719 **/
2720 UINT8 tWr2RdSG;
2721
2722 /** Offset 0x05AA - tWr2RdDG
2723 Delay between Write-to-Read commands in different Bank Group for DDR4. All other
2724 DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
2725 **/
2726 UINT8 tWr2RdDG;
2727
2728 /** Offset 0x05AB - tWr2RdDR
2729 Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.
2730 **/
2731 UINT8 tWr2RdDR;
2732
2733 /** Offset 0x05AC - tWr2RdDD
2734 Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
2735 **/
2736 UINT8 tWr2RdDD;
2737
2738 /** Offset 0x05AD - tWr2WrSG
2739 Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
2740 **/
2741 UINT8 tWr2WrSG;
2742
2743 /** Offset 0x05AE - tWr2WrDG
2744 Delay between Write-to-Write commands in different Bank Group for DDR4. All other
2745 DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
2746 **/
2747 UINT8 tWr2WrDG;
2748
2749 /** Offset 0x05AF - tWr2WrDR
2750 Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.
2751 **/
2752 UINT8 tWr2WrDR;
2753
2754 /** Offset 0x05B0 - tWr2WrDD
2755 Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
2756 **/
2757 UINT8 tWr2WrDD;
2758
2759 /** Offset 0x05B1 - tRd2WrSG
2760 Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
2761 **/
2762 UINT8 tRd2WrSG;
2763
2764 /** Offset 0x05B2 - tRd2WrDG
2765 Delay between Read-to-Write commands in different Bank Group for DDR4. All other
2766 DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
2767 **/
2768 UINT8 tRd2WrDG;
2769
2770 /** Offset 0x05B3 - tRd2WrDR
2771 Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.
2772 **/
2773 UINT8 tRd2WrDR;
2774
2775 /** Offset 0x05B4 - tRd2WrDD
2776 Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
2777 **/
2778 UINT8 tRd2WrDD;
2779
2780 /** Offset 0x05B5 - tRRD_L
2781 Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31
2782 **/
2783 UINT8 tRRD_L;
2784
2785 /** Offset 0x05B6 - tRRD_S
2786 Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0:
2787 AUTO, max: 31
2788 **/
2789 UINT8 tRRD_S;
2790
2791 /** Offset 0x05B7 - tWTR_L
2792 Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0:
2793 AUTO, max: 60
2794 **/
2795 UINT8 tWTR_L;
2796
2797 /** Offset 0x05B8 - tWTR_S
2798 Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only.
2799 0: AUTO, max: 28
2800 **/
2801 UINT8 tWTR_S;
2802
2803 /** Offset 0x05B9
2804 **/
2805 UINT8 ReservedFspmTestUpd[3];
2806 } FSP_M_TEST_CONFIG;
2807
2808 /** Fsp M UPD Configuration
2809 **/
2810 typedef struct {
2811
2812 /** Offset 0x0000
2813 **/
2814 FSP_UPD_HEADER FspUpdHeader;
2815
2816 /** Offset 0x0020
2817 **/
2818 FSPM_ARCH_UPD FspmArchUpd;
2819
2820 /** Offset 0x0040
2821 **/
2822 FSP_M_CONFIG FspmConfig;
2823
2824 /** Offset 0x051F
2825 **/
2826 UINT8 UnusedUpdSpace7;
2827
2828 /** Offset 0x0520
2829 **/
2830 FSP_M_TEST_CONFIG FspmTestConfig;
2831
2832 /** Offset 0x05BC
2833 **/
2834 UINT32 UpdTerminator;
2835 } FSPM_UPD;
2836
2837 #pragma pack()
2838
2839 #endif
FSP_M_CONFIG::RMC
UINT8 RMC
Offset 0x0497 - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS.
Definition: FspmUpd.h:1660
FSP_M_CONFIG::DciUsb3TypecUfpDbg
UINT8 DciUsb3TypecUfpDbg
Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support This BIOS option enables kernel and...
Definition: FspmUpd.h:222
FSP_M_TEST_CONFIG::BdatTestType
UINT8 BdatTestType
Offset 0x0583 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACP...
Definition: FspmUpd.h:2585
FSP_M_CONFIG::Idd3p
UINT16 Idd3p
Offset 0x04BA - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet...
Definition: FspmUpd.h:1843
FSP_M_CONFIG::MmioSize
UINT16 MmioSize
Offset 0x00A0 - MMIO Size Size of MMIO space reserved for devices.
Definition: FspmUpd.h:176
FSP_M_TEST_CONFIG::Gen3SwEqJitterDwellTime
UINT16 Gen3SwEqJitterDwellTime
Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000.
Definition: FspmUpd.h:2557
FSP_M_TEST_CONFIG::Signature
UINT32 Signature
Offset 0x0520.
Definition: FspmUpd.h:2336
FSP_M_CONFIG::TvbRatioClipping
UINT8 TvbRatioClipping
Offset 0x0144 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled.
Definition: FspmUpd.h:725
FSP_M_CONFIG::CleanMemory
UINT8 CleanMemory
Offset 0x0509 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memor...
Definition: FspmUpd.h:2269
FSP_M_CONFIG::TsodEventPolarity
UINT8 TsodEventPolarity
Offset 0x04F9 - EVENT polarity Disable:Active LOW.
Definition: FspmUpd.h:2163
FSP_M_CONFIG::WarmThresholdCh0Dimm1
UINT8 WarmThresholdCh0Dimm1
Offset 0x04CA - Warm Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1912
FSP_M_CONFIG::GtusVoltageMode
UINT8 GtusVoltageMode
Offset 0x01F4 - GT unslice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
Definition: FspmUpd.h:899
FSP_M_CONFIG::IedSize
UINT32 IedSize
Offset 0x0098 - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB...
Definition: FspmUpd.h:165
FSP_M_CONFIG::DllBwEn1
UINT8 DllBwEn1
Offset 0x00EF - DllBwEn[1] DllBwEn[1], for 1333 (0..7)
Definition: FspmUpd.h:450
FSP_M_CONFIG::WarmThresholdCh0Dimm0
UINT8 WarmThresholdCh0Dimm0
Offset 0x04C9 - Warm Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1907
FSP_M_CONFIG::RingVoltageOffset
UINT16 RingVoltageOffset
Offset 0x0220 - Ring Turbo voltage Offset The voltage offset applied to the ring while operating in t...
Definition: FspmUpd.h:1098
FSP_M_CONFIG::SaIpuEnable
UINT8 SaIpuEnable
Offset 0x01F1 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU $EN_DIS...
Definition: FspmUpd.h:881
FSP_M_TEST_CONFIG::DmiMaxLinkSpeed
UINT8 DmiMaxLinkSpeed
Offset 0x0528 - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:2369
FSP_M_CONFIG::JtagC10PowerGateDisable
UINT8 JtagC10PowerGateDisable
Offset 0x020E - Set JTAG power in C10 and deeper power states False: JTAG is power gated in C10 state...
Definition: FspmUpd.h:1021
FSP_M_CONFIG::RaplLim1WindY
UINT8 RaplLim1WindY
Offset 0x04C4 - RAPL PL 1 WindowY Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) ...
Definition: FspmUpd.h:1892
FSP_M_CONFIG::RDTC2D
UINT8 RDTC2D
Offset 0x048D - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS...
Definition: FspmUpd.h:1600
FSP_M_CONFIG::PcieImrSize
UINT16 PcieImrSize
Offset 0x0456 - Size of PCIe IMR.
Definition: FspmUpd.h:1389
FSP_M_CONFIG::OcSupport
UINT8 OcSupport
Offset 0x0203 - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS...
Definition: FspmUpd.h:951
FSP_M_CONFIG::RaplLim1Ena
UINT8 RaplLim1Ena
Offset 0x04A7 - RAPL PL 1 enable Enables/Disable RAPL PL 1 enable $EN_DIS.
Definition: FspmUpd.h:1759
FSP_M_CONFIG::GtExtraTurboVoltage
UINT16 GtExtraTurboVoltage
Offset 0x01EB - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
Definition: FspmUpd.h:858
FSP_M_CONFIG::WrEnergyCh1Dimm1
UINT8 WrEnergyCh1Dimm1
Offset 0x04EC - Write Energy Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def) ...
Definition: FspmUpd.h:2082
FSP_M_CONFIG::GtusExtraTurboVoltage
UINT16 GtusExtraTurboVoltage
Offset 0x01F9 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
Definition: FspmUpd.h:914
FSP_M_CONFIG::Peg1MaxLinkSpeed
UINT8 Peg1MaxLinkSpeed
Offset 0x0118 - PEG 1 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:608
FSP_M_CONFIG::LCT
UINT8 LCT
Offset 0x0491 - Late Command Training Enables/Disable Late Command Training $EN_DIS.
Definition: FspmUpd.h:1624
FSP_M_TEST_CONFIG::Peg0Gen3EqPh2Enable
UINT8 Peg0Gen3EqPh2Enable
Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0.
Definition: FspmUpd.h:2393
FSP_M_CONFIG::MrcFastBoot
UINT8 MrcFastBoot
Offset 0x0095 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC $EN_DIS.
Definition: FspmUpd.h:145
FSP_M_CONFIG::GtusVoltageOffset
UINT16 GtusVoltageOffset
Offset 0x01F5 - voltage offset applied to GT unslice 0(Default)=Minimal, 2000=Maximum.
Definition: FspmUpd.h:904
FSP_M_TEST_CONFIG::tRd2RdDD
UINT8 tRd2RdDD
Offset 0x05A8 - tRd2RdDD Delay between Read-to-Read commands in different DIMMs.
Definition: FspmUpd.h:2715
FSP_M_CONFIG::MemorySpdDataLen
UINT16 MemorySpdDataLen
Offset 0x0058 - SPD Data Length Length of SPD Data 0x100:256 Bytes, 0x200:512 Bytes.
Definition: FspmUpd.h:87
FSP_M_CONFIG::TsodCriticalEventOnly
UINT8 TsodCriticalEventOnly
Offset 0x04FA - Critical event only Disable:Trips on alarm or critical.
Definition: FspmUpd.h:2170
FSP_M_CONFIG::PcieImrEnabled
UINT8 PcieImrEnabled
Offset 0x0460 - Enable PCIe IMR 0:Disable, 1:Enable $EN_DIS.
Definition: FspmUpd.h:1406
FSP_M_CONFIG::DmiGen3ProgramStaticEq
UINT8 DmiGen3ProgramStaticEq
Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Stati...
Definition: FspmUpd.h:566
FSP_M_CONFIG::tRAS
UINT16 tRAS
Offset 0x00E4 - tRAS RAS Active Time, 0: AUTO, max: 64.
Definition: FspmUpd.h:406
FSP_M_CONFIG::ECT
UINT8 ECT
Offset 0x047A - Early Command Training Enables/Disable Early Command Training $EN_DIS.
Definition: FspmUpd.h:1486
FSP_M_TEST_CONFIG::TotalFlashSize
UINT16 TotalFlashSize
Offset 0x0590 - TotalFlashSize Enable/Disable.
Definition: FspmUpd.h:2596
FSP_M_TEST_CONFIG::Gen3SwEqVocErrorTarget
UINT16 Gen3SwEqVocErrorTarget
Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2.
Definition: FspmUpd.h:2572
FSP_M_CONFIG::RDODTT
UINT8 RDODTT
Offset 0x0489 - Read ODT Training Enables/Disable Read ODT Training $EN_DIS.
Definition: FspmUpd.h:1576
FSP_M_CONFIG::ImrRpSelection
UINT8 ImrRpSelection
Offset 0x0461 - Root port number for IMR.
Definition: FspmUpd.h:1411
FSP_M_CONFIG::RDAPT
UINT8 RDAPT
Offset 0x048B - Read Amplifier Training Enables/Disable Read Amplifier Training $EN_DIS.
Definition: FspmUpd.h:1588
FSP_M_CONFIG::PdEnergyCh1Dimm1
UINT8 PdEnergyCh1Dimm1
Offset 0x04E0 - PowerDown Energy Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off...
Definition: FspmUpd.h:2022
FSP_M_TEST_CONFIG::PegGenerateBdatMarginTable
UINT8 PegGenerateBdatMarginTable
Offset 0x0539 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition...
Definition: FspmUpd.h:2508
FSP_M_TEST_CONFIG::DidInitStat
UINT8 DidInitStat
Offset 0x059D - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels...
Definition: FspmUpd.h:2651
FSP_M_CONFIG::MemorySpdPtr11
UINT32 MemorySpdPtr11
Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 Pointer to SPD data, will be used only when SpdAd...
Definition: FspmUpd.h:81
FSP_M_CONFIG::Peg1MaxLinkWidth
UINT8 Peg1MaxLinkWidth
Offset 0x011C - PEG 1 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4 0:Auto, 1:x1, 2:x2, 3:x4.
Definition: FspmUpd.h:636
FSP_M_CONFIG::WrEnergyCh1Dimm0
UINT8 WrEnergyCh1Dimm0
Offset 0x04EB - Write Energy Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def) ...
Definition: FspmUpd.h:2077
FSP_M_CONFIG::FreqSaGvLow
UINT16 FreqSaGvLow
Offset 0x00C0 - Low Frequency SAGV Low Frequency Selections in Mhz.
Definition: FspmUpd.h:301
FSP_M_CONFIG::EnableCltm
UINT8 EnableCltm
Offset 0x04A0 - Closed Loop Therm Manage Enables/Disable Closed Loop Therm Manage $EN_DIS...
Definition: FspmUpd.h:1716
FSP_M_CONFIG::tREFI
UINT16 tREFI
Offset 0x00E6 - tREFI Refresh Interval, 0: AUTO, max: 65535.
Definition: FspmUpd.h:411
FSP_M_CONFIG::PchPort80Route
UINT8 PchPort80Route
Offset 0x0451 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI...
Definition: FspmUpd.h:1368
FSP_M_CONFIG::InternalGfx
UINT8 InternalGfx
Offset 0x00B9 - Internal Graphics Enable/disable internal graphics.
Definition: FspmUpd.h:261
FSP_M_CONFIG::WRTC1D
UINT8 WRTC1D
Offset 0x0482 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS...
Definition: FspmUpd.h:1534
FSP_M_CONFIG::DIMMRONT
UINT8 DIMMRONT
Offset 0x0486 - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS.
Definition: FspmUpd.h:1558
FSP_M_CONFIG::PdEnergyCh0Dimm0
UINT8 PdEnergyCh0Dimm0
Offset 0x04DD - PowerDown Energy Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off...
Definition: FspmUpd.h:2007
FSP_M_CONFIG::SmramMask
UINT8 SmramMask
Offset 0x0094 - Smram Mask The SMM Regions AB-SEG and/or H-SEG reserved 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both.
Definition: FspmUpd.h:139
FSP_M_CONFIG::Avx3RatioOffset
UINT8 Avx3RatioOffset
Offset 0x0211 - AVX3 Ratio Offset 0(Default)= No Offset.
Definition: FspmUpd.h:1039
FSP_M_CONFIG::GmAdr
UINT32 GmAdr
Offset 0x017A - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO a...
Definition: FspmUpd.h:785
CHIPSET_INIT_INFO
The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CR...
Definition: FspmUpd.h:46
FSP_M_CONFIG::DdrThermalSensor
UINT8 DdrThermalSensor
Offset 0x04AD - LPDDR Thermal Sensor Enables/Disable LPDDR Thermal Sensor $EN_DIS.
Definition: FspmUpd.h:1795
FSP_M_CONFIG::PrimaryDisplay
UINT8 PrimaryDisplay
Offset 0x0177 - Selection of the primary display device 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH...
Definition: FspmUpd.h:771
FSP_M_CONFIG::Idd3n
UINT16 Idd3n
Offset 0x04B8 - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet.
Definition: FspmUpd.h:1837
FSP_M_CONFIG::CoreVoltageOverride
UINT16 CoreVoltageOverride
Offset 0x0214 - core voltage override The core voltage override which is applied to the entire range ...
Definition: FspmUpd.h:1057
FSP_M_CONFIG::SafeMode
UINT8 SafeMode
Offset 0x0508 - Safe Mode Support This option configures the varous items in the IO and MC to be more...
Definition: FspmUpd.h:2263
FSP_M_CONFIG::PcieRpEnableMask
UINT32 PcieRpEnableMask
Offset 0x045C - Enable PCIE RP Mask Enable/disable PCIE Root Ports.
Definition: FspmUpd.h:1400
FSP_M_CONFIG::VddVoltage
UINT16 VddVoltage
Offset 0x00DA - Memory Voltage Memory Voltage Override (Vddq).
Definition: FspmUpd.h:363
FSP_M_CONFIG::WarmThresholdCh1Dimm0
UINT8 WarmThresholdCh1Dimm0
Offset 0x04CB - Warm Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1917
FSP_M_CONFIG::RsvdSmbusAddressTablePtr
UINT32 RsvdSmbusAddressTablePtr
Offset 0x0458 - Point of RsvdSmbusAddressTable Array of addresses reserved for non-ARP-capable SMBus ...
Definition: FspmUpd.h:1394
FSP_M_CONFIG::HyperThreading
UINT8 HyperThreading
Offset 0x0209 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enab...
Definition: FspmUpd.h:987
FSPM_UPD::UnusedUpdSpace7
UINT8 UnusedUpdSpace7
Offset 0x051F.
Definition: FspmUpd.h:2826
FSP_M_CONFIG::PchHdaEnable
UINT8 PchHdaEnable
Offset 0x00FC - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_...
Definition: FspmUpd.h:510
FSP_M_CONFIG::Heci2BarAddress
UINT32 Heci2BarAddress
Offset 0x0104 - HECI2 BAR address BAR address of HECI2.
Definition: FspmUpd.h:536
FSP_M_CONFIG::WRSRT
UINT8 WRSRT
Offset 0x0488 - Write Slew Rate Training Enables/Disable Write Slew Rate Training $EN_DIS...
Definition: FspmUpd.h:1570
FSP_M_CONFIG::Peg3PowerDownUnusedLanes
UINT8 Peg3PowerDownUnusedLanes
Offset 0x0122 - Power down unused lanes on PEG 3 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
Definition: FspmUpd.h:678
FSP_M_CONFIG::PchTraceHubMemReg1Size
UINT8 PchTraceHubMemReg1Size
Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size Specify size of Pch trace memory region 1 b...
Definition: FspmUpd.h:243
FSP_M_CONFIG::TxtLcpPdBase
UINT64 TxtLcpPdBase
Offset 0x0250 - TxtLcpPdBase Enable/Disable.
Definition: FspmUpd.h:1180
FSP_M_CONFIG::WarmBudgetCh0Dimm0
UINT8 WarmBudgetCh0Dimm0
Offset 0x04D1 - Warm Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1947
FSP_M_CONFIG::Peg2PowerDownUnusedLanes
UINT8 Peg2PowerDownUnusedLanes
Offset 0x0121 - Power down unused lanes on PEG 2 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
Definition: FspmUpd.h:671
FSP_M_CONFIG::UserBudgetEnable
UINT8 UserBudgetEnable
Offset 0x04F6 - User Manual Budget Disabled: Configuration of memories will defined the Budget value...
Definition: FspmUpd.h:2142
FSP_M_CONFIG::EnableOltm
UINT8 EnableOltm
Offset 0x04A1 - Open Loop Therm Manage Enables/Disable Open Loop Therm Manage $EN_DIS.
Definition: FspmUpd.h:1722
FSP_M_CONFIG::TAT
UINT8 TAT
Offset 0x0493 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS...
Definition: FspmUpd.h:1636
FSP_M_TEST_CONFIG::Gen3SwEqJitterErrorTarget
UINT16 Gen3SwEqJitterErrorTarget
Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1.
Definition: FspmUpd.h:2562
FSP_M_CONFIG::ActiveCoreCount
UINT8 ActiveCoreCount
Offset 0x020C - Number of active cores Number of active cores(Depends on Number of cores)...
Definition: FspmUpd.h:1007
FSPM_UPD::FspmArchUpd
FSPM_ARCH_UPD FspmArchUpd
Offset 0x0020.
Definition: FspmUpd.h:2818
FSP_M_CONFIG::OddRatioMode
UINT8 OddRatioMode
Offset 0x00DD - QCLK Odd Ratio Adds 133 or 100 MHz to QCLK frequency, depending on RefClk $EN_DIS...
Definition: FspmUpd.h:376
FSP_M_TEST_CONFIG::Peg0Gen3EqPh3Method
UINT8 Peg0Gen3EqPh3Method
Offset 0x052F - Phase3 EQ method on the PEG 0:1:0.
Definition: FspmUpd.h:2424
FSP_M_TEST_CONFIG::SmbusSpdWriteDisable
UINT8 SmbusSpdWriteDisable
Offset 0x059A - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable.
Definition: FspmUpd.h:2632
FSP_M_CONFIG::MemorySpdPtr00
UINT32 MemorySpdPtr00
Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 Pointer to SPD data, will be used only when SpdAd...
Definition: FspmUpd.h:66
FSP_M_CONFIG::SOT
UINT8 SOT
Offset 0x047B - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS...
Definition: FspmUpd.h:1492
FSP_M_CONFIG::RCVENC1D
UINT8 RCVENC1D
Offset 0x0496 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS...
Definition: FspmUpd.h:1654
FSP_M_CONFIG::SaIpuImrConfiguration
UINT8 SaIpuImrConfiguration
Offset 0x01F2 - IPU IMR Configuration 0:IPU Camera, 1:IPU Gen Default is 0 0:IPU Camera, 1:IPU Gen.
Definition: FspmUpd.h:887
FSP_M_CONFIG::ActEnergyCh1Dimm1
UINT8 ActEnergyCh1Dimm1
Offset 0x04E4 - Activate Energy Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def)
Definition: FspmUpd.h:2042
FSP_M_TEST_CONFIG::PegGen3RxCtleOverride
UINT8 PegGen3RxCtleOverride
Offset 0x053B - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavi...
Definition: FspmUpd.h:2525
FSP_M_TEST_CONFIG::TxtAcheckRequest
UINT8 TxtAcheckRequest
Offset 0x0594 - TxtAcheckRequest Enable/Disable.
Definition: FspmUpd.h:2607
FSP_M_CONFIG::EnBER
UINT8 EnBER
Offset 0x050E - BER Support Enable/Disable the Rank Margin Tool interpolation/extrapolation.
Definition: FspmUpd.h:2291
FSP_M_CONFIG::tRRD
UINT8 tRRD
Offset 0x00E1 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 15.
Definition: FspmUpd.h:396
FSP_M_CONFIG::RDVC2D
UINT8 RDVC2D
Offset 0x048F - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS...
Definition: FspmUpd.h:1612
FSP_M_CONFIG::Peg0MaxLinkWidth
UINT8 Peg0MaxLinkWidth
Offset 0x011B - PEG 0 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8.
Definition: FspmUpd.h:629
FSP_M_CONFIG::PcdSerialIoUartNumber
UINT8 PcdSerialIoUartNumber
Offset 0x0471 - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug.
Definition: FspmUpd.h:1435
FSP_M_CONFIG::RingVoltageOverride
UINT16 RingVoltageOverride
Offset 0x021C - Ring voltage override The ring voltage override which is applied to the entire range ...
Definition: FspmUpd.h:1087
FSP_M_CONFIG::McPllVoltageOffset
UINT8 McPllVoltageOffset
Offset 0x0476 - Memory Controller PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1461
FSP_M_CONFIG::DisableMtrrProgram
UINT8 DisableMtrrProgram
Offset 0x0207 - Program Cache Attributes Program Cache Attributes; 0: Program; 1: Disable Program...
Definition: FspmUpd.h:975
FSP_M_TEST_CONFIG::Peg3Gen3EqPh2Enable
UINT8 Peg3Gen3EqPh2Enable
Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3.
Definition: FspmUpd.h:2414
FSP_M_CONFIG::BiosAcmBase
UINT32 BiosAcmBase
Offset 0x0240 - BiosAcmBase Enable/Disable.
Definition: FspmUpd.h:1160
FSP_M_CONFIG::DIMMODTT
UINT8 DIMMODTT
Offset 0x0485 - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS.
Definition: FspmUpd.h:1552
FSP_M_CONFIG::PostCodeOutputPort
UINT16 PostCodeOutputPort
Offset 0x050B - Post Code Output Port This option configures Post Code Output Port.
Definition: FspmUpd.h:2280
FSP_M_CONFIG::UnusedUpdSpace3
UINT8 UnusedUpdSpace3
Offset 0x00FF.
Definition: FspmUpd.h:526
FSP_M_CONFIG::HotBudgetCh0Dimm0
UINT8 HotBudgetCh0Dimm0
Offset 0x04D5 - Hot Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM...
Definition: FspmUpd.h:1967
FSP_M_TEST_CONFIG::Gen3SwEqAlwaysAttempt
UINT8 Gen3SwEqAlwaysAttempt
Offset 0x0534 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot...
Definition: FspmUpd.h:2469
FSP_M_CONFIG::Ddr4DdpSharedClock
UINT8 Ddr4DdpSharedClock
Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared...
Definition: FspmUpd.h:1801
FSP_M_TEST_CONFIG::tRd2WrDG
UINT8 tRd2WrDG
Offset 0x05B2 - tRd2WrDG Delay between Read-to-Write commands in different Bank Group for DDR4...
Definition: FspmUpd.h:2768
FSP_M_TEST_CONFIG::PegRxCemLoopbackLane
UINT8 PegRxCemLoopbackLane
Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied ...
Definition: FspmUpd.h:2500
FSP_M_CONFIG::IgdDvmt50PreAlloc
UINT8 IgdDvmt50PreAlloc
Offset 0x00B8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graph...
Definition: FspmUpd.h:255
FSP_M_CONFIG::WrEnergyCh0Dimm0
UINT8 WrEnergyCh0Dimm0
Offset 0x04E9 - Write Energy Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def) ...
Definition: FspmUpd.h:2067
FSP_M_TEST_CONFIG::Peg1Gen3EqPh3Method
UINT8 Peg1Gen3EqPh3Method
Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1.
Definition: FspmUpd.h:2434
FSP_M_TEST_CONFIG::SkipMbpHob
UINT8 SkipMbpHob
Offset 0x05A2 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. ...
Definition: FspmUpd.h:2682
FSP_M_CONFIG::TsodShutdownMode
UINT8 TsodShutdownMode
Offset 0x04FE - Shutdown mode Disable:Temperature sensor enable.
Definition: FspmUpd.h:2198
FSP_M_CONFIG::ActEnergyCh0Dimm1
UINT8 ActEnergyCh0Dimm1
Offset 0x04E2 - Activate Energy Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def)
Definition: FspmUpd.h:2032
FSP_M_CONFIG::GtVoltageMode
UINT8 GtVoltageMode
Offset 0x01E5 - GT slice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
Definition: FspmUpd.h:838
FSP_M_CONFIG::GtusVoltageOverride
UINT16 GtusVoltageOverride
Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies 0(...
Definition: FspmUpd.h:909
FSP_M_CONFIG::tRCDtRP
UINT8 tRCDtRP
Offset 0x00E0 - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63.
Definition: FspmUpd.h:391
FSP_M_CONFIG::IdleEnergyCh1Dimm0
UINT8 IdleEnergyCh1Dimm0
Offset 0x04DB - Idle Energy Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on...
Definition: FspmUpd.h:1997
FSP_M_CONFIG::Refresh2X
UINT8 Refresh2X
Offset 0x04F2 - REFRESH_2X_MODE 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC ena...
Definition: FspmUpd.h:2116
FSP_M_CONFIG::BClkFrequency
UINT32 BClkFrequency
Offset 0x04B2 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) 100...
Definition: FspmUpd.h:1819
FSP_M_CONFIG::TxtLcpPdSize
UINT64 TxtLcpPdSize
Offset 0x0258 - TxtLcpPdSize Enable/Disable.
Definition: FspmUpd.h:1185
FSP_M_CONFIG::TgaSize
UINT32 TgaSize
Offset 0x024C - TgaSize Enable/Disable.
Definition: FspmUpd.h:1175
FSP_M_TEST_CONFIG::PegRxCemNonProtocolAwareness
UINT8 PegRxCemNonProtocolAwareness
Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the g...
Definition: FspmUpd.h:2517
FSP_M_TEST_CONFIG::tWTR_S
UINT8 tWTR_S
Offset 0x05B8 - tWTR_S Min Internal Write to Read Command Delay Time for Different Bank Group...
Definition: FspmUpd.h:2801
FSP_M_CONFIG::BootFrequency
UINT8 BootFrequency
Offset 0x020B - Boot frequency Sets the boot frequency starting from reset vector.
Definition: FspmUpd.h:1000
FSP_M_CONFIG::ProbelessTrace
UINT8 ProbelessTrace
Offset 0x00A2 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable.
Definition: FspmUpd.h:183
FSP_M_CONFIG::RDMPRT
UINT8 RDMPRT
Offset 0x047D - Read MPR Training Enables/Disable Read MPR Training $EN_DIS.
Definition: FspmUpd.h:1504
FSP_M_CONFIG::PrmrrSize
UINT32 PrmrrSize
Offset 0x0228 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000.
Definition: FspmUpd.h:1135
FSP_M_TEST_CONFIG::tRd2WrDR
UINT8 tRd2WrDR
Offset 0x05B3 - tRd2WrDR Delay between Read-to-Write commands in different Ranks. ...
Definition: FspmUpd.h:2773
FSP_M_CONFIG::CMDVC
UINT8 CMDVC
Offset 0x0490 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS...
Definition: FspmUpd.h:1618
FSP_M_CONFIG::CoreMaxOcRatio
UINT8 CoreMaxOcRatio
Offset 0x0205 - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increas...
Definition: FspmUpd.h:963
FSP_M_CONFIG::ChHashEnable
UINT8 ChHashEnable
Offset 0x049E - Ch Hash Support Enable/Disable Channel Hash Support.
Definition: FspmUpd.h:1704
FSP_M_CONFIG::WRTC2D
UINT8 WRTC2D
Offset 0x048C - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS...
Definition: FspmUpd.h:1594
FSP_M_CONFIG::HotBudgetCh1Dimm0
UINT8 HotBudgetCh1Dimm0
Offset 0x04D7 - Hot Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM...
Definition: FspmUpd.h:1977
FSP_M_CONFIG::ChHashInterleaveBit
UINT8 ChHashInterleaveBit
Offset 0x04B6 - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode...
Definition: FspmUpd.h:1826
FSP_M_CONFIG::PwdwnIdleCounter
UINT8 PwdwnIdleCounter
Offset 0x0502 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Bu...
Definition: FspmUpd.h:2224
FSP_M_CONFIG::GtPllVoltageOffset
UINT8 GtPllVoltageOffset
Offset 0x0473 - GT PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1446
FSP_M_CONFIG::MemTestOnWarmBoot
UINT8 MemTestOnWarmBoot
Offset 0x0513 - Memory Test on Warm Boot Run Base Memory Test on Warm Boot 0:Disable, 1:Enable.
Definition: FspmUpd.h:2317
FSP_M_CONFIG::RmtPerTask
UINT8 RmtPerTask
Offset 0x0096 - Rank Margin Tool per Task This option enables the user to execute Rank Margin Tool pe...
Definition: FspmUpd.h:152
FSP_M_CONFIG::EnergyScaleFact
UINT8 EnergyScaleFact
Offset 0x04B7 - Energy Scale Factor Energy Scale Factor, Default is 4.
Definition: FspmUpd.h:1831
FSP_M_CONFIG::EpgEnable
UINT8 EpgEnable
Offset 0x04F3 - Energy Performance Gain Enable/disable(default) Energy Performance Gain...
Definition: FspmUpd.h:2122
FSP_M_CONFIG::HotThresholdCh0Dimm0
UINT8 HotThresholdCh0Dimm0
Offset 0x04CD - Hot Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1927
FSP_M_CONFIG::PcdSerialDebugLevel
UINT8 PcdSerialDebugLevel
Offset 0x0505 - PcdSerialDebugLevel Serial Debug Message Level.
Definition: FspmUpd.h:2245
FSP_M_TEST_CONFIG
Fsp M Test Configuration.
Definition: FspmUpd.h:2332
FSP_M_CONFIG::BiosAcmSize
UINT32 BiosAcmSize
Offset 0x0244 - BiosAcmSize Enable/Disable.
Definition: FspmUpd.h:1165
FSP_M_CONFIG::GttMmAdr
UINT32 GttMmAdr
Offset 0x017E - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MMI...
Definition: FspmUpd.h:793
FSP_M_CONFIG::CoreVoltageOffset
UINT16 CoreVoltageOffset
Offset 0x0218 - Core Turbo voltage Offset The voltage offset applied to the core while operating in t...
Definition: FspmUpd.h:1068
FSP_M_CONFIG::Heci3BarAddress
UINT32 Heci3BarAddress
Offset 0x0108 - HECI3 BAR address BAR address of HECI3.
Definition: FspmUpd.h:541
FspUpd.h
Copyright (c) 2018, Intel Corporation.
FSP_M_CONFIG::Peg3Enable
UINT8 Peg3Enable
Offset 0x0116 - Enable/Disable PEG 3 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (...
Definition: FspmUpd.h:594
FSP_M_CONFIG::SaOcSupport
UINT8 SaOcSupport
Offset 0x01E4 - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA...
Definition: FspmUpd.h:832
FSP_M_CONFIG::Peg0PowerDownUnusedLanes
UINT8 Peg0PowerDownUnusedLanes
Offset 0x011F - Power down unused lanes on PEG 0 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
Definition: FspmUpd.h:657
FSP_M_CONFIG::TvbVoltageOptimization
UINT8 TvbVoltageOptimization
Offset 0x0145 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default).
Definition: FspmUpd.h:732
FSP_M_CONFIG::RdEnergyCh0Dimm0
UINT8 RdEnergyCh0Dimm0
Offset 0x04E5 - Read Energy Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def) ...
Definition: FspmUpd.h:2047
FSP_M_CONFIG::RingPllVoltageOffset
UINT8 RingPllVoltageOffset
Offset 0x0474 - Ring PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1451
FSP_M_CONFIG::RaplPwrFlCh1
UINT8 RaplPwrFlCh1
Offset 0x04F0 - Rapl Power Floor Ch1 Power budget ,range[255;0],(0= 5.3W Def)
Definition: FspmUpd.h:2104
FSP_M_CONFIG::MemorySpdPtr10
UINT32 MemorySpdPtr10
Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 Pointer to SPD data, will be used only when SpdAd...
Definition: FspmUpd.h:76
FSP_M_CONFIG::RaplLim1Pwr
UINT16 RaplLim1Pwr
Offset 0x04C7 - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (0= Def)
Definition: FspmUpd.h:1902
FSP_M_CONFIG::ThrtCkeMinTmr
UINT8 ThrtCkeMinTmr
Offset 0x04ED - Throttler CKEMin Timer Timer value for CKEMin, range[255;0].
Definition: FspmUpd.h:2088
FSP_M_CONFIG::Peg0MaxLinkSpeed
UINT8 Peg0MaxLinkSpeed
Offset 0x0117 - PEG 0 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:601
FSP_M_CONFIG::RMT
UINT8 RMT
Offset 0x00C4 - Rank Margin Tool Enable/disable Rank Margin Tool.
Definition: FspmUpd.h:314
FSP_M_CONFIG::EnhancedInterleave
UINT8 EnhancedInterleave
Offset 0x049C - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS...
Definition: FspmUpd.h:1691
FSP_M_CONFIG::CMDSR
UINT8 CMDSR
Offset 0x04BC - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS.
Definition: FspmUpd.h:1849
FSP_M_CONFIG::GdxcMotSize
UINT8 GdxcMotSize
Offset 0x00A4 - GDXC MOT SIZE Size of IOT and MOT is in 8 MB chunks.
Definition: FspmUpd.h:193
FSP_M_CONFIG::FivrEfficiency
UINT8 FivrEfficiency
Offset 0x0507 - Fivr Efficiency Fivr Efficiency Management; 0: Disabled; 1: Enabled.
Definition: FspmUpd.h:2257
FSP_M_CONFIG::ApertureSize
UINT8 ApertureSize
Offset 0x00BA - Aperture Size Select the Aperture Size.
Definition: FspmUpd.h:267
FSPM_UPD::FspmConfig
FSP_M_CONFIG FspmConfig
Offset 0x0040.
Definition: FspmUpd.h:2822
FSP_M_CONFIG::WarmBudgetCh0Dimm1
UINT8 WarmBudgetCh0Dimm1
Offset 0x04D2 - Warm Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1952
FSP_M_CONFIG::IsvtIoPort
UINT8 IsvtIoPort
Offset 0x00F2 - ISVT IO Port Address ISVT IO Port Address.
Definition: FspmUpd.h:465
FSP_M_CONFIG::PlatformDebugConsent
UINT8 PlatformDebugConsent
Offset 0x00AA - Platform Debug Consent To 'opt-in' for debug, please select 'Enabled' with the desire...
Definition: FspmUpd.h:215
FSP_M_TEST_CONFIG::tWr2WrDD
UINT8 tWr2WrDD
Offset 0x05B0 - tWr2WrDD Delay between Write-to-Write commands in different DIMMs.
Definition: FspmUpd.h:2757
FSP_M_CONFIG::MemoryTrace
UINT8 MemoryTrace
Offset 0x049D - Memory Trace Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode.
Definition: FspmUpd.h:1698
FSP_M_TEST_CONFIG::DisableMessageCheck
UINT8 DisableMessageCheck
Offset 0x05A1 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message ch...
Definition: FspmUpd.h:2676
FSP_M_CONFIG::TxtDprMemoryBase
UINT64 TxtDprMemoryBase
Offset 0x0238 - TxtDprMemoryBase Enable/Disable.
Definition: FspmUpd.h:1155
FSP_M_CONFIG::WarmBudgetCh1Dimm0
UINT8 WarmBudgetCh1Dimm0
Offset 0x04D3 - Warm Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1957
FSP_M_CONFIG::RhPrevention
UINT8 RhPrevention
Offset 0x04AB - Enable RH Prevention Enables/Disable RH Prevention $EN_DIS.
Definition: FspmUpd.h:1783
FSP_M_CONFIG::WRVC1D
UINT8 WRVC1D
Offset 0x0483 - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS...
Definition: FspmUpd.h:1540
FSP_M_CONFIG::PeciSxReset
UINT8 PeciSxReset
Offset 0x00F7 - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: D...
Definition: FspmUpd.h:500
FSP_M_CONFIG::PchTraceHubMemReg0Size
UINT8 PchTraceHubMemReg0Size
Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size Specify size of Pch trace memory region 0 b...
Definition: FspmUpd.h:236
FSP_M_CONFIG::RaplPwrFlCh0
UINT8 RaplPwrFlCh0
Offset 0x04EF - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def)
Definition: FspmUpd.h:2099
FSP_M_CONFIG::CMDDSEQ
UINT8 CMDDSEQ
Offset 0x04BD - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equal...
Definition: FspmUpd.h:1855
FSP_M_CONFIG::Peg2MaxLinkWidth
UINT8 Peg2MaxLinkWidth
Offset 0x011D - PEG 2 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
Definition: FspmUpd.h:643
FSP_M_CONFIG::FivrFaults
UINT8 FivrFaults
Offset 0x0506 - Fivr Faults Fivr Faults; 0: Disabled; 1: Enabled.
Definition: FspmUpd.h:2251
FSP_M_TEST_CONFIG::SkipExtGfxScan
UINT8 SkipExtGfxScan
Offset 0x0524 - Skip external display device scanning Enable: Do not scan for external display device...
Definition: FspmUpd.h:2343
FSP_M_CONFIG::TsodCriticaltripLockBit
UINT8 TsodCriticaltripLockBit
Offset 0x04FD - Critical trip lock bit Disable:Critical trip is not locked and can be changed...
Definition: FspmUpd.h:2191
FSP_M_CONFIG::SgDelayAfterHoldReset
UINT16 SgDelayAfterHoldReset
Offset 0x010E - SG dGPU Reset Delay SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds.
Definition: FspmUpd.h:553
FSP_M_CONFIG::BistOnReset
UINT8 BistOnReset
Offset 0x0200 - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
Definition: FspmUpd.h:931
FSP_M_CONFIG::ThrtCkeMinDefeat
UINT8 ThrtCkeMinDefeat
Offset 0x04AA - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS...
Definition: FspmUpd.h:1777
FSPM_UPD::UpdTerminator
UINT32 UpdTerminator
Offset 0x05BC.
Definition: FspmUpd.h:2834
FSP_M_CONFIG::PlatformMemorySize
UINT64 PlatformMemorySize
Offset 0x0040 - Platform Reserved Memory Size The minimum platform memory size required to pass contr...
Definition: FspmUpd.h:61
FSP_M_CONFIG::UnusedUpdSpace6
UINT8 UnusedUpdSpace6
Offset 0x0227.
Definition: FspmUpd.h:1130
FSP_M_CONFIG::tCWL
UINT8 tCWL
Offset 0x00DF - tCWL Min CAS Write Latency Delay Time, 0: AUTO, max: 34.
Definition: FspmUpd.h:386
FSP_M_TEST_CONFIG::KtDeviceEnable
UINT8 KtDeviceEnable
Offset 0x05A4 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device...
Definition: FspmUpd.h:2694
FSP_M_TEST_CONFIG::ChipsetInitMessage
UINT8 ChipsetInitMessage
Offset 0x059B - ChipsetInit HECI message DEPRECATED $EN_DIS.
Definition: FspmUpd.h:2638
FSP_M_CONFIG::DllBwEn2
UINT8 DllBwEn2
Offset 0x00F0 - DllBwEn[2] DllBwEn[2], for 1600 (0..7)
Definition: FspmUpd.h:455
FSP_M_CONFIG::Peg2MaxLinkSpeed
UINT8 Peg2MaxLinkSpeed
Offset 0x0119 - PEG 2 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:615
FSP_M_TEST_CONFIG::PanelPowerEnable
UINT8 PanelPowerEnable
Offset 0x0582 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for ea...
Definition: FspmUpd.h:2579
FSP_M_TEST_CONFIG::tWr2RdDD
UINT8 tWr2RdDD
Offset 0x05AC - tWr2RdDD Delay between Write-to-Read commands in different DIMMs. ...
Definition: FspmUpd.h:2736
FSP_M_CONFIG::ActEnergyCh0Dimm0
UINT8 ActEnergyCh0Dimm0
Offset 0x04E1 - Activate Energy Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def)
Definition: FspmUpd.h:2027
FSP_M_CONFIG::ChHashMask
UINT16 ChHashMask
Offset 0x04B0 - Ch Hash Mask Set the BIT(s) to be included in the XOR function.
Definition: FspmUpd.h:1813
FSP_M_CONFIG::SrefCfgEna
UINT8 SrefCfgEna
Offset 0x04A8 - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS.
Definition: FspmUpd.h:1765
FSP_M_CONFIG::UserPowerWeightsEn
UINT8 UserPowerWeightsEn
Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values Enables...
Definition: FspmUpd.h:1741
FSP_M_CONFIG::PcdDebugInterfaceFlags
UINT8 PcdDebugInterfaceFlags
Offset 0x0470 - Debug Interfaces Debug Interfaces.
Definition: FspmUpd.h:1429
FSP_M_CONFIG::tWR
UINT8 tWR
Offset 0x00EB - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, 34:34, 40:40.
Definition: FspmUpd.h:430
FSP_M_CONFIG::SinitMemorySize
UINT32 SinitMemorySize
Offset 0x022C - SinitMemorySize Enable/Disable.
Definition: FspmUpd.h:1140
FSP_M_CONFIG::TsodAlarmwindowLockBit
UINT8 TsodAlarmwindowLockBit
Offset 0x04FC - Alarm window lock bit Disable:Alarm trips are not locked and can be changed...
Definition: FspmUpd.h:2184
FSP_M_CONFIG::Peg3MaxLinkWidth
UINT8 Peg3MaxLinkWidth
Offset 0x011E - PEG 3 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
Definition: FspmUpd.h:650
CHIPSET_INIT_INFO::Revision
UINT8 Revision
Chipset Init Info Revision.
Definition: FspmUpd.h:47
FSP_M_CONFIG::RingMaxOcRatio
UINT8 RingMaxOcRatio
Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase ...
Definition: FspmUpd.h:981
FSP_M_CONFIG::Peg2Enable
UINT8 Peg2Enable
Offset 0x0115 - Enable/Disable PEG 2 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (...
Definition: FspmUpd.h:587
FSP_M_CONFIG::EnableC6Dram
UINT8 EnableC6Dram
Offset 0x0202 - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate...
Definition: FspmUpd.h:945
FSP_M_CONFIG::GtPsmiSupport
UINT8 GtPsmiSupport
Offset 0x01F3 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE.
Definition: FspmUpd.h:893
FSP_M_CONFIG::CoreVoltageAdaptive
UINT16 CoreVoltageAdaptive
Offset 0x0216 - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu ...
Definition: FspmUpd.h:1063
FSP_M_CONFIG::RhSolution
UINT8 RhSolution
Offset 0x04F4 - Row Hammer Solution Type of method used to prevent Row Hammer.
Definition: FspmUpd.h:2128
FSP_M_CONFIG::tCL
UINT8 tCL
Offset 0x00DE - tCL CAS Latency, 0: AUTO, max: 31.
Definition: FspmUpd.h:381
FSP_M_CONFIG::tWTR
UINT8 tWTR
Offset 0x00EC - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28...
Definition: FspmUpd.h:435
FSP_M_TEST_CONFIG::LockPTMregs
UINT8 LockPTMregs
Offset 0x0527 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers...
Definition: FspmUpd.h:2362
FSP_M_CONFIG::IdleEnergyCh0Dimm0
UINT8 IdleEnergyCh0Dimm0
Offset 0x04D9 - Idle Energy Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on...
Definition: FspmUpd.h:1987
FSP_M_CONFIG::EnablePwrDnLpddr
UINT8 EnablePwrDnLpddr
Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR Enables/Disable DDR PowerDown and idle counter...
Definition: FspmUpd.h:1734
FSP_M_CONFIG::JWRL
UINT8 JWRL
Offset 0x047F - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS.
Definition: FspmUpd.h:1516
FSPM_UPD::FspmTestConfig
FSP_M_TEST_CONFIG FspmTestConfig
Offset 0x0520.
Definition: FspmUpd.h:2830
FSP_M_TEST_CONFIG::WdtDisableAndLock
UINT8 WdtDisableAndLock
Offset 0x0599 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock ...
Definition: FspmUpd.h:2625
FSP_M_CONFIG::RaplLim1WindX
UINT8 RaplLim1WindX
Offset 0x04C3 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) ...
Definition: FspmUpd.h:1887
FSP_M_CONFIG::PegDisableSpreadSpectrumClocking
UINT8 PegDisableSpreadSpectrumClocking
Offset 0x0124 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking...
Definition: FspmUpd.h:693
FSP_M_CONFIG::BclkAdaptiveVoltage
UINT8 BclkAdaptiveVoltage
Offset 0x0212 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequ...
Definition: FspmUpd.h:1046
FSP_M_CONFIG::RaplLim2Pwr
UINT16 RaplLim2Pwr
Offset 0x04C5 - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (222= Def)
Definition: FspmUpd.h:1897
FSP_M_CONFIG::Peg3MaxLinkSpeed
UINT8 Peg3MaxLinkSpeed
Offset 0x011A - PEG 3 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
Definition: FspmUpd.h:622
FSP_M_CONFIG::DisableDimmChannel0
UINT8 DisableDimmChannel0
Offset 0x00C5 - Channel A DIMM Control Channel A DIMM Control Support - Enable or Disable Dimms on Ch...
Definition: FspmUpd.h:320
FSP_M_CONFIG::FreqSaGvMid
UINT16 FreqSaGvMid
Offset 0x00C2 - Mid Frequency SAGV Mid Frequency Selections in Mhz.
Definition: FspmUpd.h:308
FSP_M_TEST_CONFIG::DmiGen3EqPh2Enable
UINT8 DmiGen3EqPh2Enable
Offset 0x0529 - DMI Equalization Phase 2 DMI Equalization Phase 2.
Definition: FspmUpd.h:2376
FSP_M_CONFIG::TxtHeapMemorySize
UINT32 TxtHeapMemorySize
Offset 0x0230 - TxtHeapMemorySize Enable/Disable.
Definition: FspmUpd.h:1145
FSP_M_CONFIG::tRTP
UINT8 tRTP
Offset 0x00EA - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15...
Definition: FspmUpd.h:422
FSP_M_CONFIG::DllBwEn3
UINT8 DllBwEn3
Offset 0x00F1 - DllBwEn[3] DllBwEn[3], for 1867 and up (0..7)
Definition: FspmUpd.h:460
FSP_M_CONFIG::TsegSize
UINT32 TsegSize
Offset 0x009C - Tseg Size Size of SMRAM memory reserved.
Definition: FspmUpd.h:171
FSP_M_CONFIG::EnableSgx
UINT8 EnableSgx
Offset 0x0225 - EnableSgx Enable/Disable.
Definition: FspmUpd.h:1120
FSP_M_CONFIG::TjMaxOffset
UINT8 TjMaxOffset
Offset 0x0222 - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offse...
Definition: FspmUpd.h:1104
FSP_M_CONFIG::TrainTrace
UINT8 TrainTrace
Offset 0x0097 - Training Trace This option enables the trained state tracing feature in MRC...
Definition: FspmUpd.h:159
FSP_M_CONFIG::LpDdrDqDqsReTraining
UINT8 LpDdrDqDqsReTraining
Offset 0x050A - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining $EN_DIS.
Definition: FspmUpd.h:2275
FSP_M_CONFIG::CaVrefConfig
UINT8 CaVrefConfig
Offset 0x0093 - VREF_CA CA Vref routing: board-dependent 0:VREF_CA goes to both CH_A and CH_B...
Definition: FspmUpd.h:133
FSP_M_TEST_CONFIG::UnusedUpdSpace8
UINT8 UnusedUpdSpace8
Offset 0x0579.
Definition: FspmUpd.h:2552
FSP_M_CONFIG::HeciTimeouts
UINT8 HeciTimeouts
Offset 0x00FE - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS...
Definition: FspmUpd.h:522
FSP_M_CONFIG::PchSmbusIoBase
UINT16 PchSmbusIoBase
Offset 0x0454 - SMBUS Base Address SMBUS Base Address (IO space).
Definition: FspmUpd.h:1384
MemInfoHob.h
This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Mem...
FSP_M_TEST_CONFIG::SmbusDynamicPowerGating
UINT8 SmbusDynamicPowerGating
Offset 0x0598 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating.
Definition: FspmUpd.h:2619
FSP_M_CONFIG::HotBudgetCh1Dimm1
UINT8 HotBudgetCh1Dimm1
Offset 0x04D8 - Hot Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM...
Definition: FspmUpd.h:1982
FSP_M_CONFIG::PcdIsaSerialUartBase
UINT8 PcdIsaSerialUartBase
Offset 0x0472 - ISA Serial Base selection Select ISA Serial Base address.
Definition: FspmUpd.h:1441
FSP_M_CONFIG::PchNumRsvdSmbusAddresses
UINT8 PchNumRsvdSmbusAddresses
Offset 0x0453 - Number of RsvdSmbusAddressTable.
Definition: FspmUpd.h:1379
FSP_M_CONFIG::tFAW
UINT16 tFAW
Offset 0x00E2 - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63.
Definition: FspmUpd.h:401
FSP_M_CONFIG::Heci1BarAddress
UINT32 Heci1BarAddress
Offset 0x0100 - HECI1 BAR address BAR address of HECI1.
Definition: FspmUpd.h:531
FSP_M_TEST_CONFIG::Gen3SwEqNumberOfPresets
UINT8 Gen3SwEqNumberOfPresets
Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq pres...
Definition: FspmUpd.h:2479
FSP_M_CONFIG::RealtimeMemoryTiming
UINT8 RealtimeMemoryTiming
Offset 0x01F0 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled.
Definition: FspmUpd.h:875
FSP_M_CONFIG::SmbusArpEnable
UINT8 SmbusArpEnable
Offset 0x0452 - Enable SMBus ARP support Enable SMBus ARP support.
Definition: FspmUpd.h:1374
FSP_M_CONFIG::DisableDimmChannel1
UINT8 DisableDimmChannel1
Offset 0x00C6 - Channel B DIMM Control Channel B DIMM Control Support - Enable or Disable Dimms on Ch...
Definition: FspmUpd.h:326
FSP_M_CONFIG::WrEnergyCh0Dimm1
UINT8 WrEnergyCh0Dimm1
Offset 0x04EA - Write Energy Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def) ...
Definition: FspmUpd.h:2072
FSP_M_CONFIG::GtMaxOcRatio
UINT8 GtMaxOcRatio
Offset 0x01E6 - Maximum GTs turbo ratio override 0(Default)=Minimal/Auto, 60=Maximum.
Definition: FspmUpd.h:843
FSP_M_CONFIG::RaplLim2Lock
UINT8 RaplLim2Lock
Offset 0x04A5 - RAPL PL Lock Enables/Disable RAPL PL Lock $EN_DIS.
Definition: FspmUpd.h:1747
FSP_M_CONFIG::EWRTC2D
UINT8 EWRTC2D
Offset 0x0480 - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS...
Definition: FspmUpd.h:1522
FSP_M_CONFIG::PchTraceHubMode
UINT8 PchTraceHubMode
Offset 0x00AC - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger too...
Definition: FspmUpd.h:229
FSP_M_CONFIG::ActEnergyCh1Dimm0
UINT8 ActEnergyCh1Dimm0
Offset 0x04E3 - Activate Energy Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def)
Definition: FspmUpd.h:2037
FSP_M_CONFIG::RdEnergyCh1Dimm0
UINT8 RdEnergyCh1Dimm0
Offset 0x04E7 - Read Energy Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def) ...
Definition: FspmUpd.h:2057
FSP_M_CONFIG::RCVET
UINT8 RCVET
Offset 0x047E - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS.
Definition: FspmUpd.h:1510
FSP_M_CONFIG::EnCmdRate
UINT8 EnCmdRate
Offset 0x04F1 - Command Rate Support CMD Rate and Limit Support Option.
Definition: FspmUpd.h:2110
FSP_M_TEST_CONFIG::DisableHeciRetry
UINT8 DisableHeciRetry
Offset 0x05A0 - Retry mechanism for HECI APIs Test, 0: disable, 1: enable, Enable/Disable HECI retry...
Definition: FspmUpd.h:2670
FSP_M_CONFIG::MmioSizeAdjustment
UINT16 MmioSizeAdjustment
Offset 0x0110 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size...
Definition: FspmUpd.h:559
FSP_M_CONFIG::CmdRanksTerminated
UINT8 CmdRanksTerminated
Offset 0x0503 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that...
Definition: FspmUpd.h:2230
FSP_M_CONFIG::Peg1Enable
UINT8 Peg1Enable
Offset 0x0114 - Enable/Disable PEG 1 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (...
Definition: FspmUpd.h:580
FSP_M_TEST_CONFIG::tRd2WrDD
UINT8 tRd2WrDD
Offset 0x05B4 - tRd2WrDD Delay between Read-to-Write commands in different DIMMs. ...
Definition: FspmUpd.h:2778
FSP_M_CONFIG::UnusedUpdSpace0
UINT8 UnusedUpdSpace0
Offset 0x00BD.
Definition: FspmUpd.h:286
FSP_M_CONFIG::DqPinsInterleaved
UINT8 DqPinsInterleaved
Offset 0x0092 - Dqs Pins Interleaved Setting Indicates DqPinsInterleaved setting: board-dependent $EN...
Definition: FspmUpd.h:126
FSP_M_CONFIG::RDTC1D
UINT8 RDTC1D
Offset 0x0484 - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS...
Definition: FspmUpd.h:1546
FSP_M_TEST_CONFIG::DisableCpuReplacedPolling
UINT8 DisableCpuReplacedPolling
Offset 0x059E - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disable...
Definition: FspmUpd.h:2657
FSP_M_CONFIG::tRFC
UINT16 tRFC
Offset 0x00E8 - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 1023.
Definition: FspmUpd.h:416
FSP_M_TEST_CONFIG::ScanExtGfxForLegacyOpRom
UINT8 ScanExtGfxForLegacyOpRom
Offset 0x0526 - Detect External Graphics device for LegacyOpROM Detect and report if external graphic...
Definition: FspmUpd.h:2356
CHIPSET_INIT_INFO::MeChipInitCrc
UINT16 MeChipInitCrc
16 bit CRC value of MeChipInit Table
Definition: FspmUpd.h:49
FSP_M_TEST_CONFIG::Peg2Gen3EqPh3Method
UINT8 Peg2Gen3EqPh3Method
Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2.
Definition: FspmUpd.h:2444
FSP_M_CONFIG::WRDSUDT
UINT8 WRDSUDT
Offset 0x0498 - Write Drive Strength Up/Dn independently Enables/Disable Write Drive Strength Up/Dn i...
Definition: FspmUpd.h:1666
FSP_M_CONFIG::CoreVoltageMode
UINT8 CoreVoltageMode
Offset 0x0206 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override.
Definition: FspmUpd.h:969
FSP_M_CONFIG::IdleEnergyCh1Dimm1
UINT8 IdleEnergyCh1Dimm1
Offset 0x04DC - Idle Energy Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on...
Definition: FspmUpd.h:2002
FSP_M_CONFIG::SmbusEnable
UINT8 SmbusEnable
Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller.
Definition: FspmUpd.h:199
FSP_M_CONFIG::RingVoltageMode
UINT8 RingVoltageMode
Offset 0x021B - Ring voltage mode Ring voltage mode; 0: Adaptive; 1: Override.
Definition: FspmUpd.h:1081
FSP_M_CONFIG::CpuTraceHubMemReg0Size
UINT8 CpuTraceHubMemReg0Size
Offset 0x00F4 - CPU Trace Hub Memory Region 0 CPU Trace Hub Memory Region 0, The avaliable memory siz...
Definition: FspmUpd.h:479
FSP_M_CONFIG::RMTLoopCount
UINT8 RMTLoopCount
Offset 0x050D - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing...
Definition: FspmUpd.h:2285
FSP_M_CONFIG::TsodThigMax
UINT8 TsodThigMax
Offset 0x04FF - ThighMax Thigh = ThighMax (Default is 93)
Definition: FspmUpd.h:2203
FSP_M_CONFIG::SaPllVoltageOffset
UINT8 SaPllVoltageOffset
Offset 0x0475 - System Agent PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1456
FSP_M_CONFIG::Txt
UINT8 Txt
Offset 0x0226 - Txt Enable/Disable.
Definition: FspmUpd.h:1126
FSP_M_TEST_CONFIG::PegGen3Rsvd
UINT8 PegGen3Rsvd
Offset 0x053C - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled...
Definition: FspmUpd.h:2533
FSP_M_CONFIG::ForceOltmOrRefresh2x
UINT8 ForceOltmOrRefresh2x
Offset 0x0501 - Force OLTM or 2X Refresh when needed Disabled(Default): = Force OLTM.
Definition: FspmUpd.h:2218
FSP_M_CONFIG::UserBd
UINT8 UserBd
Offset 0x00BB - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo...
Definition: FspmUpd.h:274
FSP_M_CONFIG::GdxcIotSize
UINT8 GdxcIotSize
Offset 0x00A3 - GDXC IOT SIZE Size of IOT and MOT is in 8 MB chunks.
Definition: FspmUpd.h:188
FSP_M_CONFIG::ExitOnFailure
UINT8 ExitOnFailure
Offset 0x04AC - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS.
Definition: FspmUpd.h:1789
FSP_M_CONFIG::GtVoltageOffset
UINT16 GtVoltageOffset
Offset 0x01E7 - The voltage offset applied to GT slice 0(Default)=Minimal, 1000=Maximum.
Definition: FspmUpd.h:848
FSP_M_TEST_CONFIG::SendDidMsg
UINT8 SendDidMsg
Offset 0x059F - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable wi...
Definition: FspmUpd.h:2664
FSP_M_CONFIG::TxtImplemented
UINT8 TxtImplemented
Offset 0x01E3 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initia...
Definition: FspmUpd.h:826
FSP_M_CONFIG::PchSmbAlertEnable
UINT8 PchSmbAlertEnable
Offset 0x0462 - Enable SMBus Alert Pin Enable SMBus Alert Pin.
Definition: FspmUpd.h:1417
FSP_M_CONFIG::SgDelayAfterPwrEn
UINT16 SgDelayAfterPwrEn
Offset 0x010C - SG dGPU Power Delay SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds.
Definition: FspmUpd.h:547
FSP_M_CONFIG::ALIASCHK
UINT8 ALIASCHK
Offset 0x0495 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS.
Definition: FspmUpd.h:1648
FSP_M_CONFIG::PchIshEnable
UINT8 PchIshEnable
Offset 0x00FD - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller $EN_DIS...
Definition: FspmUpd.h:516
FSP_M_TEST_CONFIG::tWr2RdSG
UINT8 tWr2RdSG
Offset 0x05A9 - tWr2RdSG Delay between Write-to-Read commands in the same Bank Group.
Definition: FspmUpd.h:2720
FSP_M_CONFIG::TsodManualEnable
UINT8 TsodManualEnable
Offset 0x0500 - User Manual Thig and Tcrit Disabled(Default): Temperature will be given by the config...
Definition: FspmUpd.h:2211
FSP_M_CONFIG::BiosGuard
UINT8 BiosGuard
Offset 0x0223 - BiosGuard Enable/Disable.
Definition: FspmUpd.h:1110
FSP_M_CONFIG::GdxcEnable
UINT8 GdxcEnable
Offset 0x0504 - GDXC MOT enable GDXC MOT enable.
Definition: FspmUpd.h:2236
FSP_M_CONFIG::Peg1PowerDownUnusedLanes
UINT8 Peg1PowerDownUnusedLanes
Offset 0x0120 - Power down unused lanes on PEG 1 (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based on the max possible link width 0:No power saving, 1:Auto.
Definition: FspmUpd.h:664
FSP_M_CONFIG::RDEQT
UINT8 RDEQT
Offset 0x048A - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS...
Definition: FspmUpd.h:1582
FSP_M_CONFIG::ERDTC2D
UINT8 ERDTC2D
Offset 0x0481 - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS...
Definition: FspmUpd.h:1528
FSPM_UPD
Fsp M UPD Configuration.
Definition: FspmUpd.h:2810
FSP_M_CONFIG::TsodTcritMax
UINT8 TsodTcritMax
Offset 0x04F7 - TcritMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor...
Definition: FspmUpd.h:2149
FSP_M_CONFIG::DualDimmPerChannelBoardType
UINT8 DualDimmPerChannelBoardType
Offset 0x050F - Dual Dimm Per-Channel Board Type Option to indicate if Board Layout includes One/Two ...
Definition: FspmUpd.h:2298
FSP_M_CONFIG::EWRDSEQ
UINT8 EWRDSEQ
Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write...
Definition: FspmUpd.h:1867
FSP_M_CONFIG::EccSupport
UINT8 EccSupport
Offset 0x0499 - ECC Support Enables/Disable ECC Support $EN_DIS.
Definition: FspmUpd.h:1672
FSP_M_TEST_CONFIG::tRd2WrSG
UINT8 tRd2WrSG
Offset 0x05B1 - tRd2WrSG Delay between Read-to-Write commands in the same Bank Group.
Definition: FspmUpd.h:2762
FSP_M_TEST_CONFIG::Peg2Gen3EqPh2Enable
UINT8 Peg2Gen3EqPh2Enable
Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2.
Definition: FspmUpd.h:2407
FSP_M_CONFIG::WarmThresholdCh1Dimm1
UINT8 WarmThresholdCh1Dimm1
Offset 0x04CC - Warm Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1922
FSP_M_CONFIG::InitPcieAspmAfterOprom
UINT8 InitPcieAspmAfterOprom
Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM prog...
Definition: FspmUpd.h:686
FSP_M_CONFIG::Avx2RatioOffset
UINT8 Avx2RatioOffset
Offset 0x0210 - AVX2 Ratio Offset 0(Default)= No Offset.
Definition: FspmUpd.h:1033
FSP_M_CONFIG::SkipStopPbet
UINT8 SkipStopPbet
Offset 0x0201 - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_D...
Definition: FspmUpd.h:937
FSP_M_CONFIG::HotThresholdCh1Dimm0
UINT8 HotThresholdCh1Dimm0
Offset 0x04CF - Hot Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1937
FSP_M_CONFIG::DdrFreqLimit
UINT16 DdrFreqLimit
Offset 0x00BE - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz.
Definition: FspmUpd.h:294
FSP_M_TEST_CONFIG::Peg1Gen3EqPh2Enable
UINT8 Peg1Gen3EqPh2Enable
Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1.
Definition: FspmUpd.h:2400
FSP_M_CONFIG::RdEnergyCh1Dimm1
UINT8 RdEnergyCh1Dimm1
Offset 0x04E8 - Read Energy Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def) ...
Definition: FspmUpd.h:2062
FSP_M_CONFIG::SpdProfileSelected
UINT8 SpdProfileSelected
Offset 0x00D8 - SPD Profile Selected Select DIMM timing profile.
Definition: FspmUpd.h:350
FSP_M_CONFIG::RhActProbability
UINT8 RhActProbability
Offset 0x04C0 - RH Activation Probability RH Activation Probability, Probability value is 1/2^(inputv...
Definition: FspmUpd.h:1872
FSP_M_TEST_CONFIG::BypassPhySyncReset
UINT8 BypassPhySyncReset
Offset 0x059C - Bypass ChipsetInit sync reset.
Definition: FspmUpd.h:2644
FSP_M_CONFIG::SaVoltageOffset
UINT16 SaVoltageOffset
Offset 0x01ED - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum.
Definition: FspmUpd.h:863
FSP_M_TEST_CONFIG::tWr2WrDR
UINT8 tWr2WrDR
Offset 0x05AF - tWr2WrDR Delay between Write-to-Write commands in different Ranks.
Definition: FspmUpd.h:2752
FSP_M_CONFIG::NModeSupport
UINT8 NModeSupport
Offset 0x00ED - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N.
Definition: FspmUpd.h:440
FSP_M_TEST_CONFIG::Gen3SwEqEnableVocTest
UINT8 Gen3SwEqEnableVocTest
Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of th...
Definition: FspmUpd.h:2487
FSP_M_TEST_CONFIG::Gen3SwEqVocDwellTime
UINT16 Gen3SwEqVocDwellTime
Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000.
Definition: FspmUpd.h:2567
FSP_M_CONFIG::PeciC10Reset
UINT8 PeciC10Reset
Offset 0x00F6 - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command...
Definition: FspmUpd.h:494
FSP_M_CONFIG::Ddr4MixedUDimm2DpcLimit
UINT8 Ddr4MixedUDimm2DpcLimit
Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation Enable/Disable 2667 Frequency Limitation for DDR4 U...
Definition: FspmUpd.h:2305
FSP_M_CONFIG::DmiDeEmphasis
UINT8 DmiDeEmphasis
Offset 0x0176 - DeEmphasis control for DMI DeEmphasis control for DMI.
Definition: FspmUpd.h:765
FSP_M_CONFIG::CpuRatio
UINT8 CpuRatio
Offset 0x020A - CPU ratio value CPU ratio value.
Definition: FspmUpd.h:992
FSP_M_CONFIG::HotBudgetCh0Dimm1
UINT8 HotBudgetCh0Dimm1
Offset 0x04D6 - Hot Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM...
Definition: FspmUpd.h:1972
FSP_M_TEST_CONFIG::tWTR_L
UINT8 tWTR_L
Offset 0x05B7 - tWTR_L Min Internal Write to Read Command Delay Time for Same Bank Group...
Definition: FspmUpd.h:2795
FSP_M_CONFIG::ERDMPRTC2D
UINT8 ERDMPRTC2D
Offset 0x047C - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $...
Definition: FspmUpd.h:1498
FSP_M_CONFIG::TxtDprMemorySize
UINT32 TxtDprMemorySize
Offset 0x0234 - TxtDprMemorySize Enable/Disable.
Definition: FspmUpd.h:1150
FSP_M_CONFIG::ThrtCkeMinDefeatLpddr
UINT8 ThrtCkeMinDefeatLpddr
Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR Enables/Disable Throttler CKEMin Defeature(For LPD...
Definition: FspmUpd.h:1771
FSP_M_CONFIG::OcLock
UINT8 OcLock
Offset 0x0204 - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable...
Definition: FspmUpd.h:957
FSP_M_CONFIG::CkeRankMapping
UINT8 CkeRankMapping
Offset 0x04EE - Cke Rank Mapping Bits [7:4] - Channel 1, bits [3:0] - Channel 0.
Definition: FspmUpd.h:2094
FSP_M_CONFIG::IdleEnergyCh0Dimm1
UINT8 IdleEnergyCh0Dimm1
Offset 0x04DA - Idle Energy Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on...
Definition: FspmUpd.h:1992
FSP_M_CONFIG::MemorySpdPtr01
UINT32 MemorySpdPtr01
Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 Pointer to SPD data, will be used only when SpdAd...
Definition: FspmUpd.h:71
FSP_M_CONFIG::CpuTraceHubMemReg1Size
UINT8 CpuTraceHubMemReg1Size
Offset 0x00F5 - CPU Trace Hub Memory Region 1 CPU Trace Hub Memory Region 1.
Definition: FspmUpd.h:486
FSP_M_CONFIG::Ratio
UINT8 Ratio
Offset 0x00DC - Memory Ratio Automatic or the frequency will equal ratio times reference clock...
Definition: FspmUpd.h:370
FSP_M_CONFIG::PdEnergyCh0Dimm1
UINT8 PdEnergyCh0Dimm1
Offset 0x04DE - PowerDown Energy Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off...
Definition: FspmUpd.h:2012
FSP_M_CONFIG::GtusMaxOcRatio
UINT8 GtusMaxOcRatio
Offset 0x01FB - Maximum GTus turbo ratio override 0(Default)=Minimal, 60=Maximum. ...
Definition: FspmUpd.h:919
FSP_M_CONFIG::DllBwEn0
UINT8 DllBwEn0
Offset 0x00EE - DllBwEn[0] DllBwEn[0], for 1067 (0..7)
Definition: FspmUpd.h:445
FSP_M_TEST_CONFIG::tWr2WrSG
UINT8 tWr2WrSG
Offset 0x05AD - tWr2WrSG Delay between Write-to-Write commands in the same Bank Group.
Definition: FspmUpd.h:2741
FSP_M_TEST_CONFIG::PegRxCemTestingMode
UINT8 PegRxCemTestingMode
Offset 0x0537 - PCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PC...
Definition: FspmUpd.h:2495
FSP_M_CONFIG::BiosGuardToolsInterface
UINT8 BiosGuardToolsInterface
Offset 0x0224.
Definition: FspmUpd.h:1114
FSP_M_CONFIG::SkipMpInit
UINT8 SkipMpInit
Offset 0x00C8 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize...
Definition: FspmUpd.h:339
FSP_M_CONFIG::PdEnergyCh1Dimm0
UINT8 PdEnergyCh1Dimm0
Offset 0x04DF - PowerDown Energy Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off...
Definition: FspmUpd.h:2017
FSP_M_TEST_CONFIG::Peg3Gen3EqPh3Method
UINT8 Peg3Gen3EqPh3Method
Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3.
Definition: FspmUpd.h:2454
FSP_M_CONFIG::GttSize
UINT16 GttSize
Offset 0x0178 - Selection of iGFX GTT Memory size 1=2MB, 2=4MB, 3=8MB, Default is 3 1:2MB...
Definition: FspmUpd.h:777
FSP_M_CONFIG::Peg0Enable
UINT8 Peg0Enable
Offset 0x0113 - Enable/Disable PEG 0 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (...
Definition: FspmUpd.h:573
FSP_M_TEST_CONFIG::BiosSize
UINT16 BiosSize
Offset 0x0592 - BiosSize Enable/Disable.
Definition: FspmUpd.h:2601
FSP_M_CONFIG::WRDSEQT
UINT8 WRDSEQT
Offset 0x0487 - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalizatio...
Definition: FspmUpd.h:1564
FSP_M_CONFIG::RTL
UINT8 RTL
Offset 0x0492 - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS...
Definition: FspmUpd.h:1630
FSP_M_CONFIG
Fsp M Configuration.
Definition: FspmUpd.h:56
FSP_M_TEST_CONFIG::tRd2RdDG
UINT8 tRd2RdDG
Offset 0x05A6 - tRd2RdDG Delay between Read-to-Read commands in different Bank Group for DDR4...
Definition: FspmUpd.h:2705
FSP_M_CONFIG::IsTPMPresence
UINT8 IsTPMPresence
Offset 0x0260 - IsTPMPresence IsTPMPresence default values.
Definition: FspmUpd.h:1190
FSP_M_TEST_CONFIG::tRd2RdSG
UINT8 tRd2RdSG
Offset 0x05A5 - tRd2RdSG Delay between Read-to-Read commands in the same Bank Group.
Definition: FspmUpd.h:2699
FSPM_UPD::FspUpdHeader
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FspmUpd.h:2814
FSP_M_CONFIG::RefClk
UINT8 RefClk
Offset 0x00D9 - Memory Reference Clock 100MHz, 133MHz.
Definition: FspmUpd.h:356
FSP_M_CONFIG::TsodEventOutputControl
UINT8 TsodEventOutputControl
Offset 0x04FB - Event output control Disable:Event output disable.
Definition: FspmUpd.h:2177
FSP_M_TEST_CONFIG::tWr2RdDR
UINT8 tWr2RdDR
Offset 0x05AB - tWr2RdDR Delay between Write-to-Read commands in different Ranks. ...
Definition: FspmUpd.h:2731
FSP_M_CONFIG::VmxEnable
UINT8 VmxEnable
Offset 0x020F - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable.
Definition: FspmUpd.h:1027
FSP_M_TEST_CONFIG::HeciCommunication2
UINT8 HeciCommunication2
Offset 0x05A3 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Devi...
Definition: FspmUpd.h:2688
FSP_M_CONFIG::RaplLim2Ena
UINT8 RaplLim2Ena
Offset 0x04A6 - RAPL PL 2 enable Enables/Disable RAPL PL 2 enable $EN_DIS.
Definition: FspmUpd.h:1753
FSP_M_CONFIG::PcdSerialDebugBaudRate
UINT8 PcdSerialDebugBaudRate
Offset 0x0478 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages.
Definition: FspmUpd.h:1473
FSP_M_TEST_CONFIG::tRRD_L
UINT8 tRRD_L
Offset 0x05B5 - tRRD_L Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only.
Definition: FspmUpd.h:2783
FSP_M_TEST_CONFIG::tRd2RdDR
UINT8 tRd2RdDR
Offset 0x05A7 - tRd2RdDR Delay between Read-to-Read commands in different Ranks.
Definition: FspmUpd.h:2710
FSP_M_CONFIG::ThrtCkeMinTmrLpddr
UINT8 ThrtCkeMinTmrLpddr
Offset 0x0514 - Throttler CKEMin Timer - LPDDR Timer value for CKEMin (For LPDDR Only), range[255;0].
Definition: FspmUpd.h:2323
CHIPSET_INIT_INFO::BiosChipInitCrc
UINT16 BiosChipInitCrc
16 bit CRC value of PchChipInit Table
Definition: FspmUpd.h:50
FSP_M_CONFIG::ScramblerSupport
UINT8 ScramblerSupport
Offset 0x00C7 - Scrambler Support This option enables data scrambling in memory.
Definition: FspmUpd.h:332
FSP_M_CONFIG::ApStartupBase
UINT32 ApStartupBase
Offset 0x0248 - ApStartupBase Enable/Disable.
Definition: FspmUpd.h:1170
FSP_M_CONFIG::CorePllVoltageOffset
UINT8 CorePllVoltageOffset
Offset 0x0213 - Core PLL voltage offset Core PLL voltage offset.
Definition: FspmUpd.h:1051
FSP_M_CONFIG::PsmiRegionSize
UINT8 PsmiRegionSize
Offset 0x0182 - Selection of PSMI Region size 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is ...
Definition: FspmUpd.h:799
FSP_M_CONFIG::TsodEventMode
UINT8 TsodEventMode
Offset 0x04F8 - Event mode Disable:Comparator mode.
Definition: FspmUpd.h:2156
FSP_M_CONFIG::FClkFrequency
UINT8 FClkFrequency
Offset 0x020D - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX).
Definition: FspmUpd.h:1014
FSP_M_TEST_CONFIG::tRRD_S
UINT8 tRRD_S
Offset 0x05B6 - tRRD_S Min Row Active to Row Active Delay Time for Different Bank Group...
Definition: FspmUpd.h:2789
FSP_M_CONFIG::WRVC2D
UINT8 WRVC2D
Offset 0x048E - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS...
Definition: FspmUpd.h:1606
FSP_M_CONFIG::PchLpcEnhancePort8xhDecoding
UINT8 PchLpcEnhancePort8xhDecoding
Offset 0x0450 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h...
Definition: FspmUpd.h:1362
FSP_M_TEST_CONFIG::PegGen3ProgramStaticEq
UINT8 PegGen3ProgramStaticEq
Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Stati...
Definition: FspmUpd.h:2461
FSP_M_CONFIG::RaplLim2WindX
UINT8 RaplLim2WindX
Offset 0x04C1 - RAPL PL 2 WindowX Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) ...
Definition: FspmUpd.h:1877
FSP_M_CONFIG::MEMTST
UINT8 MEMTST
Offset 0x0494 - Memory Test Enables/Disable Memory Test $EN_DIS.
Definition: FspmUpd.h:1642
FSP_M_CONFIG::MrcSafeConfig
UINT8 MrcSafeConfig
Offset 0x0477 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS.
Definition: FspmUpd.h:1467
FSP_M_CONFIG::WarmBudgetCh1Dimm1
UINT8 WarmBudgetCh1Dimm1
Offset 0x04D4 - Warm Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1962
FSP_M_CONFIG::CpuTraceHubMode
UINT8 CpuTraceHubMode
Offset 0x00F3 - CPU Trace Hub Mode Select 'Target Debugger' if Trace Hub is used by target debugger s...
Definition: FspmUpd.h:472
FSP_M_CONFIG::SaGv
UINT8 SaGv
Offset 0x00BC - SA GV System Agent dynamic frequency support and when enabled memory will be training...
Definition: FspmUpd.h:282
FSP_M_CONFIG::EnablePwrDn
UINT8 EnablePwrDn
Offset 0x04A2 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter $EN_DIS...
Definition: FspmUpd.h:1728
FSP_M_CONFIG::GtVoltageOverride
UINT16 GtVoltageOverride
Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies ...
Definition: FspmUpd.h:853
FSP_M_CONFIG::PegDataPtr
UINT32 PegDataPtr
Offset 0x0152 - Memory data pointer for saved preset search results The reference code will store the...
Definition: FspmUpd.h:748
FSP_M_TEST_CONFIG::tWr2RdDG
UINT8 tWr2RdDG
Offset 0x05AA - tWr2RdDG Delay between Write-to-Read commands in different Bank Group for DDR4...
Definition: FspmUpd.h:2726
FSP_M_CONFIG::RootPortIndex
UINT8 RootPortIndex
Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU Root port Index number to...
Definition: FspmUpd.h:868
FSP_M_CONFIG::RdEnergyCh0Dimm1
UINT8 RdEnergyCh0Dimm1
Offset 0x04E6 - Read Energy Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def) ...
Definition: FspmUpd.h:2052
FSP_M_CONFIG::RankInterleave
UINT8 RankInterleave
Offset 0x049B - Rank Interleave support Enables/Disable Rank Interleave support.
Definition: FspmUpd.h:1685
FSP_M_CONFIG::UserThresholdEnable
UINT8 UserThresholdEnable
Offset 0x04F5 - User Manual Threshold Disabled: Predefined threshold will be used.
Definition: FspmUpd.h:2135
FSP_M_CONFIG::RaplLim2WindY
UINT8 RaplLim2WindY
Offset 0x04C2 - RAPL PL 2 WindowY Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) ...
Definition: FspmUpd.h:1882
FSP_M_CONFIG::HobBufferSize
UINT8 HobBufferSize
Offset 0x0479 - HobBufferSize Size to set HOB Buffer.
Definition: FspmUpd.h:1480
FSP_M_CONFIG::RingVoltageAdaptive
UINT16 RingVoltageAdaptive
Offset 0x021E - Ring Turbo voltage Adaptive Extra Turbo voltage applied to the cpu ring when the cpu ...
Definition: FspmUpd.h:1093
FSP_M_CONFIG::RingDownBin
UINT8 RingDownBin
Offset 0x021A - Ring Downbin Ring Downbin enable/disable.
Definition: FspmUpd.h:1075
FSP_M_TEST_CONFIG::BdatEnable
UINT8 BdatEnable
Offset 0x0525 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data...
Definition: FspmUpd.h:2349
FSP_M_CONFIG::HotThresholdCh1Dimm1
UINT8 HotThresholdCh1Dimm1
Offset 0x04D0 - Hot Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1942
FSP_M_CONFIG::HotThresholdCh0Dimm1
UINT8 HotThresholdCh0Dimm1
Offset 0x04CE - Hot Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
Definition: FspmUpd.h:1932
FSP_M_CONFIG::RemapEnable
UINT8 RemapEnable
Offset 0x049A - Memory Remap Enables/Disable Memory Remap $EN_DIS.
Definition: FspmUpd.h:1678
FSP_M_CONFIG::CMDNORM
UINT8 CMDNORM
Offset 0x04BE - CMD Normalization Enable/Disable CMD Normalization $EN_DIS.
Definition: FspmUpd.h:1861
FSP_M_TEST_CONFIG::DmiGen3EqPh3Method
UINT8 DmiGen3EqPh3Method
Offset 0x052A - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3.
Definition: FspmUpd.h:2386
FSP_M_CONFIG::EnableExtts
UINT8 EnableExtts
Offset 0x049F - Extern Therm Status Enables/Disable Extern Therm Status $EN_DIS.
Definition: FspmUpd.h:1710
FSP_M_TEST_CONFIG::tWr2WrDG
UINT8 tWr2WrDG
Offset 0x05AE - tWr2WrDG Delay between Write-to-Write commands in different Bank Group for DDR4...
Definition: FspmUpd.h:2747
FSP_M_CONFIG::Ddr4DdpSharedZq
UINT8 Ddr4DdpSharedZq
Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is s...
Definition: FspmUpd.h:1807
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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspsUpd.h Source File

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FspsUpd.h
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1 /** @file
2
3 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31 **/
32
33 #ifndef __FSPSUPD_H__
34 #define __FSPSUPD_H__
35
36 #include <FspUpd.h>
37
38 #pragma pack(1)
39
40
41 ///
42 /// Azalia Header structure
43 ///
44 typedef struct {
45 UINT16 VendorId; ///< Codec Vendor ID
46 UINT16 DeviceId; ///< Codec Device ID
47 UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
48 UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
49 UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
50 UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
51 } AZALIA_HEADER;
52
53 ///
54 /// Audio Azalia Verb Table structure
55 ///
56 typedef struct {
57 AZALIA_HEADER Header; ///< AZALIA PCH header
58 UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
59 } AUDIO_AZALIA_VERB_TABLE;
60
61 ///
62 /// Refer to the definition of PCH_INT_PIN
63 ///
64 typedef enum {
65 SiPchNoInt, ///< No Interrupt Pin
66 SiPchIntA,
67 SiPchIntB,
68 SiPchIntC,
69 SiPchIntD
70 } SI_PCH_INT_PIN;
71 ///
72 /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
73 ///
74 typedef struct {
75 UINT8 Device; ///< Device number
76 UINT8 Function; ///< Device function
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
78 UINT8 Irq; ///< IRQ to be set for device.
79 } SI_PCH_DEVICE_INTERRUPT_CONFIG;
80
81 #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
82
83
84 /** Fsp S Configuration
85 **/
86 typedef struct {
87
88 /** Offset 0x0020 - Logo Pointer
89 Points to PEI Display Logo Image
90 **/
91 UINT32 LogoPtr;
92
93 /** Offset 0x0024 - Logo Size
94 Size of PEI Display Logo Image
95 **/
96 UINT32 LogoSize;
97
98 /** Offset 0x0028 - Graphics Configuration Ptr
99 Points to VBT
100 **/
101 UINT32 GraphicsConfigPtr;
102
103 /** Offset 0x002C - Enable Device 4
104 Enable/disable Device 4
105 $EN_DIS
106 **/
107 UINT8 Device4Enable;
108
109 /** Offset 0x002D - Enable HD Audio DSP
110 Enable/disable HD Audio DSP feature.
111 $EN_DIS
112 **/
113 UINT8 PchHdaDspEnable;
114
115 /** Offset 0x002E
116 **/
117 UINT8 UnusedUpdSpace0[3];
118
119 /** Offset 0x0031 - Enable eMMC Controller
120 Enable/disable eMMC Controller.
121 $EN_DIS
122 **/
123 UINT8 ScsEmmcEnabled;
124
125 /** Offset 0x0032 - Enable eMMC HS400 Mode
126 Enable eMMC HS400 Mode.
127 $EN_DIS
128 **/
129 UINT8 ScsEmmcHs400Enabled;
130
131 /** Offset 0x0033 - Enable SdCard Controller
132 Enable/disable SD Card Controller.
133 $EN_DIS
134 **/
135 UINT8 ScsSdCardEnabled;
136
137 /** Offset 0x0034 - Show SPI controller
138 Enable/disable to show SPI controller.
139 $EN_DIS
140 **/
141 UINT8 ShowSpiController;
142
143 /** Offset 0x0035
144 **/
145 UINT8 UnusedUpdSpace1[3];
146
147 /** Offset 0x0038 - MicrocodeRegionBase
148 Memory Base of Microcode Updates
149 **/
150 UINT32 MicrocodeRegionBase;
151
152 /** Offset 0x003C - MicrocodeRegionSize
153 Size of Microcode Updates
154 **/
155 UINT32 MicrocodeRegionSize;
156
157 /** Offset 0x0040 - Turbo Mode
158 Enable/Disable Turbo mode. 0: disable, 1: enable
159 $EN_DIS
160 **/
161 UINT8 TurboMode;
162
163 /** Offset 0x0041 - Enable SATA SALP Support
164 Enable/disable SATA Aggressive Link Power Management.
165 $EN_DIS
166 **/
167 UINT8 SataSalpSupport;
168
169 /** Offset 0x0042 - Enable SATA ports
170 Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
171 and so on.
172 **/
173 UINT8 SataPortsEnable[8];
174
175 /** Offset 0x004A - Enable SATA DEVSLP Feature
176 Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
177 port, byte0 for port0, byte1 for port1, and so on.
178 **/
179 UINT8 SataPortsDevSlp[8];
180
181 /** Offset 0x0052 - Enable USB2 ports
182 Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
183 port1, and so on.
184 **/
185 UINT8 PortUsb20Enable[16];
186
187 /** Offset 0x0062 - Enable USB3 ports
188 Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
189 port1, and so on.
190 **/
191 UINT8 PortUsb30Enable[10];
192
193 /** Offset 0x006C - Enable xDCI controller
194 Enable/disable to xDCI controller.
195 $EN_DIS
196 **/
197 UINT8 XdciEnable;
198
199 /** Offset 0x006D
200 **/
201 UINT8 UnusedUpdSpace2[2];
202
203 /** Offset 0x006F - Enable SerialIo Device Mode
204 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable
205 SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device
206 mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1,
207 and so on.
208 **/
209 UINT8 SerialIoDevMode[12];
210
211 /** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
212 The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
213 **/
214 UINT32 DevIntConfigPtr;
215
216 /** Offset 0x007F - Number of DevIntConfig Entry
217 Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
218 must not be NULL.
219 **/
220 UINT8 NumOfDevIntConfig;
221
222 /** Offset 0x0080 - PIRQx to IRQx Map Config
223 PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
224 PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
225 8259 PCI mode.
226 **/
227 UINT8 PxRcConfig[8];
228
229 /** Offset 0x0088 - Select GPIO IRQ Route
230 GPIO IRQ Select. The valid value is 14 or 15.
231 **/
232 UINT8 GpioIrqRoute;
233
234 /** Offset 0x0089 - Select SciIrqSelect
235 SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
236 **/
237 UINT8 SciIrqSelect;
238
239 /** Offset 0x008A - Select TcoIrqSelect
240 TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
241 **/
242 UINT8 TcoIrqSelect;
243
244 /** Offset 0x008B - Enable/Disable Tco IRQ
245 Enable/disable TCO IRQ
246 $EN_DIS
247 **/
248 UINT8 TcoIrqEnable;
249
250 /** Offset 0x008C - PCH HDA Verb Table Entry Number
251 Number of Entries in Verb Table.
252 **/
253 UINT8 PchHdaVerbTableEntryNum;
254
255 /** Offset 0x008D - PCH HDA Verb Table Pointer
256 Pointer to Array of pointers to Verb Table.
257 **/
258 UINT32 PchHdaVerbTablePtr;
259
260 /** Offset 0x0091 - PCH HDA Codec Sx Wake Capability
261 Capability to detect wake initiated by a codec in Sx
262 **/
263 UINT8 PchHdaCodecSxWakeCapability;
264
265 /** Offset 0x0092 - Enable SATA
266 Enable/disable SATA controller.
267 $EN_DIS
268 **/
269 UINT8 SataEnable;
270
271 /** Offset 0x0093 - SATA Mode
272 Select SATA controller working mode.
273 0:AHCI, 1:RAID
274 **/
275 UINT8 SataMode;
276
277 /** Offset 0x0094 - USB Per Port HS Preemphasis Bias
278 USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
279 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
280 **/
281 UINT8 Usb2AfePetxiset[16];
282
283 /** Offset 0x00A4 - USB Per Port HS Transmitter Bias
284 USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
285 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
286 **/
287 UINT8 Usb2AfeTxiset[16];
288
289 /** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis
290 USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
291 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
292 **/
293 UINT8 Usb2AfePredeemp[16];
294
295 /** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis
296 USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
297 One byte for each port.
298 **/
299 UINT8 Usb2AfePehalfbit[16];
300
301 /** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
302 Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
303 in arrary can be between 0-1. One byte for each port.
304 **/
305 UINT8 Usb3HsioTxDeEmphEnable[10];
306
307 /** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
308 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
309 <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
310 **/
311 UINT8 Usb3HsioTxDeEmph[10];
312
313 /** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
314 Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
315 in arrary can be between 0-1. One byte for each port.
316 **/
317 UINT8 Usb3HsioTxDownscaleAmpEnable[10];
318
319 /** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment
320 USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
321 = 00h</b>. One byte for each port.
322 **/
323 UINT8 Usb3HsioTxDownscaleAmp[10];
324
325 /** Offset 0x00FC - Enable LAN
326 Enable/disable LAN controller.
327 $EN_DIS
328 **/
329 UINT8 PchLanEnable;
330
331 /** Offset 0x00FD - Enable HD Audio Link
332 Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
333 $EN_DIS
334 **/
335 UINT8 PchHdaAudioLinkHda;
336
337 /** Offset 0x00FE - Enable HD Audio DMIC0 Link
338 Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.
339 $EN_DIS
340 **/
341 UINT8 PchHdaAudioLinkDmic0;
342
343 /** Offset 0x00FF - Enable HD Audio DMIC1 Link
344 Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
345 $EN_DIS
346 **/
347 UINT8 PchHdaAudioLinkDmic1;
348
349 /** Offset 0x0100 - Enable HD Audio SSP0 Link
350 Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
351 $EN_DIS
352 **/
353 UINT8 PchHdaAudioLinkSsp0;
354
355 /** Offset 0x0101 - Enable HD Audio SSP1 Link
356 Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
357 $EN_DIS
358 **/
359 UINT8 PchHdaAudioLinkSsp1;
360
361 /** Offset 0x0102 - Enable HD Audio SSP2 Link
362 Enable/disable HD Audio SSP2/I2S link.
363 $EN_DIS
364 **/
365 UINT8 PchHdaAudioLinkSsp2;
366
367 /** Offset 0x0103 - Enable HD Audio SoundWire#1 Link
368 Enable/disable HD Audio SNDW1 link. Muxed with HDA.
369 $EN_DIS
370 **/
371 UINT8 PchHdaAudioLinkSndw1;
372
373 /** Offset 0x0104 - Enable HD Audio SoundWire#2 Link
374 Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
375 $EN_DIS
376 **/
377 UINT8 PchHdaAudioLinkSndw2;
378
379 /** Offset 0x0105 - Enable HD Audio SoundWire#3 Link
380 Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
381 $EN_DIS
382 **/
383 UINT8 PchHdaAudioLinkSndw3;
384
385 /** Offset 0x0106 - Enable HD Audio SoundWire#4 Link
386 Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
387 $EN_DIS
388 **/
389 UINT8 PchHdaAudioLinkSndw4;
390
391 /** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting
392 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
393 $EN_DIS
394 **/
395 UINT8 PchHdaSndwBufferRcomp;
396
397 /** Offset 0x0108 - PTM for PCIE RP Mask
398 Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
399 One bit for each port, bit0 for port1, bit1 for port2, and so on.
400 **/
401 UINT32 PcieRpPtmMask;
402
403 /** Offset 0x010C - DPC for PCIE RP Mask
404 Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
405 One bit for each port, bit0 for port1, bit1 for port2, and so on.
406 **/
407 UINT32 PcieRpDpcMask;
408
409 /** Offset 0x0110 - DPC Extensions PCIE RP Mask
410 Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
411 for each port, bit0 for port1, bit1 for port2, and so on.
412 **/
413 UINT32 PcieRpDpcExtensionsMask;
414
415 /** Offset 0x0114 - USB PDO Programming
416 Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
417 during later phase. 1: enable, 0: disable
418 $EN_DIS
419 **/
420 UINT8 UsbPdoProgramming;
421
422 /** Offset 0x0115 - Power button debounce configuration
423 Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
424 be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
425 **/
426 UINT32 PmcPowerButtonDebounce;
427
428 /** Offset 0x0119 - PCH eSPI Master and Slave BME enabled
429 PCH eSPI Master and Slave BME enabled
430 $EN_DIS
431 **/
432 UINT8 PchEspiBmeMasterSlaveEnabled;
433
434 /** Offset 0x011A - PCH SATA use RST Legacy OROM
435 Use PCH SATA RST Legacy OROM when CSM is Enabled
436 $EN_DIS
437 **/
438 UINT8 SataRstLegacyOrom;
439
440 /** Offset 0x011B - Trace Hub Memory Base
441 If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
442 trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
443 memory is configured properly.
444 **/
445 UINT32 TraceHubMemBase;
446
447 /** Offset 0x011F - PMC Debug Message Enable
448 When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
449 will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
450 $EN_DIS
451 **/
452 UINT8 PmcDbgMsgEn;
453
454 /** Offset 0x0120 - Pointer of ChipsetInit Binary
455 ChipsetInit Binary Pointer.
456 **/
457 UINT32 ChipsetInitBinPtr;
458
459 /** Offset 0x0124 - Length of ChipsetInit Binary
460 ChipsetInit Binary Length.
461 **/
462 UINT32 ChipsetInitBinLen;
463
464 /** Offset 0x0128 - PchPostMemRsvd
465 Reserved for PCH Post-Mem
466 $EN_DIS
467 **/
468 UINT8 PchPostMemRsvd[29];
469
470 /** Offset 0x0145 - Enable Ufs Controller
471 Enable/disable Ufs 2.0 Controller.
472 $EN_DIS
473 **/
474 UINT8 ScsUfsEnabled;
475
476 /** Offset 0x0146 - CNVi Configuration
477 This option allows for automatic detection of Connectivity Solution. [Auto Detection]
478 assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
479 0:Disable, 1:Auto
480 **/
481 UINT8 PchCnviMode;
482
483 /** Offset 0x0147 - SdCard power enable polarity
484 Choose SD_PWREN# polarity
485 0: Active low, 1: Active high
486 **/
487 UINT8 SdCardPowerEnableActiveHigh;
488
489 /** Offset 0x0148 - PCH USB2 PHY Power Gating enable
490 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
491 Sus Well PG
492 $EN_DIS
493 **/
494 UINT8 PchUsb2PhySusPgEnable;
495
496 /** Offset 0x0149 - PCH USB OverCurrent mapping enable
497 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
498 mapping allow for NOA usage of OC pins
499 $EN_DIS
500 **/
501 UINT8 PchUsbOverCurrentEnable;
502
503 /** Offset 0x014A
504 **/
505 UINT8 UnusedUpdSpace3;
506
507 /** Offset 0x014B - CNVi MfUart1 Type
508 This option configures Uart type which connects to MfUart1
509 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads
510 **/
511 UINT8 PchCnviMfUart1Type;
512
513 /** Offset 0x014C - Espi Lgmr Memory Range decode
514 This option enables or disables espi lgmr
515 $EN_DIS
516 **/
517 UINT8 PchEspiLgmrEnable;
518
519 /** Offset 0x014D - HECI3 state
520 The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
521 0: disable, 1: enable
522 $EN_DIS
523 **/
524 UINT8 Heci3Enabled;
525
526 /** Offset 0x014E
527 **/
528 UINT8 UnusedUpdSpace4;
529
530 /** Offset 0x014F - PCHHOT# pin
531 Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
532 $EN_DIS
533 **/
534 UINT8 PchHotEnable;
535
536 /** Offset 0x0150 - SATA LED
537 SATA LED indicating SATA controller activity. 0: disable, 1: enable
538 $EN_DIS
539 **/
540 UINT8 SataLedEnable;
541
542 /** Offset 0x0151 - VRAlert# Pin
543 When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
544 to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
545 $EN_DIS
546 **/
547 UINT8 PchPmVrAlert;
548
549 /** Offset 0x0152 - SLP_S0 VM Dynamic Control
550 SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable
551 $EN_DIS
552 **/
553 UINT8 PchPmSlpS0VmRuntimeControl;
554
555 /** Offset 0x0153 - SLP_S0 VM 0.70V Support
556 SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable
557 $EN_DIS
558 **/
559 UINT8 PchPmSlpS0Vm070VSupport;
560
561 /** Offset 0x0154 - SLP_S0 VM 0.75V Support
562 SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable
563 $EN_DIS
564 **/
565 UINT8 PchPmSlpS0Vm075VSupport;
566
567 /** Offset 0x0155 - AMT Switch
568 Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
569 $EN_DIS
570 **/
571 UINT8 AmtEnabled;
572
573 /** Offset 0x0156 - WatchDog Timer Switch
574 Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
575 $EN_DIS
576 **/
577 UINT8 WatchDog;
578
579 /** Offset 0x0157 - ASF Switch
580 Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
581 $EN_DIS
582 **/
583 UINT8 AsfEnabled;
584
585 /** Offset 0x0158 - Manageability Mode set by Mebx
586 Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
587 $EN_DIS
588 **/
589 UINT8 ManageabilityMode;
590
591 /** Offset 0x0159 - PET Progress
592 Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
593 PET Events.
594 $EN_DIS
595 **/
596 UINT8 FwProgress;
597
598 /** Offset 0x015A - SOL Switch
599 Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
600 $EN_DIS
601 **/
602 UINT8 AmtSolEnabled;
603
604 /** Offset 0x015B - OS Timer
605 16 bits Value, Set OS watchdog timer.
606 $EN_DIS
607 **/
608 UINT16 WatchDogTimerOs;
609
610 /** Offset 0x015D - BIOS Timer
611 16 bits Value, Set BIOS watchdog timer.
612 $EN_DIS
613 **/
614 UINT16 WatchDogTimerBios;
615
616 /** Offset 0x015F - Remote Assistance Trigger Availablilty
617 Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx
618 $EN_DIS
619 **/
620 UINT8 RemoteAssistance;
621
622 /** Offset 0x0160 - KVM Switch
623 Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
624 $EN_DIS
625 **/
626 UINT8 AmtKvmEnabled;
627
628 /** Offset 0x0161 - MEBX execution
629 Enable/Disable. 0: Disable, 1: enable, Force MEBX execution
630 $EN_DIS
631 **/
632 UINT8 ForcMebxSyncUp;
633
634 /** Offset 0x0162
635 **/
636 UINT8 UnusedUpdSpace5[1];
637
638 /** Offset 0x0163 - PCH PCIe root port connection type
639 0: built-in device, 1:slot
640 **/
641 UINT8 PcieRpSlotImplemented[24];
642
643 /** Offset 0x017B - Usage type for ClkSrc
644 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
645 (free running), 0xFF: not used
646 **/
647 UINT8 PcieClkSrcUsage[16];
648
649 /** Offset 0x018B - ClkReq-to-ClkSrc mapping
650 Number of ClkReq signal assigned to ClkSrc
651 **/
652 UINT8 PcieClkSrcClkReq[16];
653
654 /** Offset 0x019B - PCIE RP Access Control Services Extended Capability
655 Enable/Disable PCIE RP Access Control Services Extended Capability
656 **/
657 UINT8 PcieRpAcsEnabled[24];
658
659 /** Offset 0x01B3 - PCIE RP Clock Power Management
660 Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
661 can still be controlled by L1 PM substates mechanism
662 **/
663 UINT8 PcieRpEnableCpm[24];
664
665 /** Offset 0x01CB - PCIE RP Detect Timeout Ms
666 The number of milliseconds within 0~65535 in reference code will wait for link to
667 exit Detect state for enabled ports before assuming there is no device and potentially
668 disabling the port.
669 **/
670 UINT16 PcieRpDetectTimeoutMs[24];
671
672 /** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating
673 Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
674 PCH-H. 0: disable, 1: enable
675 $EN_DIS
676 **/
677 UINT8 PmcModPhySusPgEnable;
678
679 /** Offset 0x01FC - SlpS0WithGbeSupport
680 Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable
681 $EN_DIS
682 **/
683 UINT8 SlpS0WithGbeSupport;
684
685 /** Offset 0x01FD
686 **/
687 UINT8 UnusedUpdSpace6[3];
688
689 /** Offset 0x0200 - Enable/Disable SA CRID
690 Enable: SA CRID, Disable (Default): SA CRID
691 $EN_DIS
692 **/
693 UINT8 CridEnable;
694
695 /** Offset 0x0201 - DMI ASPM
696 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
697 0:Disable, 1:L0s, 2:L1, 3:L0sL1
698 **/
699 UINT8 DmiAspm;
700
701 /** Offset 0x0202 - PCIe DeEmphasis control per root port
702 0: -6dB, 1(Default): -3.5dB
703 0:-6dB, 1:-3.5dB
704 **/
705 UINT8 PegDeEmphasis[4];
706
707 /** Offset 0x0206 - PCIe Slot Power Limit value per root port
708 Slot power limit value per root port
709 **/
710 UINT8 PegSlotPowerLimitValue[4];
711
712 /** Offset 0x020A - PCIe Slot Power Limit scale per root port
713 Slot power limit scale per root port
714 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
715 **/
716 UINT8 PegSlotPowerLimitScale[4];
717
718 /** Offset 0x020E - PCIe Physical Slot Number per root port
719 Physical Slot Number per root port
720 **/
721 UINT16 PegPhysicalSlotNumber[4];
722
723 /** Offset 0x0216 - Enable/Disable PavpEnable
724 Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
725 $EN_DIS
726 **/
727 UINT8 PavpEnable;
728
729 /** Offset 0x0217 - CdClock Frequency selection
730 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz
731 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
732 **/
733 UINT8 CdClock;
734
735 /** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit
736 Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
737 $EN_DIS
738 **/
739 UINT8 PeiGraphicsPeimInit;
740
741 /** Offset 0x0219
742 **/
743 UINT8 UnusedUpdSpace7;
744
745 /** Offset 0x021A - Enable or disable GNA device
746 0=Disable, 1(Default)=Enable
747 $EN_DIS
748 **/
749 UINT8 GnaEnable;
750
751 /** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table
752 0=Disable/Clear, 1=Enable/Set
753 $EN_DIS
754 **/
755 UINT8 X2ApicOptOut;
756
757 /** Offset 0x021C - Base addresses for VT-d function MMIO access
758 Base addresses for VT-d MMIO access per VT-d engine
759 **/
760 UINT32 VtdBaseAddress[3];
761
762 /** Offset 0x0228 - Enable or disable eDP device
763 0=Disable, 1(Default)=Enable
764 $EN_DIS
765 **/
766 UINT8 DdiPortEdp;
767
768 /** Offset 0x0229 - Enable or disable HPD of DDI port B
769 0=Disable, 1(Default)=Enable
770 $EN_DIS
771 **/
772 UINT8 DdiPortBHpd;
773
774 /** Offset 0x022A - Enable or disable HPD of DDI port C
775 0=Disable, 1(Default)=Enable
776 $EN_DIS
777 **/
778 UINT8 DdiPortCHpd;
779
780 /** Offset 0x022B - Enable or disable HPD of DDI port D
781 0=Disable, 1(Default)=Enable
782 $EN_DIS
783 **/
784 UINT8 DdiPortDHpd;
785
786 /** Offset 0x022C - Enable or disable HPD of DDI port F
787 0=Disable, 1(Default)=Enable
788 $EN_DIS
789 **/
790 UINT8 DdiPortFHpd;
791
792 /** Offset 0x022D - Enable or disable DDC of DDI port B
793 0=Disable, 1(Default)=Enable
794 $EN_DIS
795 **/
796 UINT8 DdiPortBDdc;
797
798 /** Offset 0x022E - Enable or disable DDC of DDI port C
799 0=Disable, 1(Default)=Enable
800 $EN_DIS
801 **/
802 UINT8 DdiPortCDdc;
803
804 /** Offset 0x022F - Enable or disable DDC of DDI port D
805 0=Disable, 1(Default)=Enable
806 $EN_DIS
807 **/
808 UINT8 DdiPortDDdc;
809
810 /** Offset 0x0230 - Enable or disable DDC of DDI port F
811 0(Default)=Disable, 1=Enable
812 $EN_DIS
813 **/
814 UINT8 DdiPortFDdc;
815
816 /** Offset 0x0231 - Enable/Disable SkipS3CdClockInit
817 Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
818 CD clock in S3 resume due to GOP absent
819 $EN_DIS
820 **/
821 UINT8 SkipS3CdClockInit;
822
823 /** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms
824 Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
825 T12 Delay to max 500ms
826 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
827 **/
828 UINT16 DeltaT12PowerCycleDelay;
829
830 /** Offset 0x0234 - Blt Buffer Address
831 Address of Blt buffer
832 **/
833 UINT32 BltBufferAddress;
834
835 /** Offset 0x0238 - Blt Buffer Size
836 Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
837 EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
838 **/
839 UINT32 BltBufferSize;
840
841 /** Offset 0x023C - SaPostMemProductionRsvd
842 Reserved for SA Post-Mem Production
843 $EN_DIS
844 **/
845 UINT8 SaPostMemProductionRsvd[35];
846
847 /** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
848 PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
849 Alpine ridge
850 **/
851 UINT8 PcieRootPortGen2PllL1CgDisable[24];
852
853 /** Offset 0x0277 - Advanced Encryption Standard (AES) feature
854 Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
855 $EN_DIS
856 **/
857 UINT8 AesEnable;
858
859 /** Offset 0x0278 - Power State 3 enable/disable
860 PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
861 For all VR Indexes
862 **/
863 UINT8 Psi3Enable[5];
864
865 /** Offset 0x027D - Power State 4 enable/disable
866 PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
867 all VR Indexes
868 **/
869 UINT8 Psi4Enable[5];
870
871 /** Offset 0x0282 - Imon slope correction
872 PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
873 Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
874 **/
875 UINT8 ImonSlope[5];
876
877 /** Offset 0x0287 - Imon offset correction
878 PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
879 Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
880 **/
881 UINT8 ImonOffset[5];
882
883 /** Offset 0x028C - Enable/Disable BIOS configuration of VR
884 Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
885 **/
886 UINT8 VrConfigEnable[5];
887
888 /** Offset 0x0291 - Thermal Design Current enable/disable
889 PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
890 Enable.For all VR Indexes
891 **/
892 UINT8 TdcEnable[5];
893
894 /** Offset 0x0296 - HECI3 state
895 PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
896 Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
897 , 8 - 8ms , 10 - 10ms.For all VR Indexe
898 **/
899 UINT8 TdcTimeWindow[5];
900
901 /** Offset 0x029B - Thermal Design Current Lock
902 PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
903 all VR Indexes
904 **/
905 UINT8 TdcLock[5];
906
907 /** Offset 0x02A0 - Platform Psys slope correction
908 PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
909 1/100 increment values. Range is 0-200. 125 = 1.25
910 **/
911 UINT8 PsysSlope;
912
913 /** Offset 0x02A1 - Platform Psys offset correction
914 PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
915 Range 0-255. Value of 100 = 100/4 = 25 offset
916 **/
917 UINT8 PsysOffset;
918
919 /** Offset 0x02A2 - Acoustic Noise Mitigation feature
920 Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
921 slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
922 Disabled</b>; 1: Enabled
923 $EN_DIS
924 **/
925 UINT8 AcousticNoiseMitigation;
926
927 /** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
928 Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
929 feature enabled. <b>0: False</b>; 1: True
930 $EN_DIS
931 **/
932 UINT8 FastPkgCRampDisableIa;
933
934 /** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain
935 Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
936 Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
937 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
938 **/
939 UINT8 SlowSlewRateForIa;
940
941 /** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain
942 Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
943 Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
944 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
945 **/
946 UINT8 SlowSlewRateForGt;
947
948 /** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain
949 Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
950 Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
951 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
952 **/
953 UINT8 SlowSlewRateForSa;
954
955 /** Offset 0x02A7 - Thermal Design Current current limit
956 PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
957 Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
958 **/
959 UINT16 TdcPowerLimit[5];
960
961 /** Offset 0x02B1 - AcLoadline
962 PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
963 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
964 **/
965 UINT16 AcLoadline[5];
966
967 /** Offset 0x02BB
968 **/
969 UINT8 UnusedUpdSpace8[10];
970
971 /** Offset 0x02C5 - DcLoadline
972 PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
973 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
974 **/
975 UINT16 DcLoadline[5];
976
977 /** Offset 0x02CF - Power State 1 Threshold current
978 PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
979 **/
980 UINT16 Psi1Threshold[5];
981
982 /** Offset 0x02D9 - Power State 2 Threshold current
983 PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
984 **/
985 UINT16 Psi2Threshold[5];
986
987 /** Offset 0x02E3 - Power State 3 Threshold current
988 PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
989 **/
990 UINT16 Psi3Threshold[5];
991
992 /** Offset 0x02ED - Icc Max limit
993 PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
994 **/
995 UINT16 IccMax[5];
996
997 /** Offset 0x02F7 - VR Voltage Limit
998 PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
999 **/
1000 UINT16 VrVoltageLimit[5];
1001
1002 /** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
1003 Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
1004 feature enabled. <b>0: False</b>; 1: True
1005 $EN_DIS
1006 **/
1007 UINT8 FastPkgCRampDisableGt;
1008
1009 /** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
1010 Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
1011 feature enabled. <b>0: False</b>; 1: True
1012 $EN_DIS
1013 **/
1014 UINT8 FastPkgCRampDisableSa;
1015
1016 /** Offset 0x0303 - Enable VR specific mailbox command
1017 VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
1018 VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
1019 command sent for PS4 exit issue. 11b - Reserved.
1020 $EN_DIS
1021 **/
1022 UINT8 SendVrMbxCmd;
1023
1024 /** Offset 0x0304 - Reserved
1025 Reserved
1026 **/
1027 UINT8 Reserved2;
1028
1029 /** Offset 0x0305 - Enable or Disable TXT
1030 Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
1031 $EN_DIS
1032 **/
1033 UINT8 TxtEnable;
1034
1035 /** Offset 0x0306
1036 **/
1037 UINT8 UnusedUpdSpace9[6];
1038
1039 /** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization
1040 @deprecated SkipMpInit has been moved to FspmUpd
1041 $EN_DIS
1042 **/
1043 UINT8 SkipMpInit;
1044
1045 /** Offset 0x030D - McIVR RFI Frequency Prefix
1046 PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:
1047 Minus (-).
1048 **/
1049 UINT8 McivrRfiFrequencyPrefix;
1050
1051 /** Offset 0x030E - McIVR RFI Frequency Adjustment
1052 PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in
1053 increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.
1054 **/
1055 UINT8 McivrRfiFrequencyAdjust;
1056
1057 /** Offset 0x030F - FIVR RFI Frequency
1058 PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
1059 Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
1060 0-1535 (Up to 153.5MHz) for 19MHz clock.
1061 **/
1062 UINT16 FivrRfiFrequency;
1063
1064 /** Offset 0x0311 - McIVR RFI Spread Spectrum
1065 PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-
1066 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.
1067 **/
1068 UINT8 McivrSpreadSpectrum;
1069
1070 /** Offset 0x0312 - FIVR RFI Spread Spectrum
1071 PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
1072 Range: 0.0% to 10.0% (0-100).
1073 **/
1074 UINT8 FivrSpreadSpectrum;
1075
1076 /** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
1077 Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
1078 feature enabled. <b>0: False</b>; 1: True
1079 $EN_DIS
1080 **/
1081 UINT8 FastPkgCRampDisableFivr;
1082
1083 /** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain
1084 Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic
1085 Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
1086 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
1087 **/
1088 UINT8 SlowSlewRateForFivr;
1089
1090 /** Offset 0x0315 - CpuBistData
1091 Pointer CPU BIST Data
1092 **/
1093 UINT32 CpuBistData;
1094
1095 /** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.
1096 Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
1097 command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
1098 **/
1099 UINT8 IslVrCmd;
1100
1101 /** Offset 0x031A - Imon slope1 correction
1102 PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
1103 Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
1104 **/
1105 UINT16 ImonSlope1[5];
1106
1107 /** Offset 0x0324 - CPU VR Power Delivery Design
1108 Used to communicate the power delivery design capability of the board. This value
1109 is an enum of the available power delivery segments that are defined in the Platform
1110 Design Guide.
1111 **/
1112 UINT32 VrPowerDeliveryDesign;
1113
1114 /** Offset 0x0328 - Pre Wake Randomization time
1115 PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
1116 time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
1117 Range 0-255 <b>0</b>.
1118 **/
1119 UINT8 PreWake;
1120
1121 /** Offset 0x0329 - Ramp Up Randomization time
1122 PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
1123 time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
1124 0-255 <b>0</b>.
1125 **/
1126 UINT8 RampUp;
1127
1128 /** Offset 0x032A - Ramp Down Randomization time
1129 PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
1130 time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
1131 0-255 <b>0</b>.
1132 **/
1133 UINT8 RampDown;
1134
1135 /** Offset 0x032B - CpuMpPpi
1136 Pointer for CpuMpPpi
1137 **/
1138 UINT32 CpuMpPpi;
1139
1140 /** Offset 0x032F - CpuMpHob
1141 Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage.
1142 **/
1143 UINT32 CpuMpHob;
1144
1145 /** Offset 0x0333 - Enable or Disable processor debug features
1146 Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
1147 $EN_DIS
1148 **/
1149 UINT8 DebugInterfaceEnable;
1150
1151 /** Offset 0x0334 - ReservedCpuPostMemProduction
1152 Reserved for CPU Post-Mem Production
1153 $EN_DIS
1154 **/
1155 UINT8 ReservedCpuPostMemProduction[18];
1156
1157 /** Offset 0x0346 - Enable DMI ASPM
1158 Deprecated.
1159 $EN_DIS
1160 **/
1161 UINT8 PchDmiAspm;
1162
1163 /** Offset 0x0347 - Enable Power Optimizer
1164 Enable DMI Power Optimizer on PCH side.
1165 $EN_DIS
1166 **/
1167 UINT8 PchPwrOptEnable;
1168
1169 /** Offset 0x0348 - PCH Flash Protection Ranges Write Enble
1170 Write or erase is blocked by hardware.
1171 **/
1172 UINT8 PchWriteProtectionEnable[5];
1173
1174 /** Offset 0x034D - PCH Flash Protection Ranges Read Enble
1175 Read is blocked by hardware.
1176 **/
1177 UINT8 PchReadProtectionEnable[5];
1178
1179 /** Offset 0x0352 - PCH Protect Range Limit
1180 Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
1181 limit comparison.
1182 **/
1183 UINT16 PchProtectedRangeLimit[5];
1184
1185 /** Offset 0x035C - PCH Protect Range Base
1186 Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
1187 **/
1188 UINT16 PchProtectedRangeBase[5];
1189
1190 /** Offset 0x0366 - Enable Pme
1191 Enable Azalia wake-on-ring.
1192 $EN_DIS
1193 **/
1194 UINT8 PchHdaPme;
1195
1196 /** Offset 0x0367
1197 **/
1198 UINT8 UnusedUpdSpace10;
1199
1200 /** Offset 0x0368 - VC Type
1201 Virtual Channel Type Select: 0: VC0, 1: VC1.
1202 0: VC0, 1: VC1
1203 **/
1204 UINT8 PchHdaVcType;
1205
1206 /** Offset 0x0369 - HD Audio Link Frequency
1207 HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
1208 0: 6MHz, 1: 12MHz, 2: 24MHz
1209 **/
1210 UINT8 PchHdaLinkFrequency;
1211
1212 /** Offset 0x036A - iDisp-Link Frequency
1213 iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
1214 4: 96MHz, 3: 48MHz
1215 **/
1216 UINT8 PchHdaIDispLinkFrequency;
1217
1218 /** Offset 0x036B - iDisp-Link T-mode
1219 iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
1220 0: 2T, 1: 1T
1221 **/
1222 UINT8 PchHdaIDispLinkTmode;
1223
1224 /** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system
1225 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
1226 driver or SST driver supported).
1227 $EN_DIS
1228 **/
1229 UINT8 PchHdaDspUaaCompliance;
1230
1231 /** Offset 0x036D - iDisplay Audio Codec disconnection
1232 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
1233 $EN_DIS
1234 **/
1235 UINT8 PchHdaIDispCodecDisconnect;
1236
1237 /** Offset 0x036E - USB LFPS Filter selection
1238 For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns,
1239 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns.
1240 **/
1241 UINT8 PchUsbHsioFilterSel[10];
1242
1243 /** Offset 0x0378
1244 **/
1245 UINT8 UnusedUpdSpace11[5];
1246
1247 /** Offset 0x037D - Enable PCH Io Apic Entry 24-119
1248 0: Disable; 1: Enable.
1249 $EN_DIS
1250 **/
1251 UINT8 PchIoApicEntry24_119;
1252
1253 /** Offset 0x037E - PCH Io Apic ID
1254 This member determines IOAPIC ID. Default is 0x02.
1255 **/
1256 UINT8 PchIoApicId;
1257
1258 /** Offset 0x037F
1259 **/
1260 UINT8 UnusedUpdSpace12;
1261
1262 /** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
1263 0: Disable; 1: Enable.
1264 $EN_DIS
1265 **/
1266 UINT8 PchIshSpiGpioAssign;
1267
1268 /** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned
1269 0: Disable; 1: Enable.
1270 $EN_DIS
1271 **/
1272 UINT8 PchIshUart0GpioAssign;
1273
1274 /** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned
1275 0: Disable; 1: Enable.
1276 $EN_DIS
1277 **/
1278 UINT8 PchIshUart1GpioAssign;
1279
1280 /** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned
1281 0: Disable; 1: Enable.
1282 $EN_DIS
1283 **/
1284 UINT8 PchIshI2c0GpioAssign;
1285
1286 /** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned
1287 0: Disable; 1: Enable.
1288 $EN_DIS
1289 **/
1290 UINT8 PchIshI2c1GpioAssign;
1291
1292 /** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned
1293 0: Disable; 1: Enable.
1294 $EN_DIS
1295 **/
1296 UINT8 PchIshI2c2GpioAssign;
1297
1298 /** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned
1299 0: Disable; 1: Enable.
1300 $EN_DIS
1301 **/
1302 UINT8 PchIshGp0GpioAssign;
1303
1304 /** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned
1305 0: Disable; 1: Enable.
1306 $EN_DIS
1307 **/
1308 UINT8 PchIshGp1GpioAssign;
1309
1310 /** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned
1311 0: Disable; 1: Enable.
1312 $EN_DIS
1313 **/
1314 UINT8 PchIshGp2GpioAssign;
1315
1316 /** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned
1317 0: Disable; 1: Enable.
1318 $EN_DIS
1319 **/
1320 UINT8 PchIshGp3GpioAssign;
1321
1322 /** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned
1323 0: Disable; 1: Enable.
1324 $EN_DIS
1325 **/
1326 UINT8 PchIshGp4GpioAssign;
1327
1328 /** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned
1329 0: Disable; 1: Enable.
1330 $EN_DIS
1331 **/
1332 UINT8 PchIshGp5GpioAssign;
1333
1334 /** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned
1335 0: Disable; 1: Enable.
1336 $EN_DIS
1337 **/
1338 UINT8 PchIshGp6GpioAssign;
1339
1340 /** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned
1341 0: Disable; 1: Enable.
1342 $EN_DIS
1343 **/
1344 UINT8 PchIshGp7GpioAssign;
1345
1346 /** Offset 0x038E - PCH ISH PDT Unlock Msg
1347 0: False; 1: True.
1348 $EN_DIS
1349 **/
1350 UINT8 PchIshPdtUnlock;
1351
1352 /** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN
1353 0: Disable; 1: Enable.
1354 $EN_DIS
1355 **/
1356 UINT8 PchLanLtrEnable;
1357
1358 /** Offset 0x0390
1359 **/
1360 UINT8 UnusedUpdSpace13[3];
1361
1362 /** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
1363 Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
1364 protection.
1365 $EN_DIS
1366 **/
1367 UINT8 PchLockDownBiosLock;
1368
1369 /** Offset 0x0394 - PCH Compatibility Revision ID
1370 This member describes whether or not the CRID feature of PCH should be enabled.
1371 $EN_DIS
1372 **/
1373 UINT8 PchCrid;
1374
1375 /** Offset 0x0395 - RTC CMOS MEMORY LOCK
1376 Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
1377 and and lower 128-byte bank of RTC RAM.
1378 $EN_DIS
1379 **/
1380 UINT8 PchLockDownRtcMemoryLock;
1381
1382 /** Offset 0x0396 - Enable PCIE RP HotPlug
1383 Indicate whether the root port is hot plug available.
1384 **/
1385 UINT8 PcieRpHotPlug[24];
1386
1387 /** Offset 0x03AE - Enable PCIE RP Pm Sci
1388 Indicate whether the root port power manager SCI is enabled.
1389 **/
1390 UINT8 PcieRpPmSci[24];
1391
1392 /** Offset 0x03C6 - Enable PCIE RP Ext Sync
1393 Indicate whether the extended synch is enabled.
1394 **/
1395 UINT8 PcieRpExtSync[24];
1396
1397 /** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing
1398 Indicate whether the Transmitter Half Swing is enabled.
1399 **/
1400 UINT8 PcieRpTransmitterHalfSwing[24];
1401
1402 /** Offset 0x03F6 - Enable PCIE RP Clk Req Detect
1403 Probe CLKREQ# signal before enabling CLKREQ# based power management.
1404 **/
1405 UINT8 PcieRpClkReqDetect[24];
1406
1407 /** Offset 0x040E - PCIE RP Advanced Error Report
1408 Indicate whether the Advanced Error Reporting is enabled.
1409 **/
1410 UINT8 PcieRpAdvancedErrorReporting[24];
1411
1412 /** Offset 0x0426 - PCIE RP Unsupported Request Report
1413 Indicate whether the Unsupported Request Report is enabled.
1414 **/
1415 UINT8 PcieRpUnsupportedRequestReport[24];
1416
1417 /** Offset 0x043E - PCIE RP Fatal Error Report
1418 Indicate whether the Fatal Error Report is enabled.
1419 **/
1420 UINT8 PcieRpFatalErrorReport[24];
1421
1422 /** Offset 0x0456 - PCIE RP No Fatal Error Report
1423 Indicate whether the No Fatal Error Report is enabled.
1424 **/
1425 UINT8 PcieRpNoFatalErrorReport[24];
1426
1427 /** Offset 0x046E - PCIE RP Correctable Error Report
1428 Indicate whether the Correctable Error Report is enabled.
1429 **/
1430 UINT8 PcieRpCorrectableErrorReport[24];
1431
1432 /** Offset 0x0486 - PCIE RP System Error On Fatal Error
1433 Indicate whether the System Error on Fatal Error is enabled.
1434 **/
1435 UINT8 PcieRpSystemErrorOnFatalError[24];
1436
1437 /** Offset 0x049E - PCIE RP System Error On Non Fatal Error
1438 Indicate whether the System Error on Non Fatal Error is enabled.
1439 **/
1440 UINT8 PcieRpSystemErrorOnNonFatalError[24];
1441
1442 /** Offset 0x04B6 - PCIE RP System Error On Correctable Error
1443 Indicate whether the System Error on Correctable Error is enabled.
1444 **/
1445 UINT8 PcieRpSystemErrorOnCorrectableError[24];
1446
1447 /** Offset 0x04CE - PCIE RP Max Payload
1448 Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
1449 **/
1450 UINT8 PcieRpMaxPayload[24];
1451
1452 /** Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters
1453 Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for
1454 controlling the input offset
1455 **/
1456 UINT8 PchUsbHsioRxTuningParameters[10];
1457
1458 /** Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable
1459 Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable,
1460 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable
1461 **/
1462 UINT8 PchUsbHsioRxTuningEnable[10];
1463
1464 /** Offset 0x04FA
1465 **/
1466 UINT8 UnusedUpdSpace14[4];
1467
1468 /** Offset 0x04FE - PCIE RP Pcie Speed
1469 Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
1470 PCH_PCIE_SPEED).
1471 **/
1472 UINT8 PcieRpPcieSpeed[24];
1473
1474 /** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method
1475 PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
1476 1: hardware equalization; 4: Fixed Coeficients.
1477 **/
1478 UINT8 PcieRpGen3EqPh3Method[24];
1479
1480 /** Offset 0x052E - PCIE RP Physical Slot Number
1481 Indicates the slot number for the root port. Default is the value as root port index.
1482 **/
1483 UINT8 PcieRpPhysicalSlotNumber[24];
1484
1485 /** Offset 0x0546 - PCIE RP Completion Timeout
1486 The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
1487 **/
1488 UINT8 PcieRpCompletionTimeout[24];
1489
1490 /** Offset 0x055E
1491 **/
1492 UINT8 UnusedUpdSpace15[106];
1493
1494 /** Offset 0x05C8 - PCIE RP Aspm
1495 The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
1496 PchPcieAspmAutoConfig.
1497 **/
1498 UINT8 PcieRpAspm[24];
1499
1500 /** Offset 0x05E0 - PCIE RP L1 Substates
1501 The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
1502 Default is PchPcieL1SubstatesL1_1_2.
1503 **/
1504 UINT8 PcieRpL1Substates[24];
1505
1506 /** Offset 0x05F8 - PCIE RP Ltr Enable
1507 Latency Tolerance Reporting Mechanism.
1508 **/
1509 UINT8 PcieRpLtrEnable[24];
1510
1511 /** Offset 0x0610 - PCIE RP Ltr Config Lock
1512 0: Disable; 1: Enable.
1513 **/
1514 UINT8 PcieRpLtrConfigLock[24];
1515
1516 /** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm
1517 PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
1518 **/
1519 UINT8 PcieEqPh3LaneParamCm[24];
1520
1521 /** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp
1522 PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
1523 **/
1524 UINT8 PcieEqPh3LaneParamCp[24];
1525
1526 /** Offset 0x0658 - PCIE Sw Eq CoeffList Cm
1527 PCH_PCIE_EQ_PARAM. Coefficient C-1.
1528 **/
1529 UINT8 PcieSwEqCoeffListCm[5];
1530
1531 /** Offset 0x065D - PCIE Sw Eq CoeffList Cp
1532 PCH_PCIE_EQ_PARAM. Coefficient C+1.
1533 **/
1534 UINT8 PcieSwEqCoeffListCp[5];
1535
1536 /** Offset 0x0662 - PCIE Disable RootPort Clock Gating
1537 Describes whether the PCI Express Clock Gating for each root port is enabled by
1538 platform modules. 0: Disable; 1: Enable.
1539 $EN_DIS
1540 **/
1541 UINT8 PcieDisableRootPortClockGating;
1542
1543 /** Offset 0x0663 - PCIE Enable Peer Memory Write
1544 This member describes whether Peer Memory Writes are enabled on the platform.
1545 $EN_DIS
1546 **/
1547 UINT8 PcieEnablePeerMemoryWrite;
1548
1549 /** Offset 0x0664
1550 **/
1551 UINT8 UnusedUpdSpace16;
1552
1553 /** Offset 0x0665 - PCIE Compliance Test Mode
1554 Compliance Test Mode shall be enabled when using Compliance Load Board.
1555 $EN_DIS
1556 **/
1557 UINT8 PcieComplianceTestMode;
1558
1559 /** Offset 0x0666 - PCIE Rp Function Swap
1560 Allows BIOS to use root port function number swapping when root port of function
1561 0 is disabled.
1562 $EN_DIS
1563 **/
1564 UINT8 PcieRpFunctionSwap;
1565
1566 /** Offset 0x0667 - Teton Glacier Support
1567 Enables support for the Teton Glacier card.
1568 $EN_DIS
1569 **/
1570 UINT8 TetonGlacierSupport;
1571
1572 /** Offset 0x0668 - Teton Glacier Cycle Router
1573 Specify to which cycle router Teton Glacier is connected, it is valid only when
1574 Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system
1575 **/
1576 UINT8 TetonGlacierCR;
1577
1578 /** Offset 0x0669 - PCH Pm PME_B0_S5_DIS
1579 When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
1580 $EN_DIS
1581 **/
1582 UINT8 PchPmPmeB0S5Dis;
1583
1584 /** Offset 0x066A - SPI ChipSelect signal polarity
1585 Selects SPI ChipSelect signal polarity.
1586 **/
1587 UINT8 SerialIoSpiCsPolarity[3];
1588
1589 /** Offset 0x066D - PCIE IMR
1590 Enables Isolated Memory Region for PCIe.
1591 $EN_DIS
1592 **/
1593 UINT8 PcieRpImrEnabled;
1594
1595 /** Offset 0x066E - PCIE IMR port number
1596 Selects PCIE root port number for IMR feature.
1597 **/
1598 UINT8 PcieRpImrSelection;
1599
1600 /** Offset 0x066F
1601 **/
1602 UINT8 UnusedUpdSpace17;
1603
1604 /** Offset 0x0670 - PCH Pm Wol Enable Override
1605 Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
1606 $EN_DIS
1607 **/
1608 UINT8 PchPmWolEnableOverride;
1609
1610 /** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx
1611 Determine if enable PCIe to wake from deep Sx.
1612 $EN_DIS
1613 **/
1614 UINT8 PchPmPcieWakeFromDeepSx;
1615
1616 /** Offset 0x0672 - PCH Pm WoW lan Enable
1617 Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
1618 $EN_DIS
1619 **/
1620 UINT8 PchPmWoWlanEnable;
1621
1622 /** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable
1623 Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
1624 PWRM_CFG3 register.
1625 $EN_DIS
1626 **/
1627 UINT8 PchPmWoWlanDeepSxEnable;
1628
1629 /** Offset 0x0674 - PCH Pm Lan Wake From DeepSx
1630 Determine if enable LAN to wake from deep Sx.
1631 $EN_DIS
1632 **/
1633 UINT8 PchPmLanWakeFromDeepSx;
1634
1635 /** Offset 0x0675 - PCH Pm Deep Sx Pol
1636 Deep Sx Policy.
1637 $EN_DIS
1638 **/
1639 UINT8 PchPmDeepSxPol;
1640
1641 /** Offset 0x0676 - PCH Pm Slp S3 Min Assert
1642 SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
1643 **/
1644 UINT8 PchPmSlpS3MinAssert;
1645
1646 /** Offset 0x0677 - PCH Pm Slp S4 Min Assert
1647 SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
1648 **/
1649 UINT8 PchPmSlpS4MinAssert;
1650
1651 /** Offset 0x0678 - PCH Pm Slp Sus Min Assert
1652 SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
1653 **/
1654 UINT8 PchPmSlpSusMinAssert;
1655
1656 /** Offset 0x0679 - PCH Pm Slp A Min Assert
1657 SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
1658 **/
1659 UINT8 PchPmSlpAMinAssert;
1660
1661 /** Offset 0x067A - SLP_S0# Override
1662 Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
1663 will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
1664 when debug is enabled. \n
1665 Note: This BIOS option should keep 'Auto', other options are intended for advanced
1666 configuration only.
1667 0:Disabled, 1:Enabled, 2:Auto
1668 **/
1669 UINT8 SlpS0Override;
1670
1671 /** Offset 0x067B - S0ix Override Settings
1672 Select 'Auto', it will be auto-configured according to probe type. 'No Change' will
1673 keep PMC default settings. Or select the desired debug probe type for S0ix Override
1674 settings.\n
1675 Reminder: DCI OOB (aka BSSB) uses CCA probe.\n
1676 Note: This BIOS option should keep 'Auto', other options are intended for advanced
1677 configuration only.
1678 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto
1679 **/
1680 UINT8 SlpS0DisQForDebug;
1681
1682 /** Offset 0x067C - USB Overcurrent Override for DbC
1683 This option overrides USB Over Current enablement state that USB OC will be disabled
1684 after enabling this option. Enable when DbC is used to avoid signaling conflicts.
1685 $EN_DIS
1686 **/
1687 UINT8 PchEnableDbcObs;
1688
1689 /** Offset 0x067D
1690 **/
1691 UINT8 UnusedUpdSpace18[3];
1692
1693 /** Offset 0x0680 - PCH Pm Lpc Clock Run
1694 This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
1695 Default value is Disabled
1696 $EN_DIS
1697 **/
1698 UINT8 PchPmLpcClockRun;
1699
1700 /** Offset 0x0681 - PCH Pm Slp Strch Sus Up
1701 Enable SLP_X Stretching After SUS Well Power Up.
1702 $EN_DIS
1703 **/
1704 UINT8 PchPmSlpStrchSusUp;
1705
1706 /** Offset 0x0682 - PCH Pm Slp Lan Low Dc
1707 Enable/Disable SLP_LAN# Low on DC Power.
1708 $EN_DIS
1709 **/
1710 UINT8 PchPmSlpLanLowDc;
1711
1712 /** Offset 0x0683 - PCH Pm Pwr Btn Override Period
1713 PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
1714 **/
1715 UINT8 PchPmPwrBtnOverridePeriod;
1716
1717 /** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown
1718 When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
1719 $EN_DIS
1720 **/
1721 UINT8 PchPmDisableDsxAcPresentPulldown;
1722
1723 /** Offset 0x0685
1724 **/
1725 UINT8 UnusedUpdSpace19;
1726
1727 /** Offset 0x0686 - PCH Pm Disable Native Power Button
1728 Power button native mode disable.
1729 $EN_DIS
1730 **/
1731 UINT8 PchPmDisableNativePowerButton;
1732
1733 /** Offset 0x0687 - PCH Pm Slp S0 Enable
1734 Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
1735 $EN_DIS
1736 **/
1737 UINT8 PchPmSlpS0Enable;
1738
1739 /** Offset 0x0688 - PCH Pm ME_WAKE_STS
1740 Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
1741 $EN_DIS
1742 **/
1743 UINT8 PchPmMeWakeSts;
1744
1745 /** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS
1746 Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
1747 $EN_DIS
1748 **/
1749 UINT8 PchPmWolOvrWkSts;
1750
1751 /** Offset 0x068A - PCH Pm Reset Power Cycle Duration
1752 Could be customized in the unit of second. Please refer to EDS for all support settings.
1753 0 is default, 1 is 1 second, 2 is 2 seconds, ...
1754 **/
1755 UINT8 PchPmPwrCycDur;
1756
1757 /** Offset 0x068B - PCH Pm Pcie Pll Ssc
1758 Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
1759 BIOS override.
1760 **/
1761 UINT8 PchPmPciePllSsc;
1762
1763 /** Offset 0x068C
1764 **/
1765 UINT8 UnusedUpdSpace20;
1766
1767 /** Offset 0x068D - PCH Sata Pwr Opt Enable
1768 SATA Power Optimizer on PCH side.
1769 $EN_DIS
1770 **/
1771 UINT8 SataPwrOptEnable;
1772
1773 /** Offset 0x068E - PCH Sata eSATA Speed Limit
1774 When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
1775 $EN_DIS
1776 **/
1777 UINT8 EsataSpeedLimit;
1778
1779 /** Offset 0x068F - PCH Sata Speed Limit
1780 Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
1781 **/
1782 UINT8 SataSpeedLimit;
1783
1784 /** Offset 0x0690 - Enable SATA Port HotPlug
1785 Enable SATA Port HotPlug.
1786 **/
1787 UINT8 SataPortsHotPlug[8];
1788
1789 /** Offset 0x0698 - Enable SATA Port Interlock Sw
1790 Enable SATA Port Interlock Sw.
1791 **/
1792 UINT8 SataPortsInterlockSw[8];
1793
1794 /** Offset 0x06A0 - Enable SATA Port External
1795 Enable SATA Port External.
1796 **/
1797 UINT8 SataPortsExternal[8];
1798
1799 /** Offset 0x06A8 - Enable SATA Port SpinUp
1800 Enable the COMRESET initialization Sequence to the device.
1801 **/
1802 UINT8 SataPortsSpinUp[8];
1803
1804 /** Offset 0x06B0 - Enable SATA Port Solid State Drive
1805 0: HDD; 1: SSD.
1806 **/
1807 UINT8 SataPortsSolidStateDrive[8];
1808
1809 /** Offset 0x06B8 - Enable SATA Port Enable Dito Config
1810 Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
1811 **/
1812 UINT8 SataPortsEnableDitoConfig[8];
1813
1814 /** Offset 0x06C0 - Enable SATA Port DmVal
1815 DITO multiplier. Default is 15.
1816 **/
1817 UINT8 SataPortsDmVal[8];
1818
1819 /** Offset 0x06C8 - Enable SATA Port DmVal
1820 DEVSLP Idle Timeout (DITO), Default is 625.
1821 **/
1822 UINT16 SataPortsDitoVal[8];
1823
1824 /** Offset 0x06D8 - Enable SATA Port ZpOdd
1825 Support zero power ODD.
1826 **/
1827 UINT8 SataPortsZpOdd[8];
1828
1829 /** Offset 0x06E0 - PCH Sata Rst Raid Device Id
1830 Enable RAID Alternate ID.
1831 0:Client, 1:Alternate, 2:Server
1832 **/
1833 UINT8 SataRstRaidDeviceId;
1834
1835 /** Offset 0x06E1 - PCH Sata Rst Raid0
1836 RAID0.
1837 $EN_DIS
1838 **/
1839 UINT8 SataRstRaid0;
1840
1841 /** Offset 0x06E2 - PCH Sata Rst Raid1
1842 RAID1.
1843 $EN_DIS
1844 **/
1845 UINT8 SataRstRaid1;
1846
1847 /** Offset 0x06E3 - PCH Sata Rst Raid10
1848 RAID10.
1849 $EN_DIS
1850 **/
1851 UINT8 SataRstRaid10;
1852
1853 /** Offset 0x06E4 - PCH Sata Rst Raid5
1854 RAID5.
1855 $EN_DIS
1856 **/
1857 UINT8 SataRstRaid5;
1858
1859 /** Offset 0x06E5 - PCH Sata Rst Irrt
1860 Intel Rapid Recovery Technology.
1861 $EN_DIS
1862 **/
1863 UINT8 SataRstIrrt;
1864
1865 /** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner
1866 OROM UI and BANNER.
1867 $EN_DIS
1868 **/
1869 UINT8 SataRstOromUiBanner;
1870
1871 /** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay
1872 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
1873 **/
1874 UINT8 SataRstOromUiDelay;
1875
1876 /** Offset 0x06E8 - PCH Sata Rst Hdd Unlock
1877 Indicates that the HDD password unlock in the OS is enabled.
1878 $EN_DIS
1879 **/
1880 UINT8 SataRstHddUnlock;
1881
1882 /** Offset 0x06E9 - PCH Sata Rst Led Locate
1883 Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
1884 enabled on the OS.
1885 $EN_DIS
1886 **/
1887 UINT8 SataRstLedLocate;
1888
1889 /** Offset 0x06EA - PCH Sata Rst Irrt Only
1890 Allow only IRRT drives to span internal and external ports.
1891 $EN_DIS
1892 **/
1893 UINT8 SataRstIrrtOnly;
1894
1895 /** Offset 0x06EB - PCH Sata Rst Smart Storage
1896 RST Smart Storage caching Bit.
1897 $EN_DIS
1898 **/
1899 UINT8 SataRstSmartStorage;
1900
1901 /** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable
1902 Enable Intel RST for PCIe Storage remapping.
1903 **/
1904 UINT8 SataRstPcieEnable[3];
1905
1906 /** Offset 0x06EF - PCH Sata Rst Pcie Storage Port
1907 Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
1908 **/
1909 UINT8 SataRstPcieStoragePort[3];
1910
1911 /** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay
1912 PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
1913 **/
1914 UINT8 SataRstPcieDeviceResetDelay[3];
1915
1916 /** Offset 0x06F5 - Enable eMMC HS400 Training
1917 Deprecated.
1918 $EN_DIS
1919 **/
1920 UINT8 PchScsEmmcHs400TuningRequired;
1921
1922 /** Offset 0x06F6 - Set HS400 Tuning Data Valid
1923 Set if HS400 Tuning Data Valid.
1924 $EN_DIS
1925 **/
1926 UINT8 PchScsEmmcHs400DllDataValid;
1927
1928 /** Offset 0x06F7 - Rx Strobe Delay Control
1929 Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
1930 **/
1931 UINT8 PchScsEmmcHs400RxStrobeDll1;
1932
1933 /** Offset 0x06F8 - Tx Data Delay Control
1934 Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
1935 **/
1936 UINT8 PchScsEmmcHs400TxDataDll;
1937
1938 /** Offset 0x06F9 - I/O Driver Strength
1939 Deprecated.
1940 0:33 Ohm, 1:40 Ohm, 2:50 Ohm
1941 **/
1942 UINT8 PchScsEmmcHs400DriverStrength;
1943
1944 /** Offset 0x06FA - PCH SerialIo I2C Pads Termination
1945 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
1946 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
1947 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
1948 for I2C1, and so on.
1949 **/
1950 UINT8 PchSerialIoI2cPadsTermination[6];
1951
1952 /** Offset 0x0700
1953 **/
1954 UINT8 UnusedUpdSpace21;
1955
1956 /** Offset 0x0701 - PcdSerialIoUart0PinMuxing
1957 Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
1958 0:default pins, 1:pins muxed with CNV_BRI/RGI
1959 **/
1960 UINT8 SerialIoUart0PinMuxing;
1961
1962 /** Offset 0x0702
1963 **/
1964 UINT8 UnusedUpdSpace22[1];
1965
1966 /** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
1967 Enables UART hardware flow control, CTS and RTS linesh.
1968 **/
1969 UINT8 SerialIoUartHwFlowCtrl[3];
1970
1971 /** Offset 0x0706 - UART Number For Debug Purpose
1972 UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected
1973 as CNVi BT Core interface, it cannot be used for debug purpose.
1974 0:UART0, 1:UART1, 2:UART2
1975 **/
1976 UINT8 SerialIoDebugUartNumber;
1977
1978 /** Offset 0x0707 - Enable Debug UART Controller
1979 Enable debug UART controller after post.
1980 $EN_DIS
1981 **/
1982 UINT8 SerialIoEnableDebugUartAfterPost;
1983
1984 /** Offset 0x0708 - Enable Serial IRQ
1985 Determines if enable Serial IRQ.
1986 $EN_DIS
1987 **/
1988 UINT8 PchSirqEnable;
1989
1990 /** Offset 0x0709 - Serial IRQ Mode Select
1991 Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
1992 $EN_DIS
1993 **/
1994 UINT8 PchSirqMode;
1995
1996 /** Offset 0x070A - Start Frame Pulse Width
1997 Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
1998 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk
1999 **/
2000 UINT8 PchStartFramePulse;
2001
2002 /** Offset 0x070B - Reserved
2003 Reserved
2004 $EN_DIS
2005 **/
2006 UINT8 ReservedForFuture1;
2007
2008 /** Offset 0x070C - Thermal Device SMI Enable
2009 This locks down SMI Enable on Alert Thermal Sensor Trip.
2010 $EN_DIS
2011 **/
2012 UINT8 PchTsmicLock;
2013
2014 /** Offset 0x070D - Thermal Throttling Custimized T0Level Value
2015 Custimized T0Level value.
2016 **/
2017 UINT16 PchT0Level;
2018
2019 /** Offset 0x070F - Thermal Throttling Custimized T1Level Value
2020 Custimized T1Level value.
2021 **/
2022 UINT16 PchT1Level;
2023
2024 /** Offset 0x0711 - Thermal Throttling Custimized T2Level Value
2025 Custimized T2Level value.
2026 **/
2027 UINT16 PchT2Level;
2028
2029 /** Offset 0x0713 - Enable The Thermal Throttle
2030 Enable the thermal throttle function.
2031 $EN_DIS
2032 **/
2033 UINT8 PchTTEnable;
2034
2035 /** Offset 0x0714 - PMSync State 13
2036 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
2037 at least T2 state.
2038 $EN_DIS
2039 **/
2040 UINT8 PchTTState13Enable;
2041
2042 /** Offset 0x0715 - Thermal Throttle Lock
2043 Thermal Throttle Lock.
2044 $EN_DIS
2045 **/
2046 UINT8 PchTTLock;
2047
2048 /** Offset 0x0716 - Thermal Throttling Suggested Setting
2049 Thermal Throttling Suggested Setting.
2050 $EN_DIS
2051 **/
2052 UINT8 TTSuggestedSetting;
2053
2054 /** Offset 0x0717 - Enable PCH Cross Throttling
2055 Enable/Disable PCH Cross Throttling
2056 $EN_DIS
2057 **/
2058 UINT8 TTCrossThrottling;
2059
2060 /** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable
2061 DMI Thermal Sensor Autonomous Width Enable.
2062 $EN_DIS
2063 **/
2064 UINT8 PchDmiTsawEn;
2065
2066 /** Offset 0x0719 - DMI Thermal Sensor Suggested Setting
2067 DMT thermal sensor suggested representative values.
2068 $EN_DIS
2069 **/
2070 UINT8 DmiSuggestedSetting;
2071
2072 /** Offset 0x071A - Thermal Sensor 0 Target Width
2073 DMT thermal sensor suggested representative values.
2074 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2075 **/
2076 UINT8 DmiTS0TW;
2077
2078 /** Offset 0x071B - Thermal Sensor 1 Target Width
2079 Thermal Sensor 1 Target Width.
2080 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2081 **/
2082 UINT8 DmiTS1TW;
2083
2084 /** Offset 0x071C - Thermal Sensor 2 Target Width
2085 Thermal Sensor 2 Target Width.
2086 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2087 **/
2088 UINT8 DmiTS2TW;
2089
2090 /** Offset 0x071D - Thermal Sensor 3 Target Width
2091 Thermal Sensor 3 Target Width.
2092 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2093 **/
2094 UINT8 DmiTS3TW;
2095
2096 /** Offset 0x071E - Port 0 T1 Multipler
2097 Port 0 T1 Multipler.
2098 **/
2099 UINT8 SataP0T1M;
2100
2101 /** Offset 0x071F - Port 0 T2 Multipler
2102 Port 0 T2 Multipler.
2103 **/
2104 UINT8 SataP0T2M;
2105
2106 /** Offset 0x0720 - Port 0 T3 Multipler
2107 Port 0 T3 Multipler.
2108 **/
2109 UINT8 SataP0T3M;
2110
2111 /** Offset 0x0721 - Port 0 Tdispatch
2112 Port 0 Tdispatch.
2113 **/
2114 UINT8 SataP0TDisp;
2115
2116 /** Offset 0x0722 - Port 1 T1 Multipler
2117 Port 1 T1 Multipler.
2118 **/
2119 UINT8 SataP1T1M;
2120
2121 /** Offset 0x0723 - Port 1 T2 Multipler
2122 Port 1 T2 Multipler.
2123 **/
2124 UINT8 SataP1T2M;
2125
2126 /** Offset 0x0724 - Port 1 T3 Multipler
2127 Port 1 T3 Multipler.
2128 **/
2129 UINT8 SataP1T3M;
2130
2131 /** Offset 0x0725 - Port 1 Tdispatch
2132 Port 1 Tdispatch.
2133 **/
2134 UINT8 SataP1TDisp;
2135
2136 /** Offset 0x0726 - Port 0 Tinactive
2137 Port 0 Tinactive.
2138 **/
2139 UINT8 SataP0Tinact;
2140
2141 /** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch
2142 Port 0 Alternate Fast Init Tdispatch.
2143 $EN_DIS
2144 **/
2145 UINT8 SataP0TDispFinit;
2146
2147 /** Offset 0x0728 - Port 1 Tinactive
2148 Port 1 Tinactive.
2149 **/
2150 UINT8 SataP1Tinact;
2151
2152 /** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch
2153 Port 1 Alternate Fast Init Tdispatch.
2154 $EN_DIS
2155 **/
2156 UINT8 SataP1TDispFinit;
2157
2158 /** Offset 0x072A - Sata Thermal Throttling Suggested Setting
2159 Sata Thermal Throttling Suggested Setting.
2160 $EN_DIS
2161 **/
2162 UINT8 SataThermalSuggestedSetting;
2163
2164 /** Offset 0x072B - Enable Memory Thermal Throttling
2165 Enable Memory Thermal Throttling.
2166 $EN_DIS
2167 **/
2168 UINT8 PchMemoryThrottlingEnable;
2169
2170 /** Offset 0x072C - Memory Thermal Throttling
2171 Enable Memory Thermal Throttling.
2172 **/
2173 UINT8 PchMemoryPmsyncEnable[2];
2174
2175 /** Offset 0x072E - Enable Memory Thermal Throttling
2176 Enable Memory Thermal Throttling.
2177 **/
2178 UINT8 PchMemoryC0TransmitEnable[2];
2179
2180 /** Offset 0x0730 - Enable Memory Thermal Throttling
2181 Enable Memory Thermal Throttling.
2182 **/
2183 UINT8 PchMemoryPinSelection[2];
2184
2185 /** Offset 0x0732 - Thermal Device Temperature
2186 Decides the temperature.
2187 **/
2188 UINT16 PchTemperatureHotLevel;
2189
2190 /** Offset 0x0734 - Enable xHCI Compliance Mode
2191 Compliance Mode can be enabled for testing through this option but this is disabled
2192 by default.
2193 $EN_DIS
2194 **/
2195 UINT8 PchEnableComplianceMode;
2196
2197 /** Offset 0x0735 - USB2 Port Over Current Pin
2198 Describe the specific over current pin number of USB 2.0 Port N.
2199 **/
2200 UINT8 Usb2OverCurrentPin[16];
2201
2202 /** Offset 0x0745 - USB3 Port Over Current Pin
2203 Describe the specific over current pin number of USB 3.0 Port N.
2204 **/
2205 UINT8 Usb3OverCurrentPin[10];
2206
2207 /** Offset 0x074F - Enable 8254 Static Clock Gating
2208 Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
2209 might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
2210 boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.
2211 $EN_DIS
2212 **/
2213 UINT8 Enable8254ClockGating;
2214
2215 /** Offset 0x0750 - PCH Sata Rst Optane Memory
2216 Optane Memory
2217 $EN_DIS
2218 **/
2219 UINT8 SataRstOptaneMemory;
2220
2221 /** Offset 0x0751 - PCH Sata Rst CPU Attached Storage
2222 CPU Attached Storage
2223 $EN_DIS
2224 **/
2225 UINT8 SataRstCpuAttachedStorage;
2226
2227 /** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
2228 This is only applicable when Enable8254ClockGating is disabled. FSP will do the
2229 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
2230 avoids the SMI requirement for the programming.
2231 $EN_DIS
2232 **/
2233 UINT8 Enable8254ClockGatingOnS3;
2234
2235 /** Offset 0x0753
2236 **/
2237 UINT8 UnusedUpdSpace23;
2238
2239 /** Offset 0x0754 - Pch PCIE device override table pointer
2240 The PCIe device table is being used to override PCIe device ASPM settings. This
2241 is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
2242 refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
2243 must be 0.
2244 **/
2245 UINT32 PchPcieDeviceOverrideTablePtr;
2246
2247 /** Offset 0x0758 - Enable TCO timer.
2248 When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
2249 huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
2250 emulation must be enabled, and WDAT table must not be exposed to the OS.
2251 $EN_DIS
2252 **/
2253 UINT8 EnableTcoTimer;
2254
2255 /** Offset 0x0759 - BgpdtHash[4]
2256 BgpdtHash values
2257 **/
2258 UINT64 BgpdtHash[4];
2259
2260 /** Offset 0x0779 - BiosGuardAttr
2261 BiosGuardAttr default values
2262 **/
2263 UINT32 BiosGuardAttr;
2264
2265 /** Offset 0x077D - BiosGuardModulePtr
2266 BiosGuardModulePtr default values
2267 **/
2268 UINT64 BiosGuardModulePtr;
2269
2270 /** Offset 0x0785 - SendEcCmd
2271 SendEcCmd function pointer. \n
2272 @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
2273 EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
2274 **/
2275 UINT64 SendEcCmd;
2276
2277 /** Offset 0x078D - EcCmdProvisionEav
2278 Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
2279 **/
2280 UINT8 EcCmdProvisionEav;
2281
2282 /** Offset 0x078E - EcCmdLock
2283 EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
2284 **/
2285 UINT8 EcCmdLock;
2286
2287 /** Offset 0x078F - SgxEpoch0
2288 SgxEpoch0 default values
2289 **/
2290 UINT64 SgxEpoch0;
2291
2292 /** Offset 0x0797 - SgxEpoch1
2293 SgxEpoch1 default values
2294 **/
2295 UINT64 SgxEpoch1;
2296
2297 /** Offset 0x079F - SgxSinitNvsData
2298 SgxSinitNvsData default values
2299 **/
2300 UINT8 SgxSinitNvsData;
2301
2302 /** Offset 0x07A0 - Si Config CSM Flag.
2303 Platform specific common policies that used by several silicon components. CSM status flag.
2304 $EN_DIS
2305 **/
2306 UINT8 SiCsmFlag;
2307
2308 /** Offset 0x07A1
2309 **/
2310 UINT32 SiSsidTablePtr;
2311
2312 /** Offset 0x07A5
2313 **/
2314 UINT16 SiNumberOfSsidTableEntry;
2315
2316 /** Offset 0x07A7 - SATA RST Interrupt Mode
2317 Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
2318 0:Msix, 1:Msi, 2:Legacy
2319 **/
2320 UINT8 SataRstInterrupt;
2321
2322 /** Offset 0x07A8 - ME Unconfig on RTC clear
2323 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2324 2: Cmos is clear, status unkonwn. 3: Reserved
2325 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
2326 is clear, 3: Reserved
2327 **/
2328 UINT8 MeUnconfigOnRtcClear;
2329
2330 /** Offset 0x07A9 - Enable PS_ON.
2331 PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
2332 target that will be required by the California Energy Commission (CEC). When FALSE,
2333 PS_ON is to be disabled.
2334 $EN_DIS
2335 **/
2336 UINT8 PsOnEnable;
2337
2338 /** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable
2339 Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
2340 and VccSTG rails instead of SLP_S0# pin.
2341 $EN_DIS
2342 **/
2343 UINT8 PmcCpuC10GatePinEnable;
2344
2345 /** Offset 0x07AB - Pch Dmi Aspm Ctrl
2346 ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
2347 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
2348 **/
2349 UINT8 PchDmiAspmCtrl;
2350
2351 /** Offset 0x07AC
2352 **/
2353 UINT8 ReservedFspsUpd[1];
2354 } FSP_S_CONFIG;
2355
2356 /** Fsp S Test Configuration
2357 **/
2358 typedef struct {
2359
2360 /** Offset 0x07AD
2361 **/
2362 UINT32 Signature;
2363
2364 /** Offset 0x07B1 - Enable/Disable Device 7
2365 Enable: Device 7 enabled, Disable (Default): Device 7 disabled
2366 $EN_DIS
2367 **/
2368 UINT8 ChapDeviceEnable;
2369
2370 /** Offset 0x07B2 - Skip PAM register lock
2371 Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
2372 PAM registers will be locked by RC
2373 $EN_DIS
2374 **/
2375 UINT8 SkipPamLock;
2376
2377 /** Offset 0x07B3 - EDRAM Test Mode
2378 Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
2379 PAM registers will be locked by RC
2380 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
2381 **/
2382 UINT8 EdramTestMode;
2383
2384 /** Offset 0x07B4 - DMI Extended Sync Control
2385 Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
2386 Sync Control
2387 $EN_DIS
2388 **/
2389 UINT8 DmiExtSync;
2390
2391 /** Offset 0x07B5 - DMI IOT Control
2392 Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
2393 $EN_DIS
2394 **/
2395 UINT8 DmiIot;
2396
2397 /** Offset 0x07B6 - PEG Max Payload size per root port
2398 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
2399 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
2400 **/
2401 UINT8 PegMaxPayload[4];
2402
2403 /** Offset 0x07BA - Enable/Disable IGFX RenderStandby
2404 Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
2405 $EN_DIS
2406 **/
2407 UINT8 RenderStandby;
2408
2409 /** Offset 0x07BB - Enable/Disable IGFX PmSupport
2410 Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
2411 $EN_DIS
2412 **/
2413 UINT8 PmSupport;
2414
2415 /** Offset 0x07BC - Enable/Disable CdynmaxClamp
2416 Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
2417 $EN_DIS
2418 **/
2419 UINT8 CdynmaxClampEnable;
2420
2421 /** Offset 0x07BD - Disable VT-d
2422 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
2423 $EN_DIS
2424 **/
2425 UINT8 VtdDisable;
2426
2427 /** Offset 0x07BE - GT Frequency Limit
2428 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
2429 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
2430 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
2431 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
2432 0x18: 1200 Mhz
2433 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
2434 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
2435 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
2436 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
2437 0x18: 1200 Mhz
2438 **/
2439 UINT8 GtFreqMax;
2440
2441 /** Offset 0x07BF - Disable Turbo GT
2442 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
2443 $EN_DIS
2444 **/
2445 UINT8 DisableTurboGt;
2446
2447 /** Offset 0x07C0 - SaPostMemTestRsvd
2448 Reserved for SA Post-Mem Test
2449 $EN_DIS
2450 **/
2451 UINT8 SaPostMemTestRsvd[11];
2452
2453 /** Offset 0x07CB - 1-Core Ratio Limit
2454 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core
2455 Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
2456 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
2457 8-Core Ratio Limit. Range is 0 to 255
2458 **/
2459 UINT8 OneCoreRatioLimit;
2460
2461 /** Offset 0x07CC - 2-Core Ratio Limit
2462 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core
2463 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2464 **/
2465 UINT8 TwoCoreRatioLimit;
2466
2467 /** Offset 0x07CD - 3-Core Ratio Limit
2468 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core
2469 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2470 **/
2471 UINT8 ThreeCoreRatioLimit;
2472
2473 /** Offset 0x07CE - 4-Core Ratio Limit
2474 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core
2475 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2476 **/
2477 UINT8 FourCoreRatioLimit;
2478
2479 /** Offset 0x07CF - Enable or Disable HWP
2480 Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2481 2-3:Reserved
2482 $EN_DIS
2483 **/
2484 UINT8 Hwp;
2485
2486 /** Offset 0x07D0 - Hardware Duty Cycle Control
2487 Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
2488 $EN_DIS
2489 **/
2490 UINT8 HdcControl;
2491
2492 /** Offset 0x07D1 - Package Long duration turbo mode time
2493 Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds.
2494 Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40
2495 , 48 , 56 , 64 , 80 , 96 , 112 , 128
2496 **/
2497 UINT8 PowerLimit1Time;
2498
2499 /** Offset 0x07D2 - Short Duration Turbo Mode
2500 Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
2501 $EN_DIS
2502 **/
2503 UINT8 PowerLimit2;
2504
2505 /** Offset 0x07D3 - Turbo settings Lock
2506 Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
2507 $EN_DIS
2508 **/
2509 UINT8 TurboPowerLimitLock;
2510
2511 /** Offset 0x07D4 - Package PL3 time window
2512 Package PL3 time window range for this policy from 0 to 64ms
2513 **/
2514 UINT8 PowerLimit3Time;
2515
2516 /** Offset 0x07D5 - Package PL3 Duty Cycle
2517 Package PL3 Duty Cycle; Valid Range is 0 to 100
2518 **/
2519 UINT8 PowerLimit3DutyCycle;
2520
2521 /** Offset 0x07D6 - Package PL3 Lock
2522 Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
2523 $EN_DIS
2524 **/
2525 UINT8 PowerLimit3Lock;
2526
2527 /** Offset 0x07D7 - Package PL4 Lock
2528 Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
2529 $EN_DIS
2530 **/
2531 UINT8 PowerLimit4Lock;
2532
2533 /** Offset 0x07D8 - TCC Activation Offset
2534 TCC Activation Offset. Offset from factory set TCC activation temperature at which
2535 the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
2536 Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,
2537 For all other SKUs the recommended default are <b>0</b>
2538 **/
2539 UINT8 TccActivationOffset;
2540
2541 /** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable
2542 Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
2543 below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
2544 For all other SKUs the recommended default are <b>0: Disabled</b>.
2545 $EN_DIS
2546 **/
2547 UINT8 TccOffsetClamp;
2548
2549 /** Offset 0x07DA - Tcc Offset Lock
2550 Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
2551 target; <b>0: Disabled</b>; 1: Enabled.
2552 $EN_DIS
2553 **/
2554 UINT8 TccOffsetLock;
2555
2556 /** Offset 0x07DB - Custom Ratio State Entries
2557 The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
2558 ratio table.Sets the number of custom P-states. At least 2 states must be present
2559 **/
2560 UINT8 NumberOfEntries;
2561
2562 /** Offset 0x07DC - Custom Short term Power Limit time window
2563 Short term Power Limit time window value for custom CTDP level 1. Valid Range 0
2564 to 128, 0 = AUTO
2565 **/
2566 UINT8 Custom1PowerLimit1Time;
2567
2568 /** Offset 0x07DD - Custom Turbo Activation Ratio
2569 Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
2570 **/
2571 UINT8 Custom1TurboActivationRatio;
2572
2573 /** Offset 0x07DE - Custom Config Tdp Control
2574 Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2575 **/
2576 UINT8 Custom1ConfigTdpControl;
2577
2578 /** Offset 0x07DF - Custom Short term Power Limit time window
2579 Short term Power Limit time window value for custom CTDP level 2. Valid Range 0
2580 to 128, 0 = AUTO
2581 **/
2582 UINT8 Custom2PowerLimit1Time;
2583
2584 /** Offset 0x07E0 - Custom Turbo Activation Ratio
2585 Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
2586 **/
2587 UINT8 Custom2TurboActivationRatio;
2588
2589 /** Offset 0x07E1 - Custom Config Tdp Control
2590 Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2591 **/
2592 UINT8 Custom2ConfigTdpControl;
2593
2594 /** Offset 0x07E2 - Custom Short term Power Limit time window
2595 Short term Power Limit time window value for custom CTDP level 3. Valid Range 0
2596 to 128, 0 = AUTO
2597 **/
2598 UINT8 Custom3PowerLimit1Time;
2599
2600 /** Offset 0x07E3 - Custom Turbo Activation Ratio
2601 Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
2602 **/
2603 UINT8 Custom3TurboActivationRatio;
2604
2605 /** Offset 0x07E4 - Custom Config Tdp Control
2606 Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2607 **/
2608 UINT8 Custom3ConfigTdpControl;
2609
2610 /** Offset 0x07E5 - ConfigTdp mode settings Lock
2611 Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
2612 $EN_DIS
2613 **/
2614 UINT8 ConfigTdpLock;
2615
2616 /** Offset 0x07E6 - Load Configurable TDP SSDT
2617 Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
2618 $EN_DIS
2619 **/
2620 UINT8 ConfigTdpBios;
2621
2622 /** Offset 0x07E7 - PL1 Enable value
2623 PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
2624 $EN_DIS
2625 **/
2626 UINT8 PsysPowerLimit1;
2627
2628 /** Offset 0x07E8 - PL1 timewindow
2629 PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds)
2630 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
2631 **/
2632 UINT8 PsysPowerLimit1Time;
2633
2634 /** Offset 0x07E9 - PL2 Enable Value
2635 PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
2636 1: Enable.
2637 $EN_DIS
2638 **/
2639 UINT8 PsysPowerLimit2;
2640
2641 /** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher
2642 Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
2643 $EN_DIS
2644 **/
2645 UINT8 MlcStreamerPrefetcher;
2646
2647 /** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher
2648 Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
2649 $EN_DIS
2650 **/
2651 UINT8 MlcSpatialPrefetcher;
2652
2653 /** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions
2654 Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
2655 $EN_DIS
2656 **/
2657 UINT8 MonitorMwaitEnable;
2658
2659 /** Offset 0x07ED - Enable or Disable initialization of machine check registers
2660 Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
2661 $EN_DIS
2662 **/
2663 UINT8 MachineCheckEnable;
2664
2665 /** Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features
2666 @deprecated Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
2667 $EN_DIS
2668 **/
2669 UINT8 DebugInterfaceEnable;
2670
2671 /** Offset 0x07EF - Lock or Unlock debug interface features
2672 Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
2673 $EN_DIS
2674 **/
2675 UINT8 DebugInterfaceLockEnable;
2676
2677 /** Offset 0x07F0 - AP Idle Manner of waiting for SIPI
2678 AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
2679 1: HALT loop, 2: MWAIT loop, 3: RUN loop
2680 **/
2681 UINT8 ApIdleManner;
2682
2683 /** Offset 0x07F1 - Control on Processor Trace output scheme
2684 Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
2685 0: Single Range Output, 1: ToPA Output
2686 **/
2687 UINT8 ProcessorTraceOutputScheme;
2688
2689 /** Offset 0x07F2 - Enable or Disable Processor Trace feature
2690 Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
2691 $EN_DIS
2692 **/
2693 UINT8 ProcessorTraceEnable;
2694
2695 /** Offset 0x07F3 - Base of memory region allocated for Processor Trace
2696 Base address of memory region allocated for Processor Trace. Processor Trace requires
2697 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
2698 **/
2699 UINT64 ProcessorTraceMemBase;
2700
2701 /** Offset 0x07FB - Memory region allocation for Processor Trace
2702 Length in bytes of memory region allocated for Processor Trace. Processor Trace
2703 requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
2704 **/
2705 UINT32 ProcessorTraceMemLength;
2706
2707 /** Offset 0x07FF - Enable or Disable Voltage Optimization feature
2708 Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
2709 $EN_DIS
2710 **/
2711 UINT8 VoltageOptimization;
2712
2713 /** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology
2714 Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
2715 $EN_DIS
2716 **/
2717 UINT8 Eist;
2718
2719 /** Offset 0x0801 - Enable or Disable Energy Efficient P-state
2720 Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
2721 <b>1: Enable</b>
2722 $EN_DIS
2723 **/
2724 UINT8 EnergyEfficientPState;
2725
2726 /** Offset 0x0802 - Enable or Disable Energy Efficient Turbo
2727 Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
2728 <b>1: Enable</b>
2729 $EN_DIS
2730 **/
2731 UINT8 EnergyEfficientTurbo;
2732
2733 /** Offset 0x0803 - Enable or Disable T states
2734 Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
2735 $EN_DIS
2736 **/
2737 UINT8 TStates;
2738
2739 /** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT#
2740 Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
2741 $EN_DIS
2742 **/
2743 UINT8 BiProcHot;
2744
2745 /** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally
2746 Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
2747 $EN_DIS
2748 **/
2749 UINT8 DisableProcHotOut;
2750
2751 /** Offset 0x0806 - Enable or Disable PROCHOT# Response
2752 Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
2753 $EN_DIS
2754 **/
2755 UINT8 ProcHotResponse;
2756
2757 /** Offset 0x0807 - Enable or Disable VR Thermal Alert
2758 Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
2759 $EN_DIS
2760 **/
2761 UINT8 DisableVrThermalAlert;
2762
2763 /** Offset 0x0808 - Enable or Disable Thermal Reporting
2764 Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
2765 $EN_DIS
2766 **/
2767 UINT8 AutoThermalReporting;
2768
2769 /** Offset 0x0809 - Enable or Disable Thermal Monitor
2770 Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
2771 $EN_DIS
2772 **/
2773 UINT8 ThermalMonitor;
2774
2775 /** Offset 0x080A - Enable or Disable CPU power states (C-states)
2776 Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
2777 $EN_DIS
2778 **/
2779 UINT8 Cx;
2780
2781 /** Offset 0x080B - Configure C-State Configuration Lock
2782 Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
2783 $EN_DIS
2784 **/
2785 UINT8 PmgCstCfgCtrlLock;
2786
2787 /** Offset 0x080C - Enable or Disable Enhanced C-states
2788 Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
2789 $EN_DIS
2790 **/
2791 UINT8 C1e;
2792
2793 /** Offset 0x080D - Enable or Disable Package Cstate Demotion
2794 Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
2795 $EN_DIS
2796 **/
2797 UINT8 PkgCStateDemotion;
2798
2799 /** Offset 0x080E - Enable or Disable Package Cstate UnDemotion
2800 Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
2801 $EN_DIS
2802 **/
2803 UINT8 PkgCStateUnDemotion;
2804
2805 /** Offset 0x080F - Enable or Disable CState-Pre wake
2806 Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
2807 $EN_DIS
2808 **/
2809 UINT8 CStatePreWake;
2810
2811 /** Offset 0x0810 - Enable or Disable TimedMwait Support.
2812 Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
2813 $EN_DIS
2814 **/
2815 UINT8 TimedMwait;
2816
2817 /** Offset 0x0811 - Enable or Disable IO to MWAIT redirection
2818 Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
2819 $EN_DIS
2820 **/
2821 UINT8 CstCfgCtrIoMwaitRedirection;
2822
2823 /** Offset 0x0812 - Set the Max Pkg Cstate
2824 Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
2825 C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
2826 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
2827 **/
2828 UINT8 PkgCStateLimit;
2829
2830 /** Offset 0x0813 - TimeUnit for C-State Latency Control0
2831 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2832 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2833 **/
2834 UINT8 CstateLatencyControl0TimeUnit;
2835
2836 /** Offset 0x0814 - TimeUnit for C-State Latency Control1
2837 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2838 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2839 **/
2840 UINT8 CstateLatencyControl1TimeUnit;
2841
2842 /** Offset 0x0815 - TimeUnit for C-State Latency Control2
2843 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2844 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2845 **/
2846 UINT8 CstateLatencyControl2TimeUnit;
2847
2848 /** Offset 0x0816 - TimeUnit for C-State Latency Control3
2849 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2850 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2851 **/
2852 UINT8 CstateLatencyControl3TimeUnit;
2853
2854 /** Offset 0x0817 - TimeUnit for C-State Latency Control4
2855 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2856 **/
2857 UINT8 CstateLatencyControl4TimeUnit;
2858
2859 /** Offset 0x0818 - TimeUnit for C-State Latency Control5
2860 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2861 , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2862 **/
2863 UINT8 CstateLatencyControl5TimeUnit;
2864
2865 /** Offset 0x0819 - Interrupt Redirection Mode Select
2866 Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
2867 PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
2868 **/
2869 UINT8 PpmIrmSetting;
2870
2871 /** Offset 0x081A - Lock prochot configuration
2872 Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
2873 $EN_DIS
2874 **/
2875 UINT8 ProcHotLock;
2876
2877 /** Offset 0x081B - Configuration for boot TDP selection
2878 Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
2879 Up;0xFF : Deactivate
2880 **/
2881 UINT8 ConfigTdpLevel;
2882
2883 /** Offset 0x081C - Race To Halt
2884 Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
2885 in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
2886 through MSR 1FC bit 20)Disable; <b>1: Enable</b>
2887 $EN_DIS
2888 **/
2889 UINT8 RaceToHalt;
2890
2891 /** Offset 0x081D - Max P-State Ratio
2892 Max P-State Ratio, Valid Range 0 to 0x7F
2893 **/
2894 UINT8 MaxRatio;
2895
2896 /** Offset 0x081E - P-state ratios for custom P-state table
2897 P-state ratios for custom P-state table. NumberOfEntries has valid range between
2898 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
2899 are configurable. Valid Range of each entry is 0 to 0x7F
2900 **/
2901 UINT8 StateRatio[40];
2902
2903 /** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table
2904 P-state ratios for max 16 version of custom P-state table. This table is used for
2905 OS versions limited to a max of 16 P-States. If the first entry of this table is
2906 0, or if Number of Entries is 16 or less, then this table will be ignored, and
2907 up to the top 16 values of the StateRatio table will be used instead. Valid Range
2908 of each entry is 0 to 0x7F
2909 **/
2910 UINT8 StateRatioMax16[16];
2911
2912 /** Offset 0x0856 - Platform Power Pmax
2913 PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
2914 Range 0-1024 Watts. Value of 800 = 100W
2915 **/
2916 UINT16 PsysPmax;
2917
2918 /** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
2919 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
2920 **/
2921 UINT16 CstateLatencyControl0Irtl;
2922
2923 /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
2924 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
2925 **/
2926 UINT16 CstateLatencyControl1Irtl;
2927
2928 /** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2
2929 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
2930 **/
2931 UINT16 CstateLatencyControl2Irtl;
2932
2933 /** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3
2934 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
2935 **/
2936 UINT16 CstateLatencyControl3Irtl;
2937
2938 /** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4
2939 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
2940 **/
2941 UINT16 CstateLatencyControl4Irtl;
2942
2943 /** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5
2944 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
2945 **/
2946 UINT16 CstateLatencyControl5Irtl;
2947
2948 /** Offset 0x0864 - Package Long duration turbo mode power limit
2949 Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
2950 Valid Range 0 to 4095875 in Step size of 125
2951 **/
2952 UINT32 PowerLimit1;
2953
2954 /** Offset 0x0868 - Package Short duration turbo mode power limit
2955 Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2956 Range 0 to 4095875 in Step size of 125
2957 **/
2958 UINT32 PowerLimit2Power;
2959
2960 /** Offset 0x086C - Package PL3 power limit
2961 Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2962 Range 0 to 4095875 in Step size of 125
2963 **/
2964 UINT32 PowerLimit3;
2965
2966 /** Offset 0x0870 - Package PL4 power limit
2967 Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2968 Range 0 to 1023875 in Step size of 125
2969 **/
2970 UINT32 PowerLimit4;
2971
2972 /** Offset 0x0874 - Tcc Offset Time Window for RATL
2973 Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2974 Range 0 to 1023875 in Step size of 125
2975 **/
2976 UINT32 TccOffsetTimeWindowForRatl;
2977
2978 /** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1
2979 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2980 Range 0 to 4095875 in Step size of 125
2981 **/
2982 UINT32 Custom1PowerLimit1;
2983
2984 /** Offset 0x087C - Long term Power Limit value for custom cTDP level 1
2985 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2986 Range 0 to 4095875 in Step size of 125
2987 **/
2988 UINT32 Custom1PowerLimit2;
2989
2990 /** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2
2991 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2992 Range 0 to 4095875 in Step size of 125
2993 **/
2994 UINT32 Custom2PowerLimit1;
2995
2996 /** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2
2997 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2998 Range 0 to 4095875 in Step size of 125
2999 **/
3000 UINT32 Custom2PowerLimit2;
3001
3002 /** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3
3003 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
3004 Range 0 to 4095875 in Step size of 125
3005 **/
3006 UINT32 Custom3PowerLimit1;
3007
3008 /** Offset 0x088C - Long term Power Limit value for custom cTDP level 3
3009 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
3010 Range 0 to 4095875 in Step size of 125
3011 **/
3012 UINT32 Custom3PowerLimit2;
3013
3014 /** Offset 0x0890 - Platform PL1 power
3015 Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
3016 0 to 4095875 in Step size of 125
3017 **/
3018 UINT32 PsysPowerLimit1Power;
3019
3020 /** Offset 0x0894 - Platform PL2 power
3021 Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
3022 0 to 4095875 in Step size of 125
3023 **/
3024 UINT32 PsysPowerLimit2Power;
3025
3026 /** Offset 0x0898 - Set Three Strike Counter Disable
3027 False (default): Three Strike counter will be incremented and True: Prevents Three
3028 Strike counter from incrementing; <b>0: False</b>; 1: True.
3029 0: False, 1: True
3030 **/
3031 UINT8 ThreeStrikeCounterDisable;
3032
3033 /** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
3034 Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
3035 $EN_DIS
3036 **/
3037 UINT8 HwpInterruptControl;
3038
3039 /** Offset 0x089A - 5-Core Ratio Limit
3040 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core
3041 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3042 0x0:0xFF
3043 **/
3044 UINT8 FiveCoreRatioLimit;
3045
3046 /** Offset 0x089B - 6-Core Ratio Limit
3047 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core
3048 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3049 0x0:0xFF
3050 **/
3051 UINT8 SixCoreRatioLimit;
3052
3053 /** Offset 0x089C - 7-Core Ratio Limit
3054 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core
3055 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3056 0x0:0xFF
3057 **/
3058 UINT8 SevenCoreRatioLimit;
3059
3060 /** Offset 0x089D - 8-Core Ratio Limit
3061 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core
3062 Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3063 0x0:0xFF
3064 **/
3065 UINT8 EightCoreRatioLimit;
3066
3067 /** Offset 0x089E - Intel Turbo Boost Max Technology 3.0
3068 Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
3069 $EN_DIS
3070 **/
3071 UINT8 EnableItbm;
3072
3073 /** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver
3074 Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
3075 $EN_DIS
3076 **/
3077 UINT8 EnableItbmDriver;
3078
3079 /** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion
3080 Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
3081 $EN_DIS
3082 **/
3083 UINT8 C1StateAutoDemotion;
3084
3085 /** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion
3086 Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
3087 $EN_DIS
3088 **/
3089 UINT8 C1StateUnDemotion;
3090
3091 /** Offset 0x08A2 - CpuWakeUpTimer
3092 Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
3093 to 180 seconds. 0: Disable; <b>1: Enable</b>
3094 $EN_DIS
3095 **/
3096 UINT8 CpuWakeUpTimer;
3097
3098 /** Offset 0x08A3 - Minimum Ring ratio limit override
3099 Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
3100 ratio limit
3101 **/
3102 UINT8 MinRingRatioLimit;
3103
3104 /** Offset 0x08A4 - Minimum Ring ratio limit override
3105 Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
3106 ratio limit
3107 **/
3108 UINT8 MaxRingRatioLimit;
3109
3110 /** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
3111 Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
3112 $EN_DIS
3113 **/
3114 UINT8 C3StateAutoDemotion;
3115
3116 /** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
3117 Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
3118 $EN_DIS
3119 **/
3120 UINT8 C3StateUnDemotion;
3121
3122 /** Offset 0x08A7 - ReservedCpuPostMemTest
3123 Reserved for CPU Post-Mem Test
3124 $EN_DIS
3125 **/
3126 UINT8 ReservedCpuPostMemTest[19];
3127
3128 /** Offset 0x08BA - SgxSinitDataFromTpm
3129 SgxSinitDataFromTpm default values
3130 **/
3131 UINT8 SgxSinitDataFromTpm;
3132
3133 /** Offset 0x08BB - End of Post message
3134 Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
3135 EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
3136 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
3137 **/
3138 UINT8 EndOfPostMessage;
3139
3140 /** Offset 0x08BC - D0I3 Setting for HECI Disable
3141 Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
3142 HECI devices
3143 $EN_DIS
3144 **/
3145 UINT8 DisableD0I3SettingForHeci;
3146
3147 /** Offset 0x08BD - HD Audio Reset Wait Timer
3148 The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
3149 **/
3150 UINT16 PchHdaResetWaitTimer;
3151
3152 /** Offset 0x08BF - Enable LOCKDOWN SMI
3153 Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
3154 $EN_DIS
3155 **/
3156 UINT8 PchLockDownGlobalSmi;
3157
3158 /** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface
3159 Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
3160 $EN_DIS
3161 **/
3162 UINT8 PchLockDownBiosInterface;
3163
3164 /** Offset 0x08C1 - Unlock all GPIO pads
3165 Force all GPIO pads to be unlocked for debug purpose.
3166 $EN_DIS
3167 **/
3168 UINT8 PchUnlockGpioPads;
3169
3170 /** Offset 0x08C2 - PCH Unlock SBI access
3171 Deprecated
3172 $EN_DIS
3173 **/
3174 UINT8 PchSbiUnlock;
3175
3176 /** Offset 0x08C3 - PCH Unlock SideBand access
3177 The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3178 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
3179 $EN_DIS
3180 **/
3181 UINT8 PchSbAccessUnlock;
3182
3183 /** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency
3184 Latency Tolerance Reporting, Max Snoop Latency.
3185 **/
3186 UINT16 PcieRpLtrMaxSnoopLatency[24];
3187
3188 /** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency
3189 Latency Tolerance Reporting, Max Non-Snoop Latency.
3190 **/
3191 UINT16 PcieRpLtrMaxNoSnoopLatency[24];
3192
3193 /** Offset 0x0924 - PCIE RP Snoop Latency Override Mode
3194 Latency Tolerance Reporting, Snoop Latency Override Mode.
3195 **/
3196 UINT8 PcieRpSnoopLatencyOverrideMode[24];
3197
3198 /** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier
3199 Latency Tolerance Reporting, Snoop Latency Override Multiplier.
3200 **/
3201 UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
3202
3203 /** Offset 0x0954 - PCIE RP Snoop Latency Override Value
3204 Latency Tolerance Reporting, Snoop Latency Override Value.
3205 **/
3206 UINT16 PcieRpSnoopLatencyOverrideValue[24];
3207
3208 /** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode
3209 Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
3210 **/
3211 UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
3212
3213 /** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier
3214 Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
3215 **/
3216 UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
3217
3218 /** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value
3219 Latency Tolerance Reporting, Non-Snoop Latency Override Value.
3220 **/
3221 UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
3222
3223 /** Offset 0x09E4 - PCIE RP Slot Power Limit Scale
3224 Specifies scale used for slot power limit value. Leave as 0 to set to default.
3225 **/
3226 UINT8 PcieRpSlotPowerLimitScale[24];
3227
3228 /** Offset 0x09FC - PCIE RP Slot Power Limit Value
3229 Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
3230 **/
3231 UINT16 PcieRpSlotPowerLimitValue[24];
3232
3233 /** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset
3234 Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
3235 **/
3236 UINT8 PcieRpUptp[24];
3237
3238 /** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset
3239 Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
3240 **/
3241 UINT8 PcieRpDptp[24];
3242
3243 /** Offset 0x0A5C - PCIE RP Enable Port8xh Decode
3244 This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
3245 1: Enable.
3246 $EN_DIS
3247 **/
3248 UINT8 PcieEnablePort8xhDecode;
3249
3250 /** Offset 0x0A5D - PCIE Port8xh Decode Port Index
3251 The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
3252 **/
3253 UINT8 PchPciePort8xhDecodePortIndex;
3254
3255 /** Offset 0x0A5E - PCH Energy Reporting
3256 Disable/Enable PCH to CPU energy report feature.
3257 $EN_DIS
3258 **/
3259 UINT8 PchPmDisableEnergyReport;
3260
3261 /** Offset 0x0A5F - PCH Sata Test Mode
3262 Allow entrance to the PCH SATA test modes.
3263 $EN_DIS
3264 **/
3265 UINT8 SataTestMode;
3266
3267 /** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable
3268 If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
3269 that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
3270 $EN_DIS
3271 **/
3272 UINT8 PchXhciOcLock;
3273
3274 /** Offset 0x0A61
3275 **/
3276 UINT8 UnusedUpdSpace24[17];
3277
3278 /** Offset 0x0A72 - Skip POSTBOOT SAI
3279 Deprecated
3280 $EN_DIS
3281 **/
3282 UINT8 SkipPostBootSai;
3283
3284 /** Offset 0x0A73 - Mctp Broadcast Cycle
3285 Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
3286 $EN_DIS
3287 **/
3288 UINT8 MctpBroadcastCycle;
3289
3290 /** Offset 0x0A74
3291 **/
3292 UINT8 ReservedFspsTestUpd[12];
3293 } FSP_S_TEST_CONFIG;
3294
3295 /** Fsp S UPD Configuration
3296 **/
3297 typedef struct {
3298
3299 /** Offset 0x0000
3300 **/
3301 FSP_UPD_HEADER FspUpdHeader;
3302
3303 /** Offset 0x0020
3304 **/
3305 FSP_S_CONFIG FspsConfig;
3306
3307 /** Offset 0x07AD
3308 **/
3309 FSP_S_TEST_CONFIG FspsTestConfig;
3310
3311 /** Offset 0x0A80
3312 **/
3313 UINT16 UpdTerminator;
3314 } FSPS_UPD;
3315
3316 #pragma pack()
3317
3318 #endif
FSP_S_TEST_CONFIG::PsysPowerLimit2Power
UINT32 PsysPowerLimit2Power
Offset 0x0894 - Platform PL2 power Platform PL2 power.
Definition: FspsUpd.h:3024
FSP_S_TEST_CONFIG::ThreeCoreRatioLimit
UINT8 ThreeCoreRatioLimit
Offset 0x07CD - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2471
FSP_S_CONFIG::PchHdaAudioLinkDmic1
UINT8 PchHdaAudioLinkDmic1
Offset 0x00FF - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link.
Definition: FspsUpd.h:347
FSP_S_CONFIG::TcoIrqEnable
UINT8 TcoIrqEnable
Offset 0x008B - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
Definition: FspsUpd.h:248
FSP_S_CONFIG::PchHdaIDispLinkFrequency
UINT8 PchHdaIDispLinkFrequency
Offset 0x036A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz...
Definition: FspsUpd.h:1216
FSP_S_TEST_CONFIG::CstateLatencyControl1Irtl
UINT16 CstateLatencyControl1Irtl
Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit...
Definition: FspsUpd.h:2926
FSP_S_CONFIG::PchPmVrAlert
UINT8 PchPmVrAlert
Offset 0x0151 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0'...
Definition: FspsUpd.h:547
FSP_S_CONFIG::PchTTLock
UINT8 PchTTLock
Offset 0x0715 - Thermal Throttle Lock Thermal Throttle Lock.
Definition: FspsUpd.h:2046
FSP_S_TEST_CONFIG::Custom3PowerLimit2
UINT32 Custom3PowerLimit2
Offset 0x088C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for c...
Definition: FspsUpd.h:3012
FSP_S_CONFIG::WatchDogTimerBios
UINT16 WatchDogTimerBios
Offset 0x015D - BIOS Timer 16 bits Value, Set BIOS watchdog timer.
Definition: FspsUpd.h:614
FSP_S_CONFIG::SlowSlewRateForIa
UINT8 SlowSlewRateForIa
Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configur...
Definition: FspsUpd.h:939
FSP_S_CONFIG::UnusedUpdSpace19
UINT8 UnusedUpdSpace19
Offset 0x0685.
Definition: FspsUpd.h:1725
FSP_S_CONFIG::CridEnable
UINT8 CridEnable
Offset 0x0200 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS...
Definition: FspsUpd.h:693
FSP_S_CONFIG::BltBufferAddress
UINT32 BltBufferAddress
Offset 0x0234 - Blt Buffer Address Address of Blt buffer.
Definition: FspsUpd.h:833
FSP_S_CONFIG::PchCnviMfUart1Type
UINT8 PchCnviMfUart1Type
Offset 0x014B - CNVi MfUart1 Type This option configures Uart type which connects to MfUart1 0:ISH Ua...
Definition: FspsUpd.h:511
FSP_S_CONFIG::MeUnconfigOnRtcClear
UINT8 MeUnconfigOnRtcClear
Offset 0x07A8 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear.
Definition: FspsUpd.h:2328
FSP_S_TEST_CONFIG::ProcessorTraceEnable
UINT8 ProcessorTraceEnable
Offset 0x07F2 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; ...
Definition: FspsUpd.h:2693
FSP_S_CONFIG::PchT2Level
UINT16 PchT2Level
Offset 0x0711 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
Definition: FspsUpd.h:2027
FSP_S_CONFIG::PchPmWoWlanDeepSxEnable
UINT8 PchPmWoWlanDeepSxEnable
Offset 0x0673 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the D...
Definition: FspsUpd.h:1627
FSP_S_CONFIG::PchUsb2PhySusPgEnable
UINT8 PchUsb2PhySusPgEnable
Offset 0x0148 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating...
Definition: FspsUpd.h:494
FSP_S_CONFIG::SataSalpSupport
UINT8 SataSalpSupport
Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management...
Definition: FspsUpd.h:167
FSP_S_CONFIG::PchLockDownRtcMemoryLock
UINT8 PchLockDownRtcMemoryLock
Offset 0x0395 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-...
Definition: FspsUpd.h:1380
FSP_S_CONFIG::PchPmWolEnableOverride
UINT8 PchPmWolEnableOverride
Offset 0x0670 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General ...
Definition: FspsUpd.h:1608
FSP_S_CONFIG::UsbPdoProgramming
UINT8 UsbPdoProgramming
Offset 0x0114 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase...
Definition: FspsUpd.h:420
FSP_S_CONFIG::SataP0TDispFinit
UINT8 SataP0TDispFinit
Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch.
Definition: FspsUpd.h:2145
FSP_S_TEST_CONFIG::PsysPowerLimit2
UINT8 PsysPowerLimit2
Offset 0x07E9 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power...
Definition: FspsUpd.h:2639
FSP_S_CONFIG::TTCrossThrottling
UINT8 TTCrossThrottling
Offset 0x0717 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
Definition: FspsUpd.h:2058
FSP_S_CONFIG::SataRstCpuAttachedStorage
UINT8 SataRstCpuAttachedStorage
Offset 0x0751 - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS.
Definition: FspsUpd.h:2225
FSP_S_TEST_CONFIG::NumberOfEntries
UINT8 NumberOfEntries
Offset 0x07DB - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states.
Definition: FspsUpd.h:2560
FSP_S_TEST_CONFIG::EnergyEfficientTurbo
UINT8 EnergyEfficientTurbo
Offset 0x0802 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo...
Definition: FspsUpd.h:2731
FSP_S_TEST_CONFIG::EdramTestMode
UINT8 EdramTestMode
Offset 0x07B3 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should l...
Definition: FspsUpd.h:2382
FSP_S_TEST_CONFIG::CstateLatencyControl2Irtl
UINT16 CstateLatencyControl2Irtl
Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit...
Definition: FspsUpd.h:2931
FSP_S_TEST_CONFIG::PchLockDownBiosInterface
UINT8 PchLockDownBiosInterface
Offset 0x08C0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes ...
Definition: FspsUpd.h:3162
FSP_S_CONFIG::PchPmSlpStrchSusUp
UINT8 PchPmSlpStrchSusUp
Offset 0x0681 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up...
Definition: FspsUpd.h:1704
FSP_S_CONFIG::FivrRfiFrequency
UINT16 FivrRfiFrequency
Offset 0x030F - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
Definition: FspsUpd.h:1062
FSP_S_CONFIG::RemoteAssistance
UINT8 RemoteAssistance
Offset 0x015F - Remote Assistance Trigger Availablilty Enable/Disable.
Definition: FspsUpd.h:620
FSP_S_TEST_CONFIG::C1e
UINT8 C1e
Offset 0x080C - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states.
Definition: FspsUpd.h:2791
FSP_S_TEST_CONFIG::PpmIrmSetting
UINT8 PpmIrmSetting
Offset 0x0819 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
Definition: FspsUpd.h:2869
FSP_S_CONFIG::PchDmiAspmCtrl
UINT8 PchDmiAspmCtrl
Offset 0x07AB - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link...
Definition: FspsUpd.h:2349
FSP_S_CONFIG::PchEspiLgmrEnable
UINT8 PchEspiLgmrEnable
Offset 0x014C - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS...
Definition: FspsUpd.h:517
FSP_S_TEST_CONFIG::MinRingRatioLimit
UINT8 MinRingRatioLimit
Offset 0x08A3 - Minimum Ring ratio limit override Minimum Ring ratio limit override.
Definition: FspsUpd.h:3102
FSP_S_CONFIG::PchIshGp7GpioAssign
UINT8 PchIshGp7GpioAssign
Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1344
AZALIA_HEADER
Azalia Header structure.
Definition: FspsUpd.h:44
FSP_S_CONFIG::DdiPortCDdc
UINT8 DdiPortCDdc
Offset 0x022E - Enable or disable DDC of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:802
FSP_S_CONFIG::SdCardPowerEnableActiveHigh
UINT8 SdCardPowerEnableActiveHigh
Offset 0x0147 - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high.
Definition: FspsUpd.h:487
FSP_S_CONFIG::IslVrCmd
UINT8 IslVrCmd
Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.
Definition: FspsUpd.h:1099
FSP_S_CONFIG::BiosGuardModulePtr
UINT64 BiosGuardModulePtr
Offset 0x077D - BiosGuardModulePtr BiosGuardModulePtr default values.
Definition: FspsUpd.h:2268
FSP_S_TEST_CONFIG::PowerLimit4
UINT32 PowerLimit4
Offset 0x0870 - Package PL4 power limit Package PL4 power limit.
Definition: FspsUpd.h:2970
FSP_S_CONFIG::SerialIoEnableDebugUartAfterPost
UINT8 SerialIoEnableDebugUartAfterPost
Offset 0x0707 - Enable Debug UART Controller Enable debug UART controller after post.
Definition: FspsUpd.h:1982
FSP_S_TEST_CONFIG::ProcessorTraceMemLength
UINT32 ProcessorTraceMemLength
Offset 0x07FB - Memory region allocation for Processor Trace Length in bytes of memory region allocat...
Definition: FspsUpd.h:2705
FSP_S_CONFIG::FastPkgCRampDisableSa
UINT8 FastPkgCRampDisableSa
Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew R...
Definition: FspsUpd.h:1014
FSP_S_TEST_CONFIG::SixCoreRatioLimit
UINT8 SixCoreRatioLimit
Offset 0x089B - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3051
AZALIA_HEADER::RevisionId
UINT8 RevisionId
Revision ID of the codec. 0xFF matches any revision.
Definition: FspsUpd.h:47
FSP_S_TEST_CONFIG::PsysPowerLimit1Time
UINT8 PsysPowerLimit1Time
Offset 0x07E8 - PL1 timewindow PL1 timewindow in seconds.
Definition: FspsUpd.h:2632
FSP_S_CONFIG::PchLanEnable
UINT8 PchLanEnable
Offset 0x00FC - Enable LAN Enable/disable LAN controller.
Definition: FspsUpd.h:329
FSP_S_TEST_CONFIG::Custom1PowerLimit2
UINT32 Custom1PowerLimit2
Offset 0x087C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for c...
Definition: FspsUpd.h:2988
FSP_S_CONFIG::PmcCpuC10GatePinEnable
UINT8 PmcCpuC10GatePinEnable
Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to ...
Definition: FspsUpd.h:2343
FSP_S_CONFIG::PchIshGp0GpioAssign
UINT8 PchIshGp0GpioAssign
Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1302
FSP_S_TEST_CONFIG::CstateLatencyControl3TimeUnit
UINT8 CstateLatencyControl3TimeUnit
Offset 0x0816 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid val...
Definition: FspsUpd.h:2852
FSP_S_TEST_CONFIG::BiProcHot
UINT8 BiProcHot
Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; ...
Definition: FspsUpd.h:2743
AUDIO_AZALIA_VERB_TABLE::Header
AZALIA_HEADER Header
AZALIA PCH header.
Definition: FspsUpd.h:57
FSP_S_CONFIG::PchMemoryThrottlingEnable
UINT8 PchMemoryThrottlingEnable
Offset 0x072B - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
Definition: FspsUpd.h:2168
FSP_S_CONFIG::PchLockDownBiosLock
UINT8 PchLockDownBiosLock
Offset 0x0393 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDC...
Definition: FspsUpd.h:1367
FSP_S_CONFIG::PchCrid
UINT8 PchCrid
Offset 0x0394 - PCH Compatibility Revision ID This member describes whether or not the CRID feature o...
Definition: FspsUpd.h:1373
FSP_S_CONFIG::SataLedEnable
UINT8 SataLedEnable
Offset 0x0150 - SATA LED SATA LED indicating SATA controller activity.
Definition: FspsUpd.h:540
FSP_S_CONFIG::PchHdaVerbTablePtr
UINT32 PchHdaVerbTablePtr
Offset 0x008D - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
Definition: FspsUpd.h:258
FSP_S_TEST_CONFIG::OneCoreRatioLimit
UINT8 OneCoreRatioLimit
Offset 0x07CB - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2459
FSP_S_CONFIG::SlpS0Override
UINT8 SlpS0Override
Offset 0x067A - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type...
Definition: FspsUpd.h:1669
FSP_S_TEST_CONFIG::PkgCStateUnDemotion
UINT8 PkgCStateUnDemotion
Offset 0x080E - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemoti...
Definition: FspsUpd.h:2803
FSP_S_TEST_CONFIG::PchHdaResetWaitTimer
UINT16 PchHdaResetWaitTimer
Offset 0x08BD - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of ...
Definition: FspsUpd.h:3150
FSP_S_TEST_CONFIG::EnergyEfficientPState
UINT8 EnergyEfficientPState
Offset 0x0801 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state...
Definition: FspsUpd.h:2724
FSP_S_CONFIG::ReservedForFuture1
UINT8 ReservedForFuture1
Offset 0x070B - Reserved Reserved $EN_DIS.
Definition: FspsUpd.h:2006
FSP_S_CONFIG::PcieRpDpcMask
UINT32 PcieRpDpcMask
Offset 0x010C - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports...
Definition: FspsUpd.h:407
FSP_S_CONFIG::SataRstInterrupt
UINT8 SataRstInterrupt
Offset 0x07A7 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SAT...
Definition: FspsUpd.h:2320
FSP_S_CONFIG::PchPmPwrCycDur
UINT8 PchPmPwrCycDur
Offset 0x068A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second...
Definition: FspsUpd.h:1755
FSP_S_CONFIG::SendEcCmd
UINT64 SendEcCmd
Offset 0x0785 - SendEcCmd SendEcCmd function pointer.
Definition: FspsUpd.h:2275
FSP_S_CONFIG::ForcMebxSyncUp
UINT8 ForcMebxSyncUp
Offset 0x0161 - MEBX execution Enable/Disable.
Definition: FspsUpd.h:632
FSP_S_CONFIG::PmcPowerButtonDebounce
UINT32 PmcPowerButtonDebounce
Offset 0x0115 - Power button debounce configuration Debounce time for PWRBTN in microseconds.
Definition: FspsUpd.h:426
FSP_S_TEST_CONFIG::CdynmaxClampEnable
UINT8 CdynmaxClampEnable
Offset 0x07BC - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable Cd...
Definition: FspsUpd.h:2419
FSP_S_TEST_CONFIG::Custom1ConfigTdpControl
UINT8 Custom1ConfigTdpControl
Offset 0x07DE - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2576
FSP_S_CONFIG::PchScsEmmcHs400RxStrobeDll1
UINT8 PchScsEmmcHs400RxStrobeDll1
Offset 0x06F7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)...
Definition: FspsUpd.h:1931
FSP_S_TEST_CONFIG::CstateLatencyControl4Irtl
UINT16 CstateLatencyControl4Irtl
Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit...
Definition: FspsUpd.h:2941
FSP_S_CONFIG::PchPmSlpS3MinAssert
UINT8 PchPmSlpS3MinAssert
Offset 0x0676 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy.
Definition: FspsUpd.h:1644
FSP_S_TEST_CONFIG::C1StateAutoDemotion
UINT8 C1StateAutoDemotion
Offset 0x08A0 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion.
Definition: FspsUpd.h:3083
FSP_S_TEST_CONFIG::GtFreqMax
UINT8 GtFreqMax
Offset 0x07BE - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz...
Definition: FspsUpd.h:2439
FSP_S_CONFIG::PchPmSlpS4MinAssert
UINT8 PchPmSlpS4MinAssert
Offset 0x0677 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy.
Definition: FspsUpd.h:1649
FSP_S_CONFIG::PmcModPhySusPgEnable
UINT8 PmcModPhySusPgEnable
Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic...
Definition: FspsUpd.h:677
FSP_S_TEST_CONFIG::SkipPostBootSai
UINT8 SkipPostBootSai
Offset 0x0A72 - Skip POSTBOOT SAI Deprecated $EN_DIS.
Definition: FspsUpd.h:3282
FSP_S_TEST_CONFIG::EnableItbm
UINT8 EnableItbm
Offset 0x089E - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3...
Definition: FspsUpd.h:3071
FSP_S_CONFIG::PchPmSlpS0Vm075VSupport
UINT8 PchPmSlpS0Vm075VSupport
Offset 0x0154 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy.
Definition: FspsUpd.h:565
FSP_S_CONFIG::PchHdaSndwBufferRcomp
UINT8 PchHdaSndwBufferRcomp
Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance...
Definition: FspsUpd.h:395
FSP_S_CONFIG::CpuBistData
UINT32 CpuBistData
Offset 0x0315 - CpuBistData Pointer CPU BIST Data.
Definition: FspsUpd.h:1093
FSP_S_TEST_CONFIG::CstateLatencyControl3Irtl
UINT16 CstateLatencyControl3Irtl
Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit...
Definition: FspsUpd.h:2936
FSP_S_CONFIG::GraphicsConfigPtr
UINT32 GraphicsConfigPtr
Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
Definition: FspsUpd.h:101
FSP_S_TEST_CONFIG::PkgCStateLimit
UINT8 PkgCStateLimit
Offset 0x0812 - Set the Max Pkg Cstate Set the Max Pkg Cstate.
Definition: FspsUpd.h:2828
FSP_S_CONFIG::PchTTEnable
UINT8 PchTTEnable
Offset 0x0713 - Enable The Thermal Throttle Enable the thermal throttle function. ...
Definition: FspsUpd.h:2033
FSP_S_CONFIG::PchScsEmmcHs400TuningRequired
UINT8 PchScsEmmcHs400TuningRequired
Offset 0x06F5 - Enable eMMC HS400 Training Deprecated.
Definition: FspsUpd.h:1920
FSP_S_CONFIG::UnusedUpdSpace16
UINT8 UnusedUpdSpace16
Offset 0x0664.
Definition: FspsUpd.h:1551
FSP_S_CONFIG::ManageabilityMode
UINT8 ManageabilityMode
Offset 0x0158 - Manageability Mode set by Mebx Enable/Disable.
Definition: FspsUpd.h:589
FSP_S_CONFIG::SendVrMbxCmd
UINT8 SendVrMbxCmd
Offset 0x0303 - Enable VR specific mailbox command VR specific mailbox commands.
Definition: FspsUpd.h:1022
FSP_S_CONFIG::CdClock
UINT8 CdClock
Offset 0x0217 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz 0: ...
Definition: FspsUpd.h:733
FSP_S_CONFIG::XdciEnable
UINT8 XdciEnable
Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller.
Definition: FspsUpd.h:197
FSP_S_TEST_CONFIG::Custom2PowerLimit1Time
UINT8 Custom2PowerLimit1Time
Offset 0x07DF - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2582
FSP_S_TEST_CONFIG::DisableD0I3SettingForHeci
UINT8 DisableD0I3SettingForHeci
Offset 0x08BC - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disabl...
Definition: FspsUpd.h:3145
FSP_S_CONFIG::SataP1T3M
UINT8 SataP1T3M
Offset 0x0724 - Port 1 T3 Multipler Port 1 T3 Multipler.
Definition: FspsUpd.h:2129
FSP_S_TEST_CONFIG::C1StateUnDemotion
UINT8 C1StateUnDemotion
Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion...
Definition: FspsUpd.h:3089
FSP_S_TEST_CONFIG::DmiIot
UINT8 DmiIot
Offset 0x07B5 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Con...
Definition: FspsUpd.h:2395
FSP_S_CONFIG::PsOnEnable
UINT8 PsOnEnable
Offset 0x07A9 - Enable PS_ON.
Definition: FspsUpd.h:2336
FSP_S_TEST_CONFIG::Signature
UINT32 Signature
Offset 0x07AD.
Definition: FspsUpd.h:2362
FSP_S_TEST_CONFIG::TimedMwait
UINT8 TimedMwait
Offset 0x0810 - Enable or Disable TimedMwait Support.
Definition: FspsUpd.h:2815
FSP_S_CONFIG::RampDown
UINT8 RampDown
Offset 0x032A - Ramp Down Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range...
Definition: FspsUpd.h:1133
FSP_S_CONFIG::UnusedUpdSpace7
UINT8 UnusedUpdSpace7
Offset 0x0219.
Definition: FspsUpd.h:743
FSP_S_TEST_CONFIG::ConfigTdpBios
UINT8 ConfigTdpBios
Offset 0x07E6 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disabl...
Definition: FspsUpd.h:2620
FSP_S_CONFIG::PchDmiTsawEn
UINT8 PchDmiTsawEn
Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable...
Definition: FspsUpd.h:2064
FSP_S_TEST_CONFIG::Custom1PowerLimit1
UINT32 Custom1PowerLimit1
Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for...
Definition: FspsUpd.h:2982
FSP_S_CONFIG::AsfEnabled
UINT8 AsfEnabled
Offset 0x0157 - ASF Switch Enable/Disable.
Definition: FspsUpd.h:583
FSP_S_TEST_CONFIG::DmiExtSync
UINT8 DmiExtSync
Offset 0x07B4 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS.
Definition: FspsUpd.h:2389
FSP_S_CONFIG::PchPmPciePllSsc
UINT8 PchPmPciePllSsc
Offset 0x068B - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage.
Definition: FspsUpd.h:1761
FSP_S_TEST_CONFIG::PchLockDownGlobalSmi
UINT8 PchLockDownGlobalSmi
Offset 0x08BF - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bi...
Definition: FspsUpd.h:3156
FSP_S_TEST_CONFIG::FourCoreRatioLimit
UINT8 FourCoreRatioLimit
Offset 0x07CE - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2477
FSP_S_CONFIG::PeiGraphicsPeimInit
UINT8 PeiGraphicsPeimInit
Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
Definition: FspsUpd.h:739
FSP_S_CONFIG::MicrocodeRegionBase
UINT32 MicrocodeRegionBase
Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
Definition: FspsUpd.h:150
FSP_S_TEST_CONFIG::PchPmDisableEnergyReport
UINT8 PchPmDisableEnergyReport
Offset 0x0A5E - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature.
Definition: FspsUpd.h:3259
FSP_S_CONFIG::TcoIrqSelect
UINT8 TcoIrqSelect
Offset 0x008A - Select TcoIrqSelect TCO IRQ Select.
Definition: FspsUpd.h:242
FSP_S_TEST_CONFIG::Custom1PowerLimit1Time
UINT8 Custom1PowerLimit1Time
Offset 0x07DC - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2566
FSP_S_CONFIG::SlpS0DisQForDebug
UINT8 SlpS0DisQForDebug
Offset 0x067B - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe t...
Definition: FspsUpd.h:1680
FSP_S_TEST_CONFIG::VoltageOptimization
UINT8 VoltageOptimization
Offset 0x07FF - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization...
Definition: FspsUpd.h:2711
FSP_S_CONFIG::PchPmWoWlanEnable
UINT8 PchPmWoWlanEnable
Offset 0x0672 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP...
Definition: FspsUpd.h:1620
FSP_S_CONFIG::PcieRpDpcExtensionsMask
UINT32 PcieRpDpcExtensionsMask
Offset 0x0110 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports...
Definition: FspsUpd.h:413
FSP_S_TEST_CONFIG::PchXhciOcLock
UINT8 PchXhciOcLock
Offset 0x0A60 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS wi...
Definition: FspsUpd.h:3272
FSP_S_CONFIG::PchPmDisableDsxAcPresentPulldown
UINT8 PchPmDisableDsxAcPresentPulldown
Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_P...
Definition: FspsUpd.h:1721
FSP_S_CONFIG::McivrRfiFrequencyPrefix
UINT8 McivrRfiFrequencyPrefix
Offset 0x030D - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix...
Definition: FspsUpd.h:1049
FSP_S_CONFIG::PchPmWolOvrWkSts
UINT8 PchPmWolOvrWkSts
Offset 0x0689 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRS...
Definition: FspsUpd.h:1749
FSP_S_TEST_CONFIG::DebugInterfaceLockEnable
UINT8 DebugInterfaceLockEnable
Offset 0x07EF - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: D...
Definition: FspsUpd.h:2675
FSP_S_CONFIG::PchHdaAudioLinkSndw2
UINT8 PchHdaAudioLinkSndw2
Offset 0x0104 - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link.
Definition: FspsUpd.h:377
FSP_S_CONFIG::SataPwrOptEnable
UINT8 SataPwrOptEnable
Offset 0x068D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side.
Definition: FspsUpd.h:1771
FSP_S_CONFIG::SlowSlewRateForFivr
UINT8 SlowSlewRateForFivr
Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate config...
Definition: FspsUpd.h:1088
FSP_S_CONFIG::PchHdaAudioLinkSndw1
UINT8 PchHdaAudioLinkSndw1
Offset 0x0103 - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link.
Definition: FspsUpd.h:371
FSP_S_CONFIG::PchSirqMode
UINT8 PchSirqMode
Offset 0x0709 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode...
Definition: FspsUpd.h:1994
FSP_S_CONFIG::PcieRpImrEnabled
UINT8 PcieRpImrEnabled
Offset 0x066D - PCIE IMR Enables Isolated Memory Region for PCIe.
Definition: FspsUpd.h:1593
FSP_S_CONFIG::SkipMpInit
UINT8 SkipMpInit
Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization.
Definition: FspsUpd.h:1043
FSP_S_CONFIG::PchIshUart0GpioAssign
UINT8 PchIshUart0GpioAssign
Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1272
FSP_S_TEST_CONFIG::Custom1TurboActivationRatio
UINT8 Custom1TurboActivationRatio
Offset 0x07DD - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1...
Definition: FspsUpd.h:2571
FSP_S_CONFIG::UnusedUpdSpace23
UINT8 UnusedUpdSpace23
Offset 0x0753.
Definition: FspsUpd.h:2237
FSP_S_CONFIG::UnusedUpdSpace20
UINT8 UnusedUpdSpace20
Offset 0x068C.
Definition: FspsUpd.h:1765
AZALIA_HEADER::SdiNum
UINT8 SdiNum
SDI number, 0xFF matches any SDI.
Definition: FspsUpd.h:48
FSP_S_TEST_CONFIG::PowerLimit2
UINT8 PowerLimit2
Offset 0x07D2 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode.
Definition: FspsUpd.h:2503
FSP_S_CONFIG::SiNumberOfSsidTableEntry
UINT16 SiNumberOfSsidTableEntry
Offset 0x07A5.
Definition: FspsUpd.h:2314
FSP_S_CONFIG::SataRstHddUnlock
UINT8 SataRstHddUnlock
Offset 0x06E8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled...
Definition: FspsUpd.h:1880
FSP_S_CONFIG::SataMode
UINT8 SataMode
Offset 0x0093 - SATA Mode Select SATA controller working mode.
Definition: FspsUpd.h:275
FSP_S_CONFIG::PchHdaAudioLinkSsp0
UINT8 PchHdaAudioLinkSsp0
Offset 0x0100 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link.
Definition: FspsUpd.h:353
FSP_S_CONFIG::SataRstRaid5
UINT8 SataRstRaid5
Offset 0x06E4 - PCH Sata Rst Raid5 RAID5.
Definition: FspsUpd.h:1857
FSP_S_TEST_CONFIG::RaceToHalt
UINT8 RaceToHalt
Offset 0x081C - Race To Halt Enable/Disable Race To Halt feature.
Definition: FspsUpd.h:2889
FSP_S_CONFIG::SkipS3CdClockInit
UINT8 SkipS3CdClockInit
Offset 0x0231 - Enable/Disable SkipS3CdClockInit Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent $EN_DIS.
Definition: FspsUpd.h:821
FSP_S_CONFIG::PchHdaAudioLinkSndw3
UINT8 PchHdaAudioLinkSndw3
Offset 0x0105 - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link.
Definition: FspsUpd.h:383
FSP_S_TEST_CONFIG::TStates
UINT8 TStates
Offset 0x0803 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable...
Definition: FspsUpd.h:2737
FSP_S_TEST_CONFIG::ProcessorTraceOutputScheme
UINT8 ProcessorTraceOutputScheme
Offset 0x07F1 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0:...
Definition: FspsUpd.h:2687
FspUpd.h
Copyright (c) 2018, Intel Corporation.
FSP_S_TEST_CONFIG::CstateLatencyControl2TimeUnit
UINT8 CstateLatencyControl2TimeUnit
Offset 0x0815 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid val...
Definition: FspsUpd.h:2846
FSP_S_CONFIG::BltBufferSize
UINT32 BltBufferSize
Offset 0x0238 - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (t...
Definition: FspsUpd.h:839
FSP_S_CONFIG::PchHotEnable
UINT8 PchHotEnable
Offset 0x014F - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel...
Definition: FspsUpd.h:534
AZALIA_HEADER::DataDwords
UINT16 DataDwords
Number of data DWORDs pointed by the codec data buffer.
Definition: FspsUpd.h:49
FSP_S_CONFIG::UnusedUpdSpace17
UINT8 UnusedUpdSpace17
Offset 0x066F.
Definition: FspsUpd.h:1602
FSP_S_CONFIG::CpuMpHob
UINT32 CpuMpHob
Offset 0x032F - CpuMpHob Pointer for CpuMpHob.
Definition: FspsUpd.h:1143
FSP_S_TEST_CONFIG::CstateLatencyControl5Irtl
UINT16 CstateLatencyControl5Irtl
Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit...
Definition: FspsUpd.h:2946
FSP_S_TEST_CONFIG::SevenCoreRatioLimit
UINT8 SevenCoreRatioLimit
Offset 0x089C - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3058
FSP_S_TEST_CONFIG::TwoCoreRatioLimit
UINT8 TwoCoreRatioLimit
Offset 0x07CC - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2465
FSP_S_TEST_CONFIG::PowerLimit3DutyCycle
UINT8 PowerLimit3DutyCycle
Offset 0x07D5 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100...
Definition: FspsUpd.h:2519
FSP_S_CONFIG::PchPmLanWakeFromDeepSx
UINT8 PchPmLanWakeFromDeepSx
Offset 0x0674 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx...
Definition: FspsUpd.h:1633
FSP_S_TEST_CONFIG::ConfigTdpLock
UINT8 ConfigTdpLock
Offset 0x07E5 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0...
Definition: FspsUpd.h:2614
FSP_S_CONFIG::SataThermalSuggestedSetting
UINT8 SataThermalSuggestedSetting
Offset 0x072A - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting...
Definition: FspsUpd.h:2162
FSP_S_CONFIG::SgxSinitNvsData
UINT8 SgxSinitNvsData
Offset 0x079F - SgxSinitNvsData SgxSinitNvsData default values.
Definition: FspsUpd.h:2300
FSP_S_CONFIG::WatchDog
UINT8 WatchDog
Offset 0x0156 - WatchDog Timer Switch Enable/Disable.
Definition: FspsUpd.h:577
FSP_S_TEST_CONFIG::ApIdleManner
UINT8 ApIdleManner
Offset 0x07F0 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; ...
Definition: FspsUpd.h:2681
FSP_S_CONFIG::DmiTS0TW
UINT8 DmiTS0TW
Offset 0x071A - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values...
Definition: FspsUpd.h:2076
FSP_S_TEST_CONFIG::MaxRatio
UINT8 MaxRatio
Offset 0x081D - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F.
Definition: FspsUpd.h:2894
FSP_S_TEST_CONFIG::MachineCheckEnable
UINT8 MachineCheckEnable
Offset 0x07ED - Enable or Disable initialization of machine check registers Enable or Disable initial...
Definition: FspsUpd.h:2663
FSP_S_CONFIG::EcCmdLock
UINT8 EcCmdLock
Offset 0x078E - EcCmdLock EcCmdLock default values.
Definition: FspsUpd.h:2285
FSP_S_TEST_CONFIG::Custom2PowerLimit2
UINT32 Custom2PowerLimit2
Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for c...
Definition: FspsUpd.h:3000
FSPS_UPD
Fsp S UPD Configuration.
Definition: FspsUpd.h:3297
FSP_S_CONFIG::SataEnable
UINT8 SataEnable
Offset 0x0092 - Enable SATA Enable/disable SATA controller.
Definition: FspsUpd.h:269
FSP_S_CONFIG::PchHdaIDispLinkTmode
UINT8 PchHdaIDispLinkTmode
Offset 0x036B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T...
Definition: FspsUpd.h:1222
FSP_S_TEST_CONFIG::PowerLimit4Lock
UINT8 PowerLimit4Lock
Offset 0x07D7 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS...
Definition: FspsUpd.h:2531
FSP_S_CONFIG::UnusedUpdSpace4
UINT8 UnusedUpdSpace4
Offset 0x014E.
Definition: FspsUpd.h:528
FSP_S_CONFIG::UnusedUpdSpace10
UINT8 UnusedUpdSpace10
Offset 0x0367.
Definition: FspsUpd.h:1198
FSP_S_CONFIG::PchPmLpcClockRun
UINT8 PchPmLpcClockRun
Offset 0x0680 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of...
Definition: FspsUpd.h:1698
FSP_S_CONFIG::ChipsetInitBinLen
UINT32 ChipsetInitBinLen
Offset 0x0124 - Length of ChipsetInit Binary ChipsetInit Binary Length.
Definition: FspsUpd.h:462
FSP_S_CONFIG::SataRstRaidDeviceId
UINT8 SataRstRaidDeviceId
Offset 0x06E0 - PCH Sata Rst Raid Device Id Enable RAID Alternate ID.
Definition: FspsUpd.h:1833
FSP_S_CONFIG::AesEnable
UINT8 AesEnable
Offset 0x0277 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Stan...
Definition: FspsUpd.h:857
FSP_S_TEST_CONFIG::EightCoreRatioLimit
UINT8 EightCoreRatioLimit
Offset 0x089D - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3065
FSP_S_CONFIG::SerialIoUart0PinMuxing
UINT8 SerialIoUart0PinMuxing
Offset 0x0701 - PcdSerialIoUart0PinMuxing Select SerialIo Uart0 pin muxing.
Definition: FspsUpd.h:1960
FSP_S_CONFIG::SataP1T1M
UINT8 SataP1T1M
Offset 0x0722 - Port 1 T1 Multipler Port 1 T1 Multipler.
Definition: FspsUpd.h:2119
FSP_S_CONFIG::SataP0T3M
UINT8 SataP0T3M
Offset 0x0720 - Port 0 T3 Multipler Port 0 T3 Multipler.
Definition: FspsUpd.h:2109
FSP_S_TEST_CONFIG::TccOffsetLock
UINT8 TccOffsetLock
Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock ...
Definition: FspsUpd.h:2554
FSP_S_CONFIG::PchScsEmmcHs400DriverStrength
UINT8 PchScsEmmcHs400DriverStrength
Offset 0x06F9 - I/O Driver Strength Deprecated.
Definition: FspsUpd.h:1942
FSP_S_CONFIG::LogoSize
UINT32 LogoSize
Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
Definition: FspsUpd.h:96
FSP_S_CONFIG::NumOfDevIntConfig
UINT8 NumOfDevIntConfig
Offset 0x007F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry...
Definition: FspsUpd.h:220
FSP_S_TEST_CONFIG::Hwp
UINT8 Hwp
Offset 0x07CF - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support.
Definition: FspsUpd.h:2484
FSP_S_CONFIG::AmtSolEnabled
UINT8 AmtSolEnabled
Offset 0x015A - SOL Switch Enable/Disable.
Definition: FspsUpd.h:602
FSP_S_CONFIG::SataRstRaid1
UINT8 SataRstRaid1
Offset 0x06E2 - PCH Sata Rst Raid1 RAID1.
Definition: FspsUpd.h:1845
FSP_S_TEST_CONFIG::ProcHotLock
UINT8 ProcHotLock
Offset 0x081A - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: ...
Definition: FspsUpd.h:2875
FSP_S_CONFIG::DdiPortFHpd
UINT8 DdiPortFHpd
Offset 0x022C - Enable or disable HPD of DDI port F 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:790
FSP_S_CONFIG::PchIshPdtUnlock
UINT8 PchIshPdtUnlock
Offset 0x038E - PCH ISH PDT Unlock Msg 0: False; 1: True.
Definition: FspsUpd.h:1350
FSP_S_CONFIG::SataRstOromUiBanner
UINT8 SataRstOromUiBanner
Offset 0x06E6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER.
Definition: FspsUpd.h:1869
FSP_S_TEST_CONFIG::AutoThermalReporting
UINT8 AutoThermalReporting
Offset 0x0808 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI ...
Definition: FspsUpd.h:2767
FSP_S_CONFIG::ShowSpiController
UINT8 ShowSpiController
Offset 0x0034 - Show SPI controller Enable/disable to show SPI controller.
Definition: FspsUpd.h:141
FSP_S_CONFIG::FwProgress
UINT8 FwProgress
Offset 0x0159 - PET Progress Enable/Disable.
Definition: FspsUpd.h:596
FSP_S_CONFIG::EnableTcoTimer
UINT8 EnableTcoTimer
Offset 0x0758 - Enable TCO timer.
Definition: FspsUpd.h:2253
FSP_S_CONFIG::DebugInterfaceEnable
UINT8 DebugInterfaceEnable
Offset 0x0333 - Enable or Disable processor debug features Enable or Disable processor debug features...
Definition: FspsUpd.h:1149
FSP_S_CONFIG::DevIntConfigPtr
UINT32 DevIntConfigPtr
Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
Definition: FspsUpd.h:214
FSP_S_CONFIG::SciIrqSelect
UINT8 SciIrqSelect
Offset 0x0089 - Select SciIrqSelect SCI IRQ Select.
Definition: FspsUpd.h:237
FSP_S_CONFIG::DdiPortFDdc
UINT8 DdiPortFDdc
Offset 0x0230 - Enable or disable DDC of DDI port F 0(Default)=Disable, 1=Enable $EN_DIS.
Definition: FspsUpd.h:814
FSP_S_CONFIG::Heci3Enabled
UINT8 Heci3Enabled
Offset 0x014D - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not i...
Definition: FspsUpd.h:524
FSP_S_TEST_CONFIG::TccOffsetClamp
UINT8 TccOffsetClamp
Offset 0x07D9 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limi...
Definition: FspsUpd.h:2547
FSP_S_TEST_CONFIG::Custom3TurboActivationRatio
UINT8 Custom3TurboActivationRatio
Offset 0x07E3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3...
Definition: FspsUpd.h:2603
FSP_S_TEST_CONFIG::MonitorMwaitEnable
UINT8 MonitorMwaitEnable
Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instru...
Definition: FspsUpd.h:2657
FSP_S_CONFIG::PchT0Level
UINT16 PchT0Level
Offset 0x070D - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
Definition: FspsUpd.h:2017
FSPS_UPD::FspsConfig
FSP_S_CONFIG FspsConfig
Offset 0x0020.
Definition: FspsUpd.h:3305
FSP_S_CONFIG::PchIshGp2GpioAssign
UINT8 PchIshGp2GpioAssign
Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1314
FSP_S_CONFIG::PchDmiAspm
UINT8 PchDmiAspm
Offset 0x0346 - Enable DMI ASPM Deprecated.
Definition: FspsUpd.h:1161
FSP_S_TEST_CONFIG::CstateLatencyControl5TimeUnit
UINT8 CstateLatencyControl5TimeUnit
Offset 0x0818 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid val...
Definition: FspsUpd.h:2863
FSP_S_CONFIG::PsysOffset
UINT8 PsysOffset
Offset 0x02A1 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction...
Definition: FspsUpd.h:917
FSP_S_CONFIG::DdiPortBHpd
UINT8 DdiPortBHpd
Offset 0x0229 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:772
FSP_S_TEST_CONFIG::PowerLimit3Lock
UINT8 PowerLimit3Lock
Offset 0x07D6 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS...
Definition: FspsUpd.h:2525
FSP_S_CONFIG::DdiPortDDdc
UINT8 DdiPortDDdc
Offset 0x022F - Enable or disable DDC of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:808
FSP_S_CONFIG::SataRstOromUiDelay
UINT8 SataRstOromUiDelay
Offset 0x06E7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PC...
Definition: FspsUpd.h:1874
SiPchNoInt
No Interrupt Pin.
Definition: FspsUpd.h:65
FSP_S_TEST_CONFIG::FiveCoreRatioLimit
UINT8 FiveCoreRatioLimit
Offset 0x089A - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3044
FSP_S_CONFIG::TTSuggestedSetting
UINT8 TTSuggestedSetting
Offset 0x0716 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting...
Definition: FspsUpd.h:2052
FSP_S_CONFIG::PsysSlope
UINT8 PsysSlope
Offset 0x02A0 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction...
Definition: FspsUpd.h:911
FSP_S_CONFIG::DdiPortCHpd
UINT8 DdiPortCHpd
Offset 0x022A - Enable or disable HPD of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:778
FSP_S_CONFIG::PchPmDeepSxPol
UINT8 PchPmDeepSxPol
Offset 0x0675 - PCH Pm Deep Sx Pol Deep Sx Policy.
Definition: FspsUpd.h:1639
FSP_S_CONFIG::PchIoApicEntry24_119
UINT8 PchIoApicEntry24_119
Offset 0x037D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable.
Definition: FspsUpd.h:1251
FSP_S_CONFIG::AmtKvmEnabled
UINT8 AmtKvmEnabled
Offset 0x0160 - KVM Switch Enable/Disable.
Definition: FspsUpd.h:626
FSP_S_TEST_CONFIG::CStatePreWake
UINT8 CStatePreWake
Offset 0x080F - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake.
Definition: FspsUpd.h:2809
FSP_S_CONFIG::SataRstRaid0
UINT8 SataRstRaid0
Offset 0x06E1 - PCH Sata Rst Raid0 RAID0.
Definition: FspsUpd.h:1839
FSP_S_CONFIG::SgxEpoch1
UINT64 SgxEpoch1
Offset 0x0797 - SgxEpoch1 SgxEpoch1 default values.
Definition: FspsUpd.h:2295
FSP_S_CONFIG::FastPkgCRampDisableFivr
UINT8 FastPkgCRampDisableFivr
Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew...
Definition: FspsUpd.h:1081
FSP_S_CONFIG::PchPmSlpLanLowDc
UINT8 PchPmSlpLanLowDc
Offset 0x0682 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power.
Definition: FspsUpd.h:1710
FSP_S_CONFIG::SataRstRaid10
UINT8 SataRstRaid10
Offset 0x06E3 - PCH Sata Rst Raid10 RAID10.
Definition: FspsUpd.h:1851
FSP_S_TEST_CONFIG::CstCfgCtrIoMwaitRedirection
UINT8 CstCfgCtrIoMwaitRedirection
Offset 0x0811 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; ...
Definition: FspsUpd.h:2821
FSP_S_CONFIG::PchHdaLinkFrequency
UINT8 PchHdaLinkFrequency
Offset 0x0369 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz...
Definition: FspsUpd.h:1210
FSP_S_TEST_CONFIG::PsysPowerLimit1
UINT8 PsysPowerLimit1
Offset 0x07E7 - PL1 Enable value PL1 Enable value to limit average platform power.
Definition: FspsUpd.h:2626
FSP_S_TEST_CONFIG::ThermalMonitor
UINT8 ThermalMonitor
Offset 0x0809 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: E...
Definition: FspsUpd.h:2773
FSP_S_CONFIG::UnusedUpdSpace3
UINT8 UnusedUpdSpace3
Offset 0x014A.
Definition: FspsUpd.h:505
FSP_S_CONFIG::DmiSuggestedSetting
UINT8 DmiSuggestedSetting
Offset 0x0719 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative valu...
Definition: FspsUpd.h:2070
FSP_S_CONFIG::PchIshGp6GpioAssign
UINT8 PchIshGp6GpioAssign
Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1338
FSP_S_CONFIG::PchHdaDspEnable
UINT8 PchHdaDspEnable
Offset 0x002D - Enable HD Audio DSP Enable/disable HD Audio DSP feature.
Definition: FspsUpd.h:113
FSP_S_CONFIG::DmiTS1TW
UINT8 DmiTS1TW
Offset 0x071B - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width.
Definition: FspsUpd.h:2082
FSP_S_CONFIG::AcousticNoiseMitigation
UINT8 AcousticNoiseMitigation
Offset 0x02A2 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature...
Definition: FspsUpd.h:925
FSP_S_CONFIG::PchScsEmmcHs400TxDataDll
UINT8 PchScsEmmcHs400TxDataDll
Offset 0x06F8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)...
Definition: FspsUpd.h:1936
FSP_S_TEST_CONFIG::ConfigTdpLevel
UINT8 ConfigTdpLevel
Offset 0x081B - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nom...
Definition: FspsUpd.h:2881
FSP_S_CONFIG::EcCmdProvisionEav
UINT8 EcCmdProvisionEav
Offset 0x078D - EcCmdProvisionEav Ephemeral Authorization Value default values.
Definition: FspsUpd.h:2280
FSP_S_CONFIG::BiosGuardAttr
UINT32 BiosGuardAttr
Offset 0x0779 - BiosGuardAttr BiosGuardAttr default values.
Definition: FspsUpd.h:2263
FSPS_UPD::FspUpdHeader
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FspsUpd.h:3301
FSP_S_CONFIG::Device4Enable
UINT8 Device4Enable
Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
Definition: FspsUpd.h:107
FSP_S_CONFIG::PchHdaAudioLinkHda
UINT8 PchHdaAudioLinkHda
Offset 0x00FD - Enable HD Audio Link Enable/disable HD Audio Link.
Definition: FspsUpd.h:335
FSP_S_CONFIG::PchTTState13Enable
UINT8 PchTTState13Enable
Offset 0x0714 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 1...
Definition: FspsUpd.h:2040
SI_PCH_DEVICE_INTERRUPT_CONFIG::Irq
UINT8 Irq
IRQ to be set for device.
Definition: FspsUpd.h:78
FSPS_UPD::UpdTerminator
UINT16 UpdTerminator
Offset 0x0A80.
Definition: FspsUpd.h:3313
FSP_S_CONFIG::SlowSlewRateForGt
UINT8 SlowSlewRateForGt
Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configur...
Definition: FspsUpd.h:946
FSP_S_TEST_CONFIG::PchUnlockGpioPads
UINT8 PchUnlockGpioPads
Offset 0x08C1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose...
Definition: FspsUpd.h:3168
FSP_S_TEST_CONFIG::Custom2TurboActivationRatio
UINT8 Custom2TurboActivationRatio
Offset 0x07E0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2...
Definition: FspsUpd.h:2587
FSP_S_CONFIG::TurboMode
UINT8 TurboMode
Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode.
Definition: FspsUpd.h:161
FSP_S_CONFIG::PchScsEmmcHs400DllDataValid
UINT8 PchScsEmmcHs400DllDataValid
Offset 0x06F6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid.
Definition: FspsUpd.h:1926
FSP_S_CONFIG::PchHdaPme
UINT8 PchHdaPme
Offset 0x0366 - Enable Pme Enable Azalia wake-on-ring.
Definition: FspsUpd.h:1194
FSP_S_TEST_CONFIG::CstateLatencyControl1TimeUnit
UINT8 CstateLatencyControl1TimeUnit
Offset 0x0814 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid val...
Definition: FspsUpd.h:2840
FSP_S_CONFIG::PchHdaVcType
UINT8 PchHdaVcType
Offset 0x0368 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1.
Definition: FspsUpd.h:1204
FSP_S_CONFIG::PchTsmicLock
UINT8 PchTsmicLock
Offset 0x070C - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip...
Definition: FspsUpd.h:2012
FSP_S_TEST_CONFIG::PowerLimit3Time
UINT8 PowerLimit3Time
Offset 0x07D4 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms...
Definition: FspsUpd.h:2514
FSP_S_CONFIG::PchIshGp5GpioAssign
UINT8 PchIshGp5GpioAssign
Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1332
FSP_S_CONFIG::PchHdaIDispCodecDisconnect
UINT8 PchHdaIDispCodecDisconnect
Offset 0x036D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
Definition: FspsUpd.h:1235
FSP_S_CONFIG::Reserved2
UINT8 Reserved2
Offset 0x0304 - Reserved Reserved.
Definition: FspsUpd.h:1027
FSP_S_CONFIG::WatchDogTimerOs
UINT16 WatchDogTimerOs
Offset 0x015B - OS Timer 16 bits Value, Set OS watchdog timer.
Definition: FspsUpd.h:608
FSP_S_CONFIG::TetonGlacierSupport
UINT8 TetonGlacierSupport
Offset 0x0667 - Teton Glacier Support Enables support for the Teton Glacier card. ...
Definition: FspsUpd.h:1570
FSP_S_TEST_CONFIG::PmgCstCfgCtrlLock
UINT8 PmgCstCfgCtrlLock
Offset 0x080B - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable...
Definition: FspsUpd.h:2785
FSP_S_CONFIG::PchIshGp1GpioAssign
UINT8 PchIshGp1GpioAssign
Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1308
FSP_S_CONFIG::PchHdaDspUaaCompliance
UINT8 PchHdaDspUaaCompliance
Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (...
Definition: FspsUpd.h:1229
FSP_S_TEST_CONFIG::HwpInterruptControl
UINT8 HwpInterruptControl
Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Ena...
Definition: FspsUpd.h:3037
FSP_S_CONFIG::DmiTS3TW
UINT8 DmiTS3TW
Offset 0x071D - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width.
Definition: FspsUpd.h:2094
FSP_S_TEST_CONFIG::PowerLimit1Time
UINT8 PowerLimit1Time
Offset 0x07D1 - Package Long duration turbo mode time Package Long duration turbo mode time window in...
Definition: FspsUpd.h:2497
FSP_S_TEST_CONFIG::MlcSpatialPrefetcher
UINT8 MlcSpatialPrefetcher
Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0:...
Definition: FspsUpd.h:2651
FSP_S_CONFIG::TxtEnable
UINT8 TxtEnable
Offset 0x0305 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable.
Definition: FspsUpd.h:1033
FSP_S_TEST_CONFIG::Custom2ConfigTdpControl
UINT8 Custom2ConfigTdpControl
Offset 0x07E1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2592
FSP_S_CONFIG::ScsSdCardEnabled
UINT8 ScsSdCardEnabled
Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller.
Definition: FspsUpd.h:135
FSP_S_CONFIG::SiCsmFlag
UINT8 SiCsmFlag
Offset 0x07A0 - Si Config CSM Flag.
Definition: FspsUpd.h:2306
FSP_S_CONFIG::EsataSpeedLimit
UINT8 EsataSpeedLimit
Offset 0x068E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
Definition: FspsUpd.h:1777
FSP_S_CONFIG::DeltaT12PowerCycleDelay
UINT16 DeltaT12PowerCycleDelay
Offset 0x0232 - Delta T12 Power Cycle Delay required in ms Select the value for delay required...
Definition: FspsUpd.h:828
FSP_S_TEST_CONFIG
Fsp S Test Configuration.
Definition: FspsUpd.h:2358
FSP_S_CONFIG::PchPwrOptEnable
UINT8 PchPwrOptEnable
Offset 0x0347 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side.
Definition: FspsUpd.h:1167
FSP_S_CONFIG::PchPcieDeviceOverrideTablePtr
UINT32 PchPcieDeviceOverrideTablePtr
Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to overrid...
Definition: FspsUpd.h:2245
FSP_S_CONFIG::McivrRfiFrequencyAdjust
UINT8 McivrRfiFrequencyAdjust
Offset 0x030E - McIVR RFI Frequency Adjustment PCODE MMIO Mailbox: Adjust the RFI frequency relative ...
Definition: FspsUpd.h:1055
FSP_S_TEST_CONFIG::HdcControl
UINT8 HdcControl
Offset 0x07D0 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration.
Definition: FspsUpd.h:2490
FSP_S_TEST_CONFIG::Custom3PowerLimit1Time
UINT8 Custom3PowerLimit1Time
Offset 0x07E2 - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2598
FSP_S_CONFIG::PchPmPcieWakeFromDeepSx
UINT8 PchPmPcieWakeFromDeepSx
Offset 0x0671 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx...
Definition: FspsUpd.h:1614
FSP_S_TEST_CONFIG::PsysPowerLimit1Power
UINT32 PsysPowerLimit1Power
Offset 0x0890 - Platform PL1 power Platform PL1 power.
Definition: FspsUpd.h:3018
FSP_S_CONFIG::CpuMpPpi
UINT32 CpuMpPpi
Offset 0x032B - CpuMpPpi Pointer for CpuMpPpi.
Definition: FspsUpd.h:1138
FSP_S_CONFIG::PchEnableComplianceMode
UINT8 PchEnableComplianceMode
Offset 0x0734 - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this o...
Definition: FspsUpd.h:2195
FSP_S_CONFIG::SataSpeedLimit
UINT8 SataSpeedLimit
Offset 0x068F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: ...
Definition: FspsUpd.h:1782
AUDIO_AZALIA_VERB_TABLE
Audio Azalia Verb Table structure.
Definition: FspsUpd.h:56
FSP_S_CONFIG::MicrocodeRegionSize
UINT32 MicrocodeRegionSize
Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
Definition: FspsUpd.h:155
FSP_S_CONFIG::SataP1T2M
UINT8 SataP1T2M
Offset 0x0723 - Port 1 T2 Multipler Port 1 T2 Multipler.
Definition: FspsUpd.h:2124
FSP_S_CONFIG::ChipsetInitBinPtr
UINT32 ChipsetInitBinPtr
Offset 0x0120 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer.
Definition: FspsUpd.h:457
FSP_S_CONFIG::SataRstLegacyOrom
UINT8 SataRstLegacyOrom
Offset 0x011A - PCH SATA use RST Legacy OROM Use PCH SATA RST Legacy OROM when CSM is Enabled $EN_DIS...
Definition: FspsUpd.h:438
FSP_S_CONFIG::PchIshGp3GpioAssign
UINT8 PchIshGp3GpioAssign
Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1320
FSP_S_CONFIG::SataRstSmartStorage
UINT8 SataRstSmartStorage
Offset 0x06EB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit.
Definition: FspsUpd.h:1899
FSP_S_TEST_CONFIG::TurboPowerLimitLock
UINT8 TurboPowerLimitLock
Offset 0x07D3 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable ...
Definition: FspsUpd.h:2509
FSP_S_CONFIG::PchIshI2c2GpioAssign
UINT8 PchIshI2c2GpioAssign
Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1296
FSP_S_CONFIG::DdiPortBDdc
UINT8 DdiPortBDdc
Offset 0x022D - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:796
AUDIO_AZALIA_VERB_TABLE::Data
UINT32 * Data
Pointer to the data buffer. Its length is specified in the header.
Definition: FspsUpd.h:58
AZALIA_HEADER::VendorId
UINT16 VendorId
Codec Vendor ID.
Definition: FspsUpd.h:45
FSP_S_CONFIG::PchIoApicId
UINT8 PchIoApicId
Offset 0x037E - PCH Io Apic ID This member determines IOAPIC ID.
Definition: FspsUpd.h:1256
FSP_S_CONFIG::PchPmSlpS0Vm070VSupport
UINT8 PchPmSlpS0Vm070VSupport
Offset 0x0153 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy.
Definition: FspsUpd.h:559
FSP_S_CONFIG::SgxEpoch0
UINT64 SgxEpoch0
Offset 0x078F - SgxEpoch0 SgxEpoch0 default values.
Definition: FspsUpd.h:2290
FSP_S_TEST_CONFIG::Cx
UINT8 Cx
Offset 0x080A - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-s...
Definition: FspsUpd.h:2779
FSP_S_CONFIG::SataP1TDispFinit
UINT8 SataP1TDispFinit
Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch.
Definition: FspsUpd.h:2156
FSP_S_CONFIG::PavpEnable
UINT8 PavpEnable
Offset 0x0216 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEn...
Definition: FspsUpd.h:727
FSP_S_CONFIG::SlpS0WithGbeSupport
UINT8 SlpS0WithGbeSupport
Offset 0x01FC - SlpS0WithGbeSupport Enable/Disable SLP_S0 with GBE Support.
Definition: FspsUpd.h:683
FSP_S_CONFIG::RampUp
UINT8 RampUp
Offset 0x0329 - Ramp Up Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range...
Definition: FspsUpd.h:1126
FSP_S_CONFIG::FastPkgCRampDisableGt
UINT8 FastPkgCRampDisableGt
Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew R...
Definition: FspsUpd.h:1007
FSP_S_CONFIG::PchLanLtrEnable
UINT8 PchLanLtrEnable
Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable.
Definition: FspsUpd.h:1356
FSP_S_CONFIG::SiSsidTablePtr
UINT32 SiSsidTablePtr
Offset 0x07A1.
Definition: FspsUpd.h:2310
FSP_S_TEST_CONFIG::PmSupport
UINT8 PmSupport
Offset 0x07BB - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS.
Definition: FspsUpd.h:2413
FSP_S_CONFIG::PchUsbOverCurrentEnable
UINT8 PchUsbOverCurrentEnable
Offset 0x0149 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI control...
Definition: FspsUpd.h:501
FSP_S_CONFIG::PchHdaAudioLinkDmic0
UINT8 PchHdaAudioLinkDmic0
Offset 0x00FE - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link.
Definition: FspsUpd.h:341
FSP_S_CONFIG::PchSirqEnable
UINT8 PchSirqEnable
Offset 0x0708 - Enable Serial IRQ Determines if enable Serial IRQ.
Definition: FspsUpd.h:1988
FSP_S_CONFIG::TraceHubMemBase
UINT32 TraceHubMemBase
Offset 0x011B - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired...
Definition: FspsUpd.h:445
FSP_S_CONFIG::DdiPortDHpd
UINT8 DdiPortDHpd
Offset 0x022B - Enable or disable HPD of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:784
FSP_S_CONFIG::UnusedUpdSpace12
UINT8 UnusedUpdSpace12
Offset 0x037F.
Definition: FspsUpd.h:1260
FSP_S_CONFIG::PchIshI2c0GpioAssign
UINT8 PchIshI2c0GpioAssign
Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1284
FSP_S_CONFIG::McivrSpreadSpectrum
UINT8 McivrSpreadSpectrum
Offset 0x0311 - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum.
Definition: FspsUpd.h:1068
FSP_S_TEST_CONFIG::PchPciePort8xhDecodePortIndex
UINT8 PchPciePort8xhDecodePortIndex
Offset 0x0A5D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh De...
Definition: FspsUpd.h:3253
FSP_S_CONFIG::PchCnviMode
UINT8 PchCnviMode
Offset 0x0146 - CNVi Configuration This option allows for automatic detection of Connectivity Solutio...
Definition: FspsUpd.h:481
FSP_S_TEST_CONFIG::SataTestMode
UINT8 SataTestMode
Offset 0x0A5F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes.
Definition: FspsUpd.h:3265
FSP_S_TEST_CONFIG::CstateLatencyControl4TimeUnit
UINT8 CstateLatencyControl4TimeUnit
Offset 0x0817 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns ...
Definition: FspsUpd.h:2857
FSP_S_CONFIG::LogoPtr
UINT32 LogoPtr
Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
Definition: FspsUpd.h:91
FSP_S_CONFIG::DmiAspm
UINT8 DmiAspm
Offset 0x0201 - DMI ASPM 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 0:Disable, 1:L0s, 2:L1, 3:L0sL1.
Definition: FspsUpd.h:699
FSP_S_TEST_CONFIG::DisableTurboGt
UINT8 DisableTurboGt
Offset 0x07BF - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT ...
Definition: FspsUpd.h:2445
FSP_S_TEST_CONFIG::SgxSinitDataFromTpm
UINT8 SgxSinitDataFromTpm
Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values.
Definition: FspsUpd.h:3131
FSP_S_TEST_CONFIG::ProcessorTraceMemBase
UINT64 ProcessorTraceMemBase
Offset 0x07F3 - Base of memory region allocated for Processor Trace Base address of memory region all...
Definition: FspsUpd.h:2699
FSP_S_CONFIG::PchHdaVerbTableEntryNum
UINT8 PchHdaVerbTableEntryNum
Offset 0x008C - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
Definition: FspsUpd.h:253
FSP_S_CONFIG::SataP0T2M
UINT8 SataP0T2M
Offset 0x071F - Port 0 T2 Multipler Port 0 T2 Multipler.
Definition: FspsUpd.h:2104
FSP_S_TEST_CONFIG::PchSbAccessUnlock
UINT8 PchSbAccessUnlock
Offset 0x08C3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e...
Definition: FspsUpd.h:3181
FSP_S_TEST_CONFIG::MaxRingRatioLimit
UINT8 MaxRingRatioLimit
Offset 0x08A4 - Minimum Ring ratio limit override Maximum Ring ratio limit override.
Definition: FspsUpd.h:3108
FSP_S_TEST_CONFIG::Eist
UINT8 Eist
Offset 0x0800 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Techno...
Definition: FspsUpd.h:2717
FSP_S_CONFIG::SataP0Tinact
UINT8 SataP0Tinact
Offset 0x0726 - Port 0 Tinactive Port 0 Tinactive.
Definition: FspsUpd.h:2139
FSP_S_CONFIG::PchPmDisableNativePowerButton
UINT8 PchPmDisableNativePowerButton
Offset 0x0686 - PCH Pm Disable Native Power Button Power button native mode disable.
Definition: FspsUpd.h:1731
FSP_S_CONFIG::SataRstIrrtOnly
UINT8 SataRstIrrtOnly
Offset 0x06EA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports...
Definition: FspsUpd.h:1893
FSP_S_TEST_CONFIG::TccOffsetTimeWindowForRatl
UINT32 TccOffsetTimeWindowForRatl
Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit.
Definition: FspsUpd.h:2976
FSP_S_TEST_CONFIG::PsysPmax
UINT16 PsysPmax
Offset 0x0856 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax.
Definition: FspsUpd.h:2916
FSP_S_CONFIG::PchHdaAudioLinkSsp1
UINT8 PchHdaAudioLinkSsp1
Offset 0x0101 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link.
Definition: FspsUpd.h:359
FSP_S_TEST_CONFIG::ProcHotResponse
UINT8 ProcHotResponse
Offset 0x0806 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; ...
Definition: FspsUpd.h:2755
FSP_S_CONFIG::PchPmPmeB0S5Dis
UINT8 PchPmPmeB0S5Dis
Offset 0x0669 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed ...
Definition: FspsUpd.h:1582
SI_PCH_DEVICE_INTERRUPT_CONFIG::Function
UINT8 Function
Device function.
Definition: FspsUpd.h:76
FSP_S_CONFIG::PcieRpImrSelection
UINT8 PcieRpImrSelection
Offset 0x066E - PCIE IMR port number Selects PCIE root port number for IMR feature.
Definition: FspsUpd.h:1598
FSP_S_CONFIG::SataRstLedLocate
UINT8 SataRstLedLocate
Offset 0x06E9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to...
Definition: FspsUpd.h:1887
FSP_S_CONFIG::DdiPortEdp
UINT8 DdiPortEdp
Offset 0x0228 - Enable or disable eDP device 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:766
AZALIA_HEADER::Reserved
UINT32 Reserved
Reserved for future use. Must be set to 0.
Definition: FspsUpd.h:50
FSP_S_CONFIG::PchEnableDbcObs
UINT8 PchEnableDbcObs
Offset 0x067C - USB Overcurrent Override for DbC This option overrides USB Over Current enablement st...
Definition: FspsUpd.h:1687
FSP_S_TEST_CONFIG::PowerLimit2Power
UINT32 PowerLimit2Power
Offset 0x0868 - Package Short duration turbo mode power limit Package Short duration turbo mode power...
Definition: FspsUpd.h:2958
FSP_S_CONFIG::PchIshUart1GpioAssign
UINT8 PchIshUart1GpioAssign
Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1278
FSP_S_TEST_CONFIG::C3StateUnDemotion
UINT8 C3StateUnDemotion
Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion...
Definition: FspsUpd.h:3120
FSP_S_CONFIG::SataP0T1M
UINT8 SataP0T1M
Offset 0x071E - Port 0 T1 Multipler Port 0 T1 Multipler.
Definition: FspsUpd.h:2099
FSP_S_CONFIG::PchIshGp4GpioAssign
UINT8 PchIshGp4GpioAssign
Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1326
FSP_S_CONFIG::PchIshSpiGpioAssign
UINT8 PchIshSpiGpioAssign
Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1266
FSP_S_CONFIG::PreWake
UINT8 PreWake
Offset 0x0328 - Pre Wake Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range...
Definition: FspsUpd.h:1119
AZALIA_HEADER::DeviceId
UINT16 DeviceId
Codec Device ID.
Definition: FspsUpd.h:46
FSP_S_TEST_CONFIG::EnableItbmDriver
UINT8 EnableItbmDriver
Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3...
Definition: FspsUpd.h:3077
FSP_S_TEST_CONFIG::PowerLimit3
UINT32 PowerLimit3
Offset 0x086C - Package PL3 power limit Package PL3 power limit.
Definition: FspsUpd.h:2964
FSP_S_CONFIG::TetonGlacierCR
UINT8 TetonGlacierCR
Offset 0x0668 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected...
Definition: FspsUpd.h:1576
FSP_S_TEST_CONFIG::DisableVrThermalAlert
UINT8 DisableVrThermalAlert
Offset 0x0807 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1:...
Definition: FspsUpd.h:2761
FSP_S_TEST_CONFIG::CpuWakeUpTimer
UINT8 CpuWakeUpTimer
Offset 0x08A2 - CpuWakeUpTimer Enable long CPU Wakeup Timer.
Definition: FspsUpd.h:3096
FSP_S_CONFIG::GpioIrqRoute
UINT8 GpioIrqRoute
Offset 0x0088 - Select GPIO IRQ Route GPIO IRQ Select.
Definition: FspsUpd.h:232
FSP_S_CONFIG::DmiTS2TW
UINT8 DmiTS2TW
Offset 0x071C - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width.
Definition: FspsUpd.h:2088
FSP_S_TEST_CONFIG::PcieEnablePort8xhDecode
UINT8 PcieEnablePort8xhDecode
Offset 0x0A5C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh D...
Definition: FspsUpd.h:3248
FSP_S_CONFIG::PchHdaCodecSxWakeCapability
UINT8 PchHdaCodecSxWakeCapability
Offset 0x0091 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx...
Definition: FspsUpd.h:263
FSP_S_CONFIG::PchPmSlpSusMinAssert
UINT8 PchPmSlpSusMinAssert
Offset 0x0678 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. ...
Definition: FspsUpd.h:1654
FSP_S_CONFIG::PchEspiBmeMasterSlaveEnabled
UINT8 PchEspiBmeMasterSlaveEnabled
Offset 0x0119 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS...
Definition: FspsUpd.h:432
FSP_S_TEST_CONFIG::PkgCStateDemotion
UINT8 PkgCStateDemotion
Offset 0x080D - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion...
Definition: FspsUpd.h:2797
FSP_S_CONFIG::PmcDbgMsgEn
UINT8 PmcDbgMsgEn
Offset 0x011F - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; ...
Definition: FspsUpd.h:452
FSP_S_CONFIG::GnaEnable
UINT8 GnaEnable
Offset 0x021A - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:749
FSP_S_TEST_CONFIG::C3StateAutoDemotion
UINT8 C3StateAutoDemotion
Offset 0x08A5 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion.
Definition: FspsUpd.h:3114
FSP_S_TEST_CONFIG::Custom2PowerLimit1
UINT32 Custom2PowerLimit1
Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for...
Definition: FspsUpd.h:2994
FSP_S_CONFIG::SerialIoDebugUartNumber
UINT8 SerialIoDebugUartNumber
Offset 0x0706 - UART Number For Debug Purpose UART number for debug purpose.
Definition: FspsUpd.h:1976
FSP_S_TEST_CONFIG::PchSbiUnlock
UINT8 PchSbiUnlock
Offset 0x08C2 - PCH Unlock SBI access Deprecated $EN_DIS.
Definition: FspsUpd.h:3174
FSP_S_CONFIG::PchPmPwrBtnOverridePeriod
UINT8 PchPmPwrBtnOverridePeriod
Offset 0x0683 - PCH Pm Pwr Btn Override Period PCH power button override period.
Definition: FspsUpd.h:1715
FSP_S_TEST_CONFIG::PowerLimit1
UINT32 PowerLimit1
Offset 0x0864 - Package Long duration turbo mode power limit Package Long duration turbo mode power l...
Definition: FspsUpd.h:2952
FSP_S_CONFIG::PchPmSlpS0Enable
UINT8 PchPmSlpS0Enable
Offset 0x0687 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idl...
Definition: FspsUpd.h:1737
FSP_S_CONFIG::Enable8254ClockGating
UINT8 Enable8254ClockGating
Offset 0x074F - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support...
Definition: FspsUpd.h:2213
FSP_S_CONFIG::PcieComplianceTestMode
UINT8 PcieComplianceTestMode
Offset 0x0665 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance...
Definition: FspsUpd.h:1557
FSP_S_CONFIG::X2ApicOptOut
UINT8 X2ApicOptOut
Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS...
Definition: FspsUpd.h:755
FSP_S_CONFIG::SataP1TDisp
UINT8 SataP1TDisp
Offset 0x0725 - Port 1 Tdispatch Port 1 Tdispatch.
Definition: FspsUpd.h:2134
FSP_S_TEST_CONFIG::ChapDeviceEnable
UINT8 ChapDeviceEnable
Offset 0x07B1 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disable...
Definition: FspsUpd.h:2368
FSP_S_CONFIG::SataP1Tinact
UINT8 SataP1Tinact
Offset 0x0728 - Port 1 Tinactive Port 1 Tinactive.
Definition: FspsUpd.h:2150
SI_PCH_DEVICE_INTERRUPT_CONFIG::IntX
UINT8 IntX
Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
Definition: FspsUpd.h:77
FSP_S_TEST_CONFIG::EndOfPostMessage
UINT8 EndOfPostMessage
Offset 0x08BB - End of Post message Test, Send End of Post message.
Definition: FspsUpd.h:3138
FSP_S_CONFIG::PchHdaAudioLinkSsp2
UINT8 PchHdaAudioLinkSsp2
Offset 0x0102 - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link.
Definition: FspsUpd.h:365
FSP_S_CONFIG::PcieDisableRootPortClockGating
UINT8 PcieDisableRootPortClockGating
Offset 0x0662 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for...
Definition: FspsUpd.h:1541
FSP_S_CONFIG::PchT1Level
UINT16 PchT1Level
Offset 0x070F - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
Definition: FspsUpd.h:2022
SI_PCH_INT_PIN
SI_PCH_INT_PIN
Refer to the definition of PCH_INT_PIN.
Definition: FspsUpd.h:64
SI_PCH_DEVICE_INTERRUPT_CONFIG::Device
UINT8 Device
Device number.
Definition: FspsUpd.h:75
SI_PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device...
Definition: FspsUpd.h:74
FSP_S_CONFIG::PchPmSlpAMinAssert
UINT8 PchPmSlpAMinAssert
Offset 0x0679 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy.
Definition: FspsUpd.h:1659
FSP_S_TEST_CONFIG::DebugInterfaceEnable
UINT8 DebugInterfaceEnable
Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features. ...
Definition: FspsUpd.h:2669
FSP_S_CONFIG
Fsp S Configuration.
Definition: FspsUpd.h:86
FSP_S_TEST_CONFIG::MctpBroadcastCycle
UINT8 MctpBroadcastCycle
Offset 0x0A73 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enab...
Definition: FspsUpd.h:3288
FSP_S_CONFIG::VrPowerDeliveryDesign
UINT32 VrPowerDeliveryDesign
Offset 0x0324 - CPU VR Power Delivery Design Used to communicate the power delivery design capability...
Definition: FspsUpd.h:1112
FSP_S_CONFIG::FastPkgCRampDisableIa
UINT8 FastPkgCRampDisableIa
Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew R...
Definition: FspsUpd.h:932
FSP_S_CONFIG::AmtEnabled
UINT8 AmtEnabled
Offset 0x0155 - AMT Switch Enable/Disable.
Definition: FspsUpd.h:571
FSP_S_TEST_CONFIG::SkipPamLock
UINT8 SkipPamLock
Offset 0x07B2 - Skip PAM register lock Enable: PAM register will not be locked by RC...
Definition: FspsUpd.h:2375
FSP_S_TEST_CONFIG::VtdDisable
UINT8 VtdDisable
Offset 0x07BD - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS...
Definition: FspsUpd.h:2425
FSPS_UPD::FspsTestConfig
FSP_S_TEST_CONFIG FspsTestConfig
Offset 0x07AD.
Definition: FspsUpd.h:3309
FSP_S_CONFIG::SataRstOptaneMemory
UINT8 SataRstOptaneMemory
Offset 0x0750 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
Definition: FspsUpd.h:2219
FSP_S_CONFIG::PchHdaAudioLinkSndw4
UINT8 PchHdaAudioLinkSndw4
Offset 0x0106 - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link.
Definition: FspsUpd.h:389
FSP_S_CONFIG::FivrSpreadSpectrum
UINT8 FivrSpreadSpectrum
Offset 0x0312 - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments.
Definition: FspsUpd.h:1074
FSP_S_CONFIG::PchStartFramePulse
UINT8 PchStartFramePulse
Offset 0x070A - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk...
Definition: FspsUpd.h:2000
FSP_S_TEST_CONFIG::RenderStandby
UINT8 RenderStandby
Offset 0x07BA - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS.
Definition: FspsUpd.h:2407
FSP_S_CONFIG::PcieRpFunctionSwap
UINT8 PcieRpFunctionSwap
Offset 0x0666 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root...
Definition: FspsUpd.h:1564
FSP_S_CONFIG::PcieEnablePeerMemoryWrite
UINT8 PcieEnablePeerMemoryWrite
Offset 0x0663 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are en...
Definition: FspsUpd.h:1547
FSP_S_CONFIG::ScsUfsEnabled
UINT8 ScsUfsEnabled
Offset 0x0145 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller.
Definition: FspsUpd.h:474
FSP_S_TEST_CONFIG::Custom3PowerLimit1
UINT32 Custom3PowerLimit1
Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for...
Definition: FspsUpd.h:3006
FSP_S_CONFIG::SataRstIrrt
UINT8 SataRstIrrt
Offset 0x06E5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology.
Definition: FspsUpd.h:1863
FSP_S_CONFIG::PchIshI2c1GpioAssign
UINT8 PchIshI2c1GpioAssign
Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1290
FSP_S_TEST_CONFIG::TccActivationOffset
UINT8 TccActivationOffset
Offset 0x07D8 - TCC Activation Offset TCC Activation Offset.
Definition: FspsUpd.h:2539
FSP_S_TEST_CONFIG::Custom3ConfigTdpControl
UINT8 Custom3ConfigTdpControl
Offset 0x07E4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2608
FSP_S_CONFIG::PchTemperatureHotLevel
UINT16 PchTemperatureHotLevel
Offset 0x0732 - Thermal Device Temperature Decides the temperature.
Definition: FspsUpd.h:2188
FSP_S_CONFIG::SlowSlewRateForSa
UINT8 SlowSlewRateForSa
Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configur...
Definition: FspsUpd.h:953
FSP_S_TEST_CONFIG::CstateLatencyControl0Irtl
UINT16 CstateLatencyControl0Irtl
Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit...
Definition: FspsUpd.h:2921
FSP_S_TEST_CONFIG::DisableProcHotOut
UINT8 DisableProcHotOut
Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# ...
Definition: FspsUpd.h:2749
FSP_S_CONFIG::PchPmMeWakeSts
UINT8 PchPmMeWakeSts
Offset 0x0688 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) re...
Definition: FspsUpd.h:1743
FSP_S_CONFIG::UnusedUpdSpace21
UINT8 UnusedUpdSpace21
Offset 0x0700.
Definition: FspsUpd.h:1954
FSP_S_TEST_CONFIG::MlcStreamerPrefetcher
UINT8 MlcStreamerPrefetcher
Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; ...
Definition: FspsUpd.h:2645
FSP_S_CONFIG::Enable8254ClockGatingOnS3
UINT8 Enable8254ClockGatingOnS3
Offset 0x0752 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGat...
Definition: FspsUpd.h:2233
FSP_S_CONFIG::SataP0TDisp
UINT8 SataP0TDisp
Offset 0x0721 - Port 0 Tdispatch Port 0 Tdispatch.
Definition: FspsUpd.h:2114
FSP_S_CONFIG::PcieRpPtmMask
UINT32 PcieRpPtmMask
Offset 0x0108 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports...
Definition: FspsUpd.h:401
FSP_S_CONFIG::ScsEmmcHs400Enabled
UINT8 ScsEmmcHs400Enabled
Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode.
Definition: FspsUpd.h:129
FSP_S_TEST_CONFIG::ThreeStrikeCounterDisable
UINT8 ThreeStrikeCounterDisable
Offset 0x0898 - Set Three Strike Counter Disable False (default): Three Strike counter will be increm...
Definition: FspsUpd.h:3031
FSP_S_TEST_CONFIG::CstateLatencyControl0TimeUnit
UINT8 CstateLatencyControl0TimeUnit
Offset 0x0813 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid va...
Definition: FspsUpd.h:2834
FSP_S_CONFIG::ScsEmmcEnabled
UINT8 ScsEmmcEnabled
Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller.
Definition: FspsUpd.h:123
FSP_S_CONFIG::PchPmSlpS0VmRuntimeControl
UINT8 PchPmSlpS0VmRuntimeControl
Offset 0x0152 - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy...
Definition: FspsUpd.h:553
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FsptUpd.h Source File

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FsptUpd.h
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1 /** @file
2
3 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31 **/
32
33 #ifndef __FSPTUPD_H__
34 #define __FSPTUPD_H__
35
36 #include <FspUpd.h>
37
38 #pragma pack(1)
39
40
41 /** Fsp T Core UPD
42 **/
43 typedef struct {
44
45 /** Offset 0x0020
46 **/
47 UINT32 MicrocodeRegionBase;
48
49 /** Offset 0x0024
50 **/
51 UINT32 MicrocodeRegionSize;
52
53 /** Offset 0x0028
54 **/
55 UINT32 CodeRegionBase;
56
57 /** Offset 0x002C
58 **/
59 UINT32 CodeRegionSize;
60
61 /** Offset 0x0030
62 **/
63 UINT8 Reserved[16];
64 } FSPT_CORE_UPD;
65
66 /** Fsp T Configuration
67 **/
68 typedef struct {
69
70 /** Offset 0x0040 - PcdSerialIoUartDebugEnable
71 Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
72 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
73 **/
74 UINT8 PcdSerialIoUartDebugEnable;
75
76 /** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
77 Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
78 Core interface, it cannot be used for debug purpose.
79 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
80 **/
81 UINT8 PcdSerialIoUartNumber;
82
83 /** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT
84 Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is
85 set to UART0.
86 0:default pins, 1:pins muxed with CNV_BRI/RGI
87 **/
88 UINT8 PcdSerialIoUart0PinMuxing;
89
90 /** Offset 0x0043
91 **/
92 UINT8 UnusedUpdSpace0;
93
94 /** Offset 0x0044
95 **/
96 UINT32 PcdSerialIoUartInputClock;
97
98 /** Offset 0x0048 - Pci Express Base Address
99 Base address to be programmed for Pci Express
100 **/
101 UINT64 PcdPciExpressBaseAddress;
102
103 /** Offset 0x0050 - Pci Express Region Length
104 Region Length to be programmed for Pci Express
105 **/
106 UINT32 PcdPciExpressRegionLength;
107
108 /** Offset 0x0054
109 **/
110 UINT8 ReservedFsptUpd1[44];
111 } FSP_T_CONFIG;
112
113 /** Fsp T UPD Configuration
114 **/
115 typedef struct {
116
117 /** Offset 0x0000
118 **/
119 FSP_UPD_HEADER FspUpdHeader;
120
121 /** Offset 0x0020
122 **/
123 FSPT_CORE_UPD FsptCoreUpd;
124
125 /** Offset 0x0040
126 **/
127 FSP_T_CONFIG FsptConfig;
128
129 /** Offset 0x0080
130 **/
131 UINT16 UpdTerminator;
132 } FSPT_UPD;
133
134 #pragma pack()
135
136 #endif
FSP_T_CONFIG::UnusedUpdSpace0
UINT8 UnusedUpdSpace0
Offset 0x0043.
Definition: FsptUpd.h:92
FSPT_CORE_UPD::CodeRegionBase
UINT32 CodeRegionBase
Offset 0x0028.
Definition: FsptUpd.h:55
FSPT_UPD::FsptCoreUpd
FSPT_CORE_UPD FsptCoreUpd
Offset 0x0020.
Definition: FsptUpd.h:123
FSPT_UPD::FsptConfig
FSP_T_CONFIG FsptConfig
Offset 0x0040.
Definition: FsptUpd.h:127
FSP_T_CONFIG::PcdPciExpressRegionLength
UINT32 PcdPciExpressRegionLength
Offset 0x0050 - Pci Express Region Length Region Length to be programmed for Pci Express.
Definition: FsptUpd.h:106
FSP_T_CONFIG::PcdSerialIoUartDebugEnable
UINT8 PcdSerialIoUartDebugEnable
Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializi...
Definition: FsptUpd.h:74
FSP_T_CONFIG::PcdSerialIoUart0PinMuxing
UINT8 PcdSerialIoUart0PinMuxing
Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT Select SerialIo Uart0 pin muxing.
Definition: FsptUpd.h:88
FSPT_CORE_UPD::CodeRegionSize
UINT32 CodeRegionSize
Offset 0x002C.
Definition: FsptUpd.h:59
FspUpd.h
Copyright (c) 2018, Intel Corporation.
FSP_T_CONFIG::PcdPciExpressBaseAddress
UINT64 PcdPciExpressBaseAddress
Offset 0x0048 - Pci Express Base Address Base address to be programmed for Pci Express.
Definition: FsptUpd.h:101
FSP_T_CONFIG::PcdSerialIoUartNumber
UINT8 PcdSerialIoUartNumber
Offset 0x0041 - PcdSerialIoUartNumber - FSPT Select SerialIo Uart Controller for debug.
Definition: FsptUpd.h:81
FSPT_UPD::UpdTerminator
UINT16 UpdTerminator
Offset 0x0080.
Definition: FsptUpd.h:131
FSPT_UPD
Fsp T UPD Configuration.
Definition: FsptUpd.h:115
FSP_T_CONFIG::PcdSerialIoUartInputClock
UINT32 PcdSerialIoUartInputClock
Offset 0x0044.
Definition: FsptUpd.h:96
FSPT_UPD::FspUpdHeader
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FsptUpd.h:119
FSPT_CORE_UPD::MicrocodeRegionSize
UINT32 MicrocodeRegionSize
Offset 0x0024.
Definition: FsptUpd.h:51
FSP_T_CONFIG
Fsp T Configuration.
Definition: FsptUpd.h:68
FSPT_CORE_UPD::MicrocodeRegionBase
UINT32 MicrocodeRegionBase
Offset 0x0020.
Definition: FsptUpd.h:47
FSPT_CORE_UPD
Fsp T Core UPD.
Definition: FsptUpd.h:43
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: GpioConfig.h Source File

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GpioConfig.h
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1 /** @file
2 Header file for GpioConfig structure used by GPIO library.
3
4 @copyright
5 Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 @par Specification Reference:
15 **/
16 #ifndef _GPIO_CONFIG_H_
17 #define _GPIO_CONFIG_H_
18
19 #pragma pack(push, 1)
20
21 ///
22 /// For any GpioPad usage in code use GPIO_PAD type
23 ///
24 typedef UINT32 GPIO_PAD;
25
26
27 ///
28 /// For any GpioGroup usage in code use GPIO_GROUP type
29 ///
30 typedef UINT32 GPIO_GROUP;
31
32 /**
33 GPIO configuration structure used for pin programming.
34 Structure contains fields that can be used to configure pad.
35 **/
36 typedef struct {
37 /**
38 Pad Mode
39 Pad can be set as GPIO or one of its native functions.
40 When in native mode setting Direction (except Inversion), OutputState,
41 InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
42 Refer to definition of GPIO_PAD_MODE.
43 Refer to EDS for each native mode according to the pad.
44 **/
45 UINT32 PadMode : 5;
46 /**
47 Host Software Pad Ownership
48 Set pad to ACPI mode or GPIO Driver Mode.
49 Refer to definition of GPIO_HOSTSW_OWN.
50 **/
51 UINT32 HostSoftPadOwn : 2;
52 /**
53 GPIO Direction
54 Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
55 Refer to definition of GPIO_DIRECTION for supported settings.
56 **/
57 UINT32 Direction : 6;
58 /**
59 Output State
60 Set Pad output value.
61 Refer to definition of GPIO_OUTPUT_STATE for supported settings.
62 This setting takes place when output is enabled.
63 **/
64 UINT32 OutputState : 2;
65 /**
66 GPIO Interrupt Configuration
67 Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
68 This setting is applicable only if GPIO is in GpioMode with input enabled.
69 Refer to definition of GPIO_INT_CONFIG for supported settings.
70 **/
71 UINT32 InterruptConfig : 9;
72 /**
73 GPIO Power Configuration.
74 This setting controls Pad Reset Configuration.
75 Refer to definition of GPIO_RESET_CONFIG for supported settings.
76 **/
77 UINT32 PowerConfig : 8;
78 /**
79 GPIO Electrical Configuration
80 This setting controls pads termination.
81 Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
82 **/
83 UINT32 ElectricalConfig : 9;
84 /**
85 GPIO Lock Configuration
86 This setting controls pads lock.
87 Refer to definition of GPIO_LOCK_CONFIG for supported settings.
88 **/
89 UINT32 LockConfig : 4;
90 /**
91 Additional GPIO configuration
92 Refer to definition of GPIO_OTHER_CONFIG for supported settings.
93 **/
94 UINT32 OtherSettings : 9;
95 UINT32 RsvdBits : 10; ///< Reserved bits for future extension
96 } GPIO_CONFIG;
97
98
99 typedef enum {
100 GpioHardwareDefault = 0x0 ///< Leave setting unmodified
101 } GPIO_HARDWARE_DEFAULT;
102
103 /**
104 GPIO Pad Mode
105 Refer to GPIO documentation on native functions available for certain pad.
106 If GPIO is set to one of NativeX modes then following settings are not applicable
107 and can be skipped:
108 - Interrupt related settings
109 - Host Software Ownership
110 - Output/Input enabling/disabling
111 - Output lock
112 **/
113 typedef enum {
114 GpioPadModeGpio = 0x1,
115 GpioPadModeNative1 = 0x3,
116 GpioPadModeNative2 = 0x5,
117 GpioPadModeNative3 = 0x7,
118 GpioPadModeNative4 = 0x9,
119 GpioPadModeNative5 = 0xB
120 } GPIO_PAD_MODE;
121
122 /**
123 Host Software Pad Ownership modes
124 This setting affects GPIO interrupt status registers. Depending on chosen ownership
125 some GPIO Interrupt status register get updated and other masked.
126 Please refer to EDS for HOSTSW_OWN register description.
127 **/
128 typedef enum {
129 GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
130 /**
131 Set HOST ownership to ACPI.
132 Use this setting if pad is not going to be used by GPIO OS driver.
133 If GPIO is configured to generate SCI/SMI/NMI then this setting must be
134 used for interrupts to work
135 **/
136 GpioHostOwnAcpi = 0x1,
137 /**
138 Set HOST ownership to GPIO Driver mode.
139 Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
140 GPIO OS Driver will be able to control the pad if appropriate entry in
141 ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
142 **/
143 GpioHostOwnGpio = 0x3
144 } GPIO_HOSTSW_OWN;
145
146 ///
147 /// GPIO Direction
148 ///
149 typedef enum {
150 GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
151 GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
152 GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
153 GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
154 GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
155 GpioDirOut = 0x5, ///< Set pad for output only
156 GpioDirNone = 0x7 ///< Disable both output and input
157 } GPIO_DIRECTION;
158
159 /**
160 GPIO Output State
161 This field is relevant only if output is enabled
162 **/
163 typedef enum {
164 GpioOutDefault = 0x0, ///< Leave output value unmodified
165 GpioOutLow = 0x1, ///< Set output to low
166 GpioOutHigh = 0x3 ///< Set output to high
167 } GPIO_OUTPUT_STATE;
168
169 /**
170 GPIO interrupt configuration
171 This setting is applicable only if pad is in GPIO mode and has input enabled.
172 GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
173 and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
174 EDS for details on this settings.
175 Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
176 to describe an interrupt e.g. GpioIntApic | GpioIntLevel
177 If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
178 If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
179 Not all GPIO are capable of generating an SMI or NMI interrupt.
180 When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
181 interrupt cannot be shared and its IRQn number is not configurable.
182 Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
183 If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
184 exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
185 This type of GPIO Driver interrupt doesn't have any additional routing setting
186 required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
187 **/
188
189 typedef enum {
190 GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
191 GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
192 GpioIntNmi = 0x3, ///< Enable NMI interrupt only
193 GpioIntSmi = 0x5, ///< Enable SMI interrupt only
194 GpioIntSci = 0x9, ///< Enable SCI interrupt only
195 GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
196 GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
197 GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
198 GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
199 GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
200 } GPIO_INT_CONFIG;
201
202 #define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
203 #define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
204
205 /**
206 GPIO Power Configuration
207 GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
208 be used to reset certain GPIO settings.
209 Refer to EDS for settings that are controllable by PadRstCfg.
210 **/
211 typedef enum {
212 GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
213 /**
214 Resume Reset (RSMRST)
215 GPP: PadRstCfg = 00b = "Powergood"
216 GPD: PadRstCfg = 11b = "Resume Reset"
217 Pad setting will reset on:
218 - DeepSx transition
219 - G3
220 Pad settings will not reset on:
221 - S3/S4/S5 transition
222 - Warm/Cold/Global reset
223 **/
224 GpioResumeReset = 0x01,
225 /**
226 Host Deep Reset
227 PadRstCfg = 01b = "Deep GPIO Reset"
228 Pad settings will reset on:
229 - Warm/Cold/Global reset
230 - DeepSx transition
231 - G3
232 Pad settings will not reset on:
233 - S3/S4/S5 transition
234 **/
235 GpioHostDeepReset = 0x03,
236 /**
237 Platform Reset (PLTRST)
238 PadRstCfg = 10b = "GPIO Reset"
239 Pad settings will reset on:
240 - S3/S4/S5 transition
241 - Warm/Cold/Global reset
242 - DeepSx transition
243 - G3
244 **/
245 GpioPlatformReset = 0x05,
246 /**
247 Deep Sleep Well Reset (DSW_PWROK)
248 GPP: not applicable
249 GPD: PadRstCfg = 00b = "Powergood"
250 Pad settings will reset on:
251 - G3
252 Pad settings will not reset on:
253 - S3/S4/S5 transition
254 - Warm/Cold/Global reset
255 - DeepSx transition
256 **/
257 GpioDswReset = 0x07
258 } GPIO_RESET_CONFIG;
259
260 /**
261 GPIO Electrical Configuration
262 Configuration options for GPIO termination setting
263 **/
264 typedef enum {
265 GpioTermDefault = 0x0, ///< Leave termination setting unmodified
266 GpioTermNone = 0x1, ///< none
267 GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
268 GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
269 GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
270 GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
271 GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
272 GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
273 GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
274 /**
275 Native function controls pads termination
276 This setting is applicable only to some native modes.
277 Please check EDS to determine which native functionality
278 can control pads termination
279 **/
280 GpioTermNative = 0x1F
281 } GPIO_ELECTRICAL_CONFIG;
282
283 #define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
284
285 /**
286 GPIO LockConfiguration
287 Set GPIO configuration lock and output state lock.
288 GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
289 By default GPIO pads will be locked unless GPIO lib is explicitly
290 informed that certain pad is to be left unlocked.
291 Lock settings reset is in Powergood domain. Care must be taken when using this setting
292 as fields it locks may be reset by a different signal and can be controlled
293 by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
294 functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
295 an already locked pad upon request for reconfiguration
296 **/
297 typedef enum {
298 /**
299 Perform default action
300 - if pad is an GPO, lock configuration but leave output unlocked
301 - if pad is an GPI, lock everything
302 - if pad is in native, lock everything
303 **/
304 GpioLockDefault = 0x0,
305 GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
306 GpioPadConfigLock = 0x1, ///< Lock Pad configuration
307 GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
308 GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
309 GpioPadLock = 0x5 ///< Lock both Pad configuration and output control
310 } GPIO_LOCK_CONFIG;
311
312 #define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
313 #define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
314
315 /**
316 Other GPIO Configuration
317 GPIO_OTHER_CONFIG is used for less often settings and for future extensions
318 Supported settings:
319 - RX raw override to '1' - allows to override input value to '1'
320 This setting is applicable only if in input mode (both in GPIO and native usage).
321 The override takes place at the internal pad state directly from buffer and before the RXINV.
322 **/
323 typedef enum {
324 GpioRxRaw1Default = 0x0, ///< Use default input override value
325 GpioRxRaw1Dis = 0x1, ///< Don't override input
326 GpioRxRaw1En = 0x3 ///< Override input to '1'
327 } GPIO_OTHER_CONFIG;
328
329 #define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
330
331 #pragma pack(pop)
332
333 #endif //_GPIO_CONFIG_H_
GpioPadConfigUnlock
Leave Pad configuration unlocked.
Definition: GpioConfig.h:305
GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:268
GpioResetDefault
Leave value of pad reset unmodified.
Definition: GpioConfig.h:212
GPIO_RESET_CONFIG
GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings.
Definition: GpioConfig.h:211
GPIO_OUTPUT_STATE
GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled.
Definition: GpioConfig.h:163
GPIO_CONFIG
GPIO configuration structure used for pin programming.
Definition: GpioConfig.h:36
GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:195
GpioRxRaw1Dis
Don't override input.
Definition: GpioConfig.h:325
GPIO_HARDWARE_DEFAULT
GPIO_HARDWARE_DEFAULT
Definition: GpioConfig.h:99
GpioTermWpd5K
5kOhm weak pull-down
Definition: GpioConfig.h:267
GpioOutLow
Set output to low.
Definition: GpioConfig.h:165
GpioTermDefault
Leave termination setting unmodified.
Definition: GpioConfig.h:265
GPIO_DIRECTION
GPIO_DIRECTION
GPIO Direction.
Definition: GpioConfig.h:149
GpioDirInInvOut
Set pad for both output and input with inversion.
Definition: GpioConfig.h:152
GpioHardwareDefault
Leave setting unmodified.
Definition: GpioConfig.h:100
GpioLockDefault
Perform default action.
Definition: GpioConfig.h:304
GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:257
GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:155
GpioIntDefault
Leave value of interrupt routing unmodified.
Definition: GpioConfig.h:190
GpioTermWpu2K
2kOhm weak pull-up
Definition: GpioConfig.h:270
GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:136
GpioTermNative
Native function controls pads termination This setting is applicable only to some native modes...
Definition: GpioConfig.h:280
GPIO_OTHER_CONFIG
GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions ...
Definition: GpioConfig.h:323
GpioDirDefault
Leave pad direction setting unmodified.
Definition: GpioConfig.h:150
GPIO_ELECTRICAL_CONFIG
GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Configuration options for GPIO termination setting. ...
Definition: GpioConfig.h:264
GpioTermWpu1K
1kOhm weak pull-up
Definition: GpioConfig.h:269
GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:191
GpioRxRaw1Default
Use default input override value.
Definition: GpioConfig.h:324
GpioResumeReset
Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad se...
Definition: GpioConfig.h:224
GpioOutputStateUnlock
Leave Pad output control unlocked.
Definition: GpioConfig.h:307
GpioPadUnlock
Leave both Pad configuration and output control unlocked.
Definition: GpioConfig.h:308
GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:156
GpioDirInOut
Set pad for both output and input.
Definition: GpioConfig.h:151
GPIO_HOSTSW_OWN
GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.
Definition: GpioConfig.h:128
GPIO_LOCK_CONFIG
GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock.
Definition: GpioConfig.h:297
GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:197
GpioOutHigh
Set output to high.
Definition: GpioConfig.h:166
GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:196
GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:272
GpioPadConfigLock
Lock Pad configuration.
Definition: GpioConfig.h:306
GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:164
GpioIntBothEdge
Set interrupt as both edge triggered.
Definition: GpioConfig.h:199
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:24
GPIO_INT_CONFIG
GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input ena...
Definition: GpioConfig.h:189
GpioPadLock
Lock both Pad configuration and output control.
Definition: GpioConfig.h:309
GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:154
GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on: ...
Definition: GpioConfig.h:245
GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:153
GpioRxRaw1En
Override input to '1'.
Definition: GpioConfig.h:326
GpioIntNmi
Enable NMI interrupt only.
Definition: GpioConfig.h:192
GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:198
GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:194
GpioTermWpu1K2K
1kOhm & 2kOhm weak pull-up
Definition: GpioConfig.h:273
GpioTermNone
none
Definition: GpioConfig.h:266
GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:143
GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:193
GpioTermWpu5K
5kOhm weak pull-up
Definition: GpioConfig.h:271
GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:235
GPIO_PAD_MODE
GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad...
Definition: GpioConfig.h:113
GpioHostOwnDefault
Leave ownership value unmodified.
Definition: GpioConfig.h:129
GPIO_GROUP
UINT32 GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.
Definition: GpioConfig.h:30
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: GpioSampleDef.h Source File

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GpioSampleDef.h
Go to the documentation of this file.
1 /** @file
2 Sample enum definitions for GPIO table.
3
4 @copyright
5 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 @par Specification Reference:
14 **/
15
16 #ifndef __GPIOCONFIG_H__
17 #define __GPIOCONFIG_H__
18 #include <FsptUpd.h>
19 #include <FspmUpd.h>
20 #include <FspsUpd.h>
21
22 /*
23 SKL LP GPIO pins
24 Use below for functions from PCH GPIO Lib which
25 require GpioPad as argument. Encoding used here
26 has all information required by library functions
27 */
28 #define GPIO_SKL_LP_GPP_A0 0x02000000
29 #define GPIO_SKL_LP_GPP_A1 0x02000001
30 #define GPIO_SKL_LP_GPP_A2 0x02000002
31 #define GPIO_SKL_LP_GPP_A3 0x02000003
32 #define GPIO_SKL_LP_GPP_A4 0x02000004
33 #define GPIO_SKL_LP_GPP_A5 0x02000005
34 #define GPIO_SKL_LP_GPP_A6 0x02000006
35 #define GPIO_SKL_LP_GPP_A7 0x02000007
36 #define GPIO_SKL_LP_GPP_A8 0x02000008
37 #define GPIO_SKL_LP_GPP_A9 0x02000009
38 #define GPIO_SKL_LP_GPP_A10 0x0200000A
39 #define GPIO_SKL_LP_GPP_A11 0x0200000B
40 #define GPIO_SKL_LP_GPP_A12 0x0200000C
41 #define GPIO_SKL_LP_GPP_A13 0x0200000D
42 #define GPIO_SKL_LP_GPP_A14 0x0200000E
43 #define GPIO_SKL_LP_GPP_A15 0x0200000F
44 #define GPIO_SKL_LP_GPP_A16 0x02000010
45 #define GPIO_SKL_LP_GPP_A17 0x02000011
46 #define GPIO_SKL_LP_GPP_A18 0x02000012
47 #define GPIO_SKL_LP_GPP_A19 0x02000013
48 #define GPIO_SKL_LP_GPP_A20 0x02000014
49 #define GPIO_SKL_LP_GPP_A21 0x02000015
50 #define GPIO_SKL_LP_GPP_A22 0x02000016
51 #define GPIO_SKL_LP_GPP_A23 0x02000017
52 #define GPIO_SKL_LP_GPP_B0 0x02010000
53 #define GPIO_SKL_LP_GPP_B1 0x02010001
54 #define GPIO_SKL_LP_GPP_B2 0x02010002
55 #define GPIO_SKL_LP_GPP_B3 0x02010003
56 #define GPIO_SKL_LP_GPP_B4 0x02010004
57 #define GPIO_SKL_LP_GPP_B5 0x02010005
58 #define GPIO_SKL_LP_GPP_B6 0x02010006
59 #define GPIO_SKL_LP_GPP_B7 0x02010007
60 #define GPIO_SKL_LP_GPP_B8 0x02010008
61 #define GPIO_SKL_LP_GPP_B9 0x02010009
62 #define GPIO_SKL_LP_GPP_B10 0x0201000A
63 #define GPIO_SKL_LP_GPP_B11 0x0201000B
64 #define GPIO_SKL_LP_GPP_B12 0x0201000C
65 #define GPIO_SKL_LP_GPP_B13 0x0201000D
66 #define GPIO_SKL_LP_GPP_B14 0x0201000E
67 #define GPIO_SKL_LP_GPP_B15 0x0201000F
68 #define GPIO_SKL_LP_GPP_B16 0x02010010
69 #define GPIO_SKL_LP_GPP_B17 0x02010011
70 #define GPIO_SKL_LP_GPP_B18 0x02010012
71 #define GPIO_SKL_LP_GPP_B19 0x02010013
72 #define GPIO_SKL_LP_GPP_B20 0x02010014
73 #define GPIO_SKL_LP_GPP_B21 0x02010015
74 #define GPIO_SKL_LP_GPP_B22 0x02010016
75 #define GPIO_SKL_LP_GPP_B23 0x02010017
76 #define GPIO_SKL_LP_GPP_C0 0x02020000
77 #define GPIO_SKL_LP_GPP_C1 0x02020001
78 #define GPIO_SKL_LP_GPP_C2 0x02020002
79 #define GPIO_SKL_LP_GPP_C3 0x02020003
80 #define GPIO_SKL_LP_GPP_C4 0x02020004
81 #define GPIO_SKL_LP_GPP_C5 0x02020005
82 #define GPIO_SKL_LP_GPP_C6 0x02020006
83 #define GPIO_SKL_LP_GPP_C7 0x02020007
84 #define GPIO_SKL_LP_GPP_C8 0x02020008
85 #define GPIO_SKL_LP_GPP_C9 0x02020009
86 #define GPIO_SKL_LP_GPP_C10 0x0202000A
87 #define GPIO_SKL_LP_GPP_C11 0x0202000B
88 #define GPIO_SKL_LP_GPP_C12 0x0202000C
89 #define GPIO_SKL_LP_GPP_C13 0x0202000D
90 #define GPIO_SKL_LP_GPP_C14 0x0202000E
91 #define GPIO_SKL_LP_GPP_C15 0x0202000F
92 #define GPIO_SKL_LP_GPP_C16 0x02020010
93 #define GPIO_SKL_LP_GPP_C17 0x02020011
94 #define GPIO_SKL_LP_GPP_C18 0x02020012
95 #define GPIO_SKL_LP_GPP_C19 0x02020013
96 #define GPIO_SKL_LP_GPP_C20 0x02020014
97 #define GPIO_SKL_LP_GPP_C21 0x02020015
98 #define GPIO_SKL_LP_GPP_C22 0x02020016
99 #define GPIO_SKL_LP_GPP_C23 0x02020017
100 #define GPIO_SKL_LP_GPP_D0 0x02030000
101 #define GPIO_SKL_LP_GPP_D1 0x02030001
102 #define GPIO_SKL_LP_GPP_D2 0x02030002
103 #define GPIO_SKL_LP_GPP_D3 0x02030003
104 #define GPIO_SKL_LP_GPP_D4 0x02030004
105 #define GPIO_SKL_LP_GPP_D5 0x02030005
106 #define GPIO_SKL_LP_GPP_D6 0x02030006
107 #define GPIO_SKL_LP_GPP_D7 0x02030007
108 #define GPIO_SKL_LP_GPP_D8 0x02030008
109 #define GPIO_SKL_LP_GPP_D9 0x02030009
110 #define GPIO_SKL_LP_GPP_D10 0x0203000A
111 #define GPIO_SKL_LP_GPP_D11 0x0203000B
112 #define GPIO_SKL_LP_GPP_D12 0x0203000C
113 #define GPIO_SKL_LP_GPP_D13 0x0203000D
114 #define GPIO_SKL_LP_GPP_D14 0x0203000E
115 #define GPIO_SKL_LP_GPP_D15 0x0203000F
116 #define GPIO_SKL_LP_GPP_D16 0x02030010
117 #define GPIO_SKL_LP_GPP_D17 0x02030011
118 #define GPIO_SKL_LP_GPP_D18 0x02030012
119 #define GPIO_SKL_LP_GPP_D19 0x02030013
120 #define GPIO_SKL_LP_GPP_D20 0x02030014
121 #define GPIO_SKL_LP_GPP_D21 0x02030015
122 #define GPIO_SKL_LP_GPP_D22 0x02030016
123 #define GPIO_SKL_LP_GPP_D23 0x02030017
124 #define GPIO_SKL_LP_GPP_E0 0x02040000
125 #define GPIO_SKL_LP_GPP_E1 0x02040001
126 #define GPIO_SKL_LP_GPP_E2 0x02040002
127 #define GPIO_SKL_LP_GPP_E3 0x02040003
128 #define GPIO_SKL_LP_GPP_E4 0x02040004
129 #define GPIO_SKL_LP_GPP_E5 0x02040005
130 #define GPIO_SKL_LP_GPP_E6 0x02040006
131 #define GPIO_SKL_LP_GPP_E7 0x02040007
132 #define GPIO_SKL_LP_GPP_E8 0x02040008
133 #define GPIO_SKL_LP_GPP_E9 0x02040009
134 #define GPIO_SKL_LP_GPP_E10 0x0204000A
135 #define GPIO_SKL_LP_GPP_E11 0x0204000B
136 #define GPIO_SKL_LP_GPP_E12 0x0204000C
137 #define GPIO_SKL_LP_GPP_E13 0x0204000D
138 #define GPIO_SKL_LP_GPP_E14 0x0204000E
139 #define GPIO_SKL_LP_GPP_E15 0x0204000F
140 #define GPIO_SKL_LP_GPP_E16 0x02040010
141 #define GPIO_SKL_LP_GPP_E17 0x02040011
142 #define GPIO_SKL_LP_GPP_E18 0x02040012
143 #define GPIO_SKL_LP_GPP_E19 0x02040013
144 #define GPIO_SKL_LP_GPP_E20 0x02040014
145 #define GPIO_SKL_LP_GPP_E21 0x02040015
146 #define GPIO_SKL_LP_GPP_E22 0x02040016
147 #define GPIO_SKL_LP_GPP_E23 0x02040017
148 #define GPIO_SKL_LP_GPP_F0 0x02050000
149 #define GPIO_SKL_LP_GPP_F1 0x02050001
150 #define GPIO_SKL_LP_GPP_F2 0x02050002
151 #define GPIO_SKL_LP_GPP_F3 0x02050003
152 #define GPIO_SKL_LP_GPP_F4 0x02050004
153 #define GPIO_SKL_LP_GPP_F5 0x02050005
154 #define GPIO_SKL_LP_GPP_F6 0x02050006
155 #define GPIO_SKL_LP_GPP_F7 0x02050007
156 #define GPIO_SKL_LP_GPP_F8 0x02050008
157 #define GPIO_SKL_LP_GPP_F9 0x02050009
158 #define GPIO_SKL_LP_GPP_F10 0x0205000A
159 #define GPIO_SKL_LP_GPP_F11 0x0205000B
160 #define GPIO_SKL_LP_GPP_F12 0x0205000C
161 #define GPIO_SKL_LP_GPP_F13 0x0205000D
162 #define GPIO_SKL_LP_GPP_F14 0x0205000E
163 #define GPIO_SKL_LP_GPP_F15 0x0205000F
164 #define GPIO_SKL_LP_GPP_F16 0x02050010
165 #define GPIO_SKL_LP_GPP_F17 0x02050011
166 #define GPIO_SKL_LP_GPP_F18 0x02050012
167 #define GPIO_SKL_LP_GPP_F19 0x02050013
168 #define GPIO_SKL_LP_GPP_F20 0x02050014
169 #define GPIO_SKL_LP_GPP_F21 0x02050015
170 #define GPIO_SKL_LP_GPP_F22 0x02050016
171 #define GPIO_SKL_LP_GPP_F23 0x02050017
172 #define GPIO_SKL_LP_GPP_G0 0x02060000
173 #define GPIO_SKL_LP_GPP_G1 0x02060001
174 #define GPIO_SKL_LP_GPP_G2 0x02060002
175 #define GPIO_SKL_LP_GPP_G3 0x02060003
176 #define GPIO_SKL_LP_GPP_G4 0x02060004
177 #define GPIO_SKL_LP_GPP_G5 0x02060005
178 #define GPIO_SKL_LP_GPP_G6 0x02060006
179 #define GPIO_SKL_LP_GPP_G7 0x02060007
180 #define GPIO_SKL_LP_GPD0 0x02070000
181 #define GPIO_SKL_LP_GPD1 0x02070001
182 #define GPIO_SKL_LP_GPD2 0x02070002
183 #define GPIO_SKL_LP_GPD3 0x02070003
184 #define GPIO_SKL_LP_GPD4 0x02070004
185 #define GPIO_SKL_LP_GPD5 0x02070005
186 #define GPIO_SKL_LP_GPD6 0x02070006
187 #define GPIO_SKL_LP_GPD7 0x02070007
188 #define GPIO_SKL_LP_GPD8 0x02070008
189 #define GPIO_SKL_LP_GPD9 0x02070009
190 #define GPIO_SKL_LP_GPD10 0x0207000A
191 #define GPIO_SKL_LP_GPD11 0x0207000B
192
193 #define END_OF_GPIO_TABLE 0xFFFFFFFF
194
195 //Sample GPIO Table
196
197 static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
198 {
199 //skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
200 //skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
201 //skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
202 //skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
203 //skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
204 //skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
205 //skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
206 //skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
207 {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
208 //skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
209 {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
210 {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
211 {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
212 {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
213 //skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
214 {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
215 {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
216 {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
217 {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
218 {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
219 {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
220 {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
221 {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
222 {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
223 {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
224 {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
225 {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
226 {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
227 {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
228 {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
229 // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
230 // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
231 // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
232 // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
233 // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
234 {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
235 {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
236 {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
237 {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
238 {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
239 {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
240 {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
241 {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
242 {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
243 {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
244 {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
245 {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
246 {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
247 {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
248 {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
249 {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
250 {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
251 {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
252 {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
253 {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
254 {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
255 {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
256 {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
257 {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
258 {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
259 {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
260 {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
261 {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
262 {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
263 {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
264 {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
265 {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
266 {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
267 {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
268 {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
269 {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
270 {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
271 {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
272 {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
273 {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
274 {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
275 {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
276 {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
277 {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
278 {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
279 {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
280 {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
281 {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
282 {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
283 {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
284 {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
285 {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
286 {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
287 {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
288 {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
289 {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
290 {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
291 {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
292 {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
293 {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
294 {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
295 {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
296 {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
297 {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
298 {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
299 {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
300 {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
301 {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
302 {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
303 {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
304 {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
305 {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
306 {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
307 {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
308 {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
309 {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
310 {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
311 {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
312 {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
313 {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
314 {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
315 {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
316 {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
317 {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
318 {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
319 {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
320 {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
321 {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
322 {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
323 {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
324 {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
325 {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
326 {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
327 {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
328 {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
329 {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
330 {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
331 {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
332 {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
333 {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
334 {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
335 {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
336 {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
337 {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
338 {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
339 {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
340 {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
341 {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
342 {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
343 {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
344 {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
345 {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
346 {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
347 {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
348 {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
349 {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
350 {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
351 {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
352 {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
353 {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
354 {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
355 {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
356 {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
357 {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
358 {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
359 {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
360 {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
361 {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
362 {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
363 };
364
365 #endif //_GPIO_CONFIG_H_
GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:268
GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:195
GpioOutLow
Set output to low.
Definition: GpioConfig.h:165
GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:257
GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:155
GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:136
FspsUpd.h
Copyright (c) 2018, Intel Corporation.
GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:191
GpioResumeReset
Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad se...
Definition: GpioConfig.h:224
GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:156
GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:197
GpioOutHigh
Set output to high.
Definition: GpioConfig.h:166
GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:196
GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:272
GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:164
FspmUpd.h
Copyright (c) 2018, Intel Corporation.
GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:154
FsptUpd.h
Copyright (c) 2018, Intel Corporation.
GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on: ...
Definition: GpioConfig.h:245
GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:153
GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:198
GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:194
GpioTermNone
none
Definition: GpioConfig.h:266
GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:143
GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:193
GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:235
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: HobUsageDataHob.h Source File

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HobUsageDataHob.h
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1 /** @file
2 Definitions for Hob Usage data HOB
3
4 @copyright
5 Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 @par Specification Reference:
15 **/
16
17 #ifndef _HOB_USAGE_DATA_HOB_H_
18 #define _HOB_USAGE_DATA_HOB_H_
19
20 extern EFI_GUID gHobUsageDataGuid;
21
22 #pragma pack (push, 1)
23
24 /**
25 Hob Usage Data Hob
26
27 <b>Revision 1:</b>
28 - Initial version.
29 **/
30 typedef struct {
31 EFI_PHYSICAL_ADDRESS EfiMemoryTop;
32 EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
33 EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
34 EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
35 UINTN FreeMemory;
36 } HOB_USAGE_DATA_HOB;
37
38 #pragma pack (pop)
39
40 #endif // _HOB_USAGE_DATA_HOB_H_
HOB_USAGE_DATA_HOB
Hob Usage Data Hob.
Definition: HobUsageDataHob.h:30
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: MemInfoHob.h Source File

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MemInfoHob.h
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1 /** @file
2 This file contains definitions required for creation of
3 Memory S3 Save data, Memory Info data and Memory Platform
4 data hobs.
5
6 @copyright
7 Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials are licensed and made available under
9 the terms and conditions of the BSD License that accompanies this distribution.
10 The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php.
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 @par Specification Reference:
17 **/
18 #ifndef _MEM_INFO_HOB_H_
19 #define _MEM_INFO_HOB_H_
20
21 #include <Uefi/UefiMultiPhase.h>
22 #include <Pi/PiBootMode.h>
23 #include <Pi/PiHob.h>
24
25 #pragma pack (push, 1)
26
27 extern EFI_GUID gSiMemoryS3DataGuid;
28 extern EFI_GUID gSiMemoryInfoDataGuid;
29 extern EFI_GUID gSiMemoryPlatformDataGuid;
30
31 #define MAX_NODE 1
32 #define MAX_CH 2
33 #define MAX_DIMM 2
34
35 ///
36 /// Host reset states from MRC.
37 ///
38 #define WARM_BOOT 2
39
40 #define R_MC_CHNL_RANK_PRESENT 0x7C
41 #define B_RANK0_PRS BIT0
42 #define B_RANK1_PRS BIT1
43 #define B_RANK2_PRS BIT4
44 #define B_RANK3_PRS BIT5
45
46 ///
47 /// Defines taken from MRC so avoid having to include MrcInterface.h
48 ///
49
50 //
51 // Matches MAX_SPD_SAVE define in MRC
52 //
53 #ifndef MAX_SPD_SAVE
54 #define MAX_SPD_SAVE 29
55 #endif
56
57 //
58 // MRC version description.
59 //
60 typedef struct {
61 UINT8 Major; ///< Major version number
62 UINT8 Minor; ///< Minor version number
63 UINT8 Rev; ///< Revision number
64 UINT8 Build; ///< Build number
65 } SiMrcVersion;
66
67 //
68 // Matches MrcChannelSts enum in MRC
69 //
70 #ifndef CHANNEL_NOT_PRESENT
71 #define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
72 #endif
73 #ifndef CHANNEL_DISABLED
74 #define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
75 #endif
76 #ifndef CHANNEL_PRESENT
77 #define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
78 #endif
79
80 //
81 // Matches MrcDimmSts enum in MRC
82 //
83 #ifndef DIMM_ENABLED
84 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
85 #endif
86 #ifndef DIMM_DISABLED
87 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
88 #endif
89 #ifndef DIMM_PRESENT
90 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
91 #endif
92 #ifndef DIMM_NOT_PRESENT
93 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
94 #endif
95
96 //
97 // Matches MrcBootMode enum in MRC
98 //
99 #ifndef bmCold
100 #define bmCold 0 // Cold boot
101 #endif
102 #ifndef bmWarm
103 #define bmWarm 1 // Warm boot
104 #endif
105 #ifndef bmS3
106 #define bmS3 2 // S3 resume
107 #endif
108 #ifndef bmFast
109 #define bmFast 3 // Fast boot
110 #endif
111
112 //
113 // Matches MrcDdrType enum in MRC
114 //
115 #ifndef MRC_DDR_TYPE_DDR4
116 #define MRC_DDR_TYPE_DDR4 0
117 #endif
118 #ifndef MRC_DDR_TYPE_DDR3
119 #define MRC_DDR_TYPE_DDR3 1
120 #endif
121 #ifndef MRC_DDR_TYPE_LPDDR3
122 #define MRC_DDR_TYPE_LPDDR3 2
123 #endif
124 #ifndef CPU_CFL//CNL
125 #ifndef MRC_DDR_TYPE_LPDDR4
126 #define MRC_DDR_TYPE_LPDDR4 3
127 #endif
128 #else//CFL
129 #ifndef MRC_DDR_TYPE_UNKNOWN
130 #define MRC_DDR_TYPE_UNKNOWN 3
131 #endif
132 #endif//CPU_CFL-endif
133
134 #define MAX_PROFILE_NUM 4 // number of memory profiles supported
135 #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
136
137 //
138 // DIMM timings
139 //
140 typedef struct {
141 UINT32 tCK; ///< Memory cycle time, in femtoseconds.
142 UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
143 UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
144 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
145 UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
146 UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
147 UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
148 UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
149 UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
150 UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
151 UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
152 UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
153 UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
154 UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
155 UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
156 UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
157 UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
158 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
159 UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
160 UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
161 UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
162 UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
163 } MRC_CH_TIMING;
164
165 typedef struct {
166 UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
167 UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
168 UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
169 UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
170 } MRC_TA_TIMING;
171
172 ///
173 /// Memory SMBIOS & OC Memory Data Hob
174 ///
175 typedef struct {
176 UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
177 UINT8 DimmId;
178 UINT32 DimmCapacity; ///< DIMM size in MBytes.
179 UINT16 MfgId;
180 UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
181 UINT8 RankInDimm; ///< The number of ranks in this DIMM.
182 UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
183 UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
184 UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
185 UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
186 UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
187 } DIMM_INFO;
188
189 typedef struct {
190 UINT8 Status; ///< Indicates whether this channel should be used.
191 UINT8 ChannelId;
192 UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
193 MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
194 DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
195 MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
196 MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
197 MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
198 MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
199 } CHANNEL_INFO;
200
201 typedef struct {
202 UINT8 Status; ///< Indicates whether this controller should be used.
203 UINT16 DeviceId; ///< The PCI device id of this memory controller.
204 UINT8 RevisionId; ///< The PCI revision id of this memory controller.
205 UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
206 CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
207 MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings
208 MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings
209 MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings
210 MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
211 } CONTROLLER_INFO;
212
213 typedef struct {
214 UINT8 Revision;
215 UINT16 DataWidth; ///< Data width, in bits, of this memory device
216 /** As defined in SMBIOS 3.0 spec
217 Section 7.18.2 and Table 75
218 **/
219 UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
220 UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
221 UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
222 /** As defined in SMBIOS 3.0 spec
223 Section 7.17.3 and Table 72
224 **/
225 UINT8 ErrorCorrectionType;
226
227 SiMrcVersion Version;
228 BOOLEAN EccSupport;
229 UINT8 MemoryProfile;
230 UINT32 TotalPhysicalMemorySize;
231 UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
232 UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
233 UINT8 Ratio;
234 UINT8 RefClk;
235 UINT32 VddVoltage[MAX_PROFILE_NUM];
236 CONTROLLER_INFO Controller[MAX_NODE];
237 } MEMORY_INFO_DATA_HOB;
238
239 /**
240 Memory Platform Data Hob
241
242 <b>Revision 1:</b>
243 - Initial version.
244 <b>Revision 2:</b>
245 - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
246 **/
247 typedef struct {
248 UINT8 Revision;
249 UINT8 Reserved[3];
250 UINT32 BootMode;
251 UINT32 TsegSize;
252 UINT32 TsegBase;
253 UINT32 PrmrrSize;
254 UINT32 PrmrrBase;
255 UINT32 GttBase;
256 UINT32 MmioSize;
257 UINT32 PciEBaseAddress;
258 #ifdef CPU_CFL
259 UINT32 GdxcIotBase;
260 UINT32 GdxcIotSize;
261 UINT32 GdxcMotBase;
262 UINT32 GdxcMotSize;
263 #endif //CPU_CFL
264 } MEMORY_PLATFORM_DATA;
265
266 typedef struct {
267 EFI_HOB_GUID_TYPE EfiHobGuidType;
268 MEMORY_PLATFORM_DATA Data;
269 UINT8 *Buffer;
270 } MEMORY_PLATFORM_DATA_HOB;
271
272 #pragma pack (pop)
273
274 #endif // _MEM_INFO_HOB_H_
DIMM_INFO::Status
UINT8 Status
See MrcDimmStatus for the definition of this field.
Definition: MemInfoHob.h:176
DIMM_INFO::SpdDramDeviceType
UINT8 SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:182
DIMM_INFO::SpdModuleMemoryBusWidth
UINT8 SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:184
DIMM_INFO::DimmCapacity
UINT32 DimmCapacity
DIMM size in MBytes.
Definition: MemInfoHob.h:178
DIMM_INFO
Memory SMBIOS & OC Memory Data Hob.
Definition: MemInfoHob.h:175
MEMORY_PLATFORM_DATA
Memory Platform Data Hob.
Definition: MemInfoHob.h:247
DIMM_INFO::SpdModuleType
UINT8 SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:183
MAX_SPD_SAVE
#define MAX_SPD_SAVE
Defines taken from MRC so avoid having to include MrcInterface.h.
Definition: MemInfoHob.h:54
DIMM_INFO::Speed
UINT16 Speed
The maximum capable speed of the device, in MHz.
Definition: MemInfoHob.h:186
DIMM_INFO::RankInDimm
UINT8 RankInDimm
The number of ranks in this DIMM.
Definition: MemInfoHob.h:181
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SmbiosCacheInfoHob.h Source File

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SmbiosCacheInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for SMBIOS Cache Info HOB
3
4 @copyright
5 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
6
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License which accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 System Management BIOS (SMBIOS) Reference Specification v3.1.0
16 dated 2016-Nov-16 (DSP0134)
17 http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
18 **/
19
20 #ifndef _SMBIOS_CACHE_INFO_HOB_H_
21 #define _SMBIOS_CACHE_INFO_HOB_H_
22
23 #include <Uefi.h>
24 #include <Pi/PiHob.h>
25
26 #pragma pack(1)
27 ///
28 /// SMBIOS Cache Info HOB Structure
29 ///
30 typedef struct {
31 UINT16 ProcessorSocketNumber;
32 UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
33 UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
34 UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
35 UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
36 UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
37 UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
38 UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
39 UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
40 UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
41 UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
42 UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
43 //
44 // Add for smbios 3.1.0
45 //
46 UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
47 UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
48 /**
49 String Buffer - each string terminated by NULL "0x00"
50 String buffer terminated by double NULL "0x0000"
51 **/
52 } SMBIOS_CACHE_INFO;
53 #pragma pack()
54
55 #endif // _SMBIOS_CACHE_INFO_HOB_H_
SMBIOS_CACHE_INFO::CurrentSramType
UINT16 CurrentSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
Definition: SmbiosCacheInfoHob.h:38
SMBIOS_CACHE_INFO::SupportedSramType
UINT16 SupportedSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
Definition: SmbiosCacheInfoHob.h:37
SMBIOS_CACHE_INFO::Associativity
UINT8 Associativity
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5.
Definition: SmbiosCacheInfoHob.h:42
SMBIOS_CACHE_INFO::SocketDesignationStrIndex
UINT8 SocketDesignationStrIndex
String Index in the string Buffer. Example "L1-CACHE".
Definition: SmbiosCacheInfoHob.h:33
SMBIOS_CACHE_INFO::CacheSpeed
UINT8 CacheSpeed
Cache Speed in nanoseconds. 0 if speed is unknown.
Definition: SmbiosCacheInfoHob.h:39
SMBIOS_CACHE_INFO::SystemCacheType
UINT8 SystemCacheType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4.
Definition: SmbiosCacheInfoHob.h:41
SMBIOS_CACHE_INFO::ErrorCorrectionType
UINT8 ErrorCorrectionType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3.
Definition: SmbiosCacheInfoHob.h:40
SMBIOS_CACHE_INFO
SMBIOS Cache Info HOB Structure.
Definition: SmbiosCacheInfoHob.h:30
SMBIOS_CACHE_INFO::MaxCacheSize
UINT16 MaxCacheSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:35
SMBIOS_CACHE_INFO::InstalledSize
UINT16 InstalledSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:36
SMBIOS_CACHE_INFO::InstalledSize2
UINT32 InstalledSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:47
SMBIOS_CACHE_INFO::NumberOfCacheLevels
UINT16 NumberOfCacheLevels
Based on Number of Cache Types L1/L2/L3.
Definition: SmbiosCacheInfoHob.h:32
SMBIOS_CACHE_INFO::MaximumCacheSize2
UINT32 MaximumCacheSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:46
SMBIOS_CACHE_INFO::CacheConfiguration
UINT16 CacheConfiguration
Format defined in SMBIOS Spec v3.1 Section7.8 Table36.
Definition: SmbiosCacheInfoHob.h:34
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: SmbiosProcessorInfoHob.h Source File

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SmbiosProcessorInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for SMBIOS Processor Info HOB
3
4 @copyright
5 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 System Management BIOS (SMBIOS) Reference Specification v3.1.0
15 dated 2016-Nov-16 (DSP0134)
16 http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
17 **/
18
19 #ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
20 #define _SMBIOS_PROCESSOR_INFO_HOB_H_
21
22 #include <Uefi.h>
23 #include <Pi/PiHob.h>
24
25 #pragma pack(1)
26 ///
27 /// SMBIOS Processor Info HOB Structure
28 ///
29 typedef struct {
30 UINT16 TotalNumberOfSockets;
31 UINT16 CurrentSocketNumber;
32 UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1
33 /** This info is used for both ProcessorFamily and ProcessorFamily2 fields
34 See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2
35 **/
36 UINT16 ProcessorFamily;
37 UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
38 UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3
39 UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
40 UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4
41 UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
42 UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
43 UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21
44 UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5
45 /** This info is used for both CoreCount & CoreCount2 fields
46 See detailed description in SMBIOS Spec v3.1 Section 7.5.6
47 **/
48 UINT16 CoreCount;
49 /** This info is used for both CoreEnabled & CoreEnabled2 fields
50 See detailed description in SMBIOS Spec v3.1 Section 7.5.7
51 **/
52 UINT16 EnabledCoreCount;
53 /** This info is used for both ThreadCount & ThreadCount2 fields
54 See detailed description in SMBIOS Spec v3.1 Section 7.5.8
55 **/
56 UINT16 ThreadCount;
57 UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9
58 /**
59 String Buffer - each string terminated by NULL "0x00"
60 String buffer terminated by double NULL "0x0000"
61 **/
62 } SMBIOS_PROCESSOR_INFO;
63 #pragma pack()
64
65 #endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
SMBIOS_PROCESSOR_INFO::CoreCount
UINT16 CoreCount
This info is used for both CoreCount & CoreCount2 fields See detailed description in SMBIOS Spec v3...
Definition: SmbiosProcessorInfoHob.h:48
SMBIOS_PROCESSOR_INFO::ProcessorManufacturerStrIndex
UINT8 ProcessorManufacturerStrIndex
Index of the String in the String Buffer.
Definition: SmbiosProcessorInfoHob.h:37
SMBIOS_PROCESSOR_INFO::EnabledCoreCount
UINT16 EnabledCoreCount
This info is used for both CoreEnabled & CoreEnabled2 fields See detailed description in SMBIOS Spec ...
Definition: SmbiosProcessorInfoHob.h:52
SMBIOS_PROCESSOR_INFO::Status
UINT8 Status
Format defined in the SMBIOS Spec v3.1 Table 21.
Definition: SmbiosProcessorInfoHob.h:43
SMBIOS_PROCESSOR_INFO::Voltage
UINT8 Voltage
Format defined in SMBIOS Spec v3.1 Section 7.5.4.
Definition: SmbiosProcessorInfoHob.h:40
SMBIOS_PROCESSOR_INFO::ProcessorType
UINT8 ProcessorType
ENUM defined in SMBIOS Spec v3.1 Section 7.5.1.
Definition: SmbiosProcessorInfoHob.h:32
SMBIOS_PROCESSOR_INFO::ProcessorVersionStrIndex
UINT8 ProcessorVersionStrIndex
Index of the String in the String Buffer.
Definition: SmbiosProcessorInfoHob.h:39
SMBIOS_PROCESSOR_INFO::ProcessorFamily
UINT16 ProcessorFamily
This info is used for both ProcessorFamily and ProcessorFamily2 fields See ENUM defined in SMBIOS Spe...
Definition: SmbiosProcessorInfoHob.h:36
SMBIOS_PROCESSOR_INFO::ProcessorUpgrade
UINT8 ProcessorUpgrade
ENUM defined in SMBIOS Spec v3.1 Section 7.5.5.
Definition: SmbiosProcessorInfoHob.h:44
SMBIOS_PROCESSOR_INFO::ThreadCount
UINT16 ThreadCount
This info is used for both ThreadCount & ThreadCount2 fields See detailed description in SMBIOS Spec ...
Definition: SmbiosProcessorInfoHob.h:56
SMBIOS_PROCESSOR_INFO::CurrentSpeedInMHz
UINT16 CurrentSpeedInMHz
Snapshot of current processor speed during boot.
Definition: SmbiosProcessorInfoHob.h:42
SMBIOS_PROCESSOR_INFO::ProcessorId
UINT64 ProcessorId
ENUM defined in SMBIOS Spec v3.1 Section 7.5.3.
Definition: SmbiosProcessorInfoHob.h:38
SMBIOS_PROCESSOR_INFO
SMBIOS Processor Info HOB Structure.
Definition: SmbiosProcessorInfoHob.h:29
SMBIOS_PROCESSOR_INFO::ProcessorCharacteristics
UINT16 ProcessorCharacteristics
Format defined in SMBIOS Spec v3.1 Section 7.5.9.
Definition: SmbiosProcessorInfoHob.h:57
SMBIOS_PROCESSOR_INFO::ExternalClockInMHz
UINT16 ExternalClockInMHz
External Clock Frequency. Set to 0 if unknown.
Definition: SmbiosProcessorInfoHob.h:41
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Include
Include Directory Reference
Directory dependency graph for Include:

Files

file | FirmwareVersionInfoHob.h [code]
Header file for Firmware Version Information.
file | FspInfoHob.h [code]
Header file for FSP Information HOB.
file | FspmUpd.h [code]
Copyright (c) 2018, Intel Corporation.
file | FspsUpd.h [code]
Copyright (c) 2018, Intel Corporation.
file | FsptUpd.h [code]
Copyright (c) 2018, Intel Corporation.
file | FspUpd.h [code]
Copyright (c) 2018, Intel Corporation.
file | GpioConfig.h [code]
Header file for GpioConfig structure used by GPIO library.
file | GpioSampleDef.h [code]
Sample enum definitions for GPIO table.
file | HobUsageDataHob.h [code]
Definitions for Hob Usage data HOB.
file | MemInfoHob.h [code]
This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs.
file | SmbiosCacheInfoHob.h [code]
Header file for SMBIOS Cache Info HOB.
file | SmbiosProcessorInfoHob.h [code]
Header file for SMBIOS Processor Info HOB.


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

1 /*! Invisible class because of truncation */
2 class Invisible { };
3
4 /*! Truncated class, inheritance relation is hidden */
5 class Truncated : public Invisible { };
6
7 /* Class not documented with doxygen comments */
8 class Undocumented { };
9
10 /*! Class that is inherited using public inheritance */
11 class PublicBase : public Truncated { };
12
13 /*! A template class */
14 template<class T> class Templ { };
15
16 /*! Class that is inherited using protected inheritance */
17 class ProtectedBase { };
18
19 /*! Class that is inherited using private inheritance */
20 class PrivateBase { };
21
22 /*! Class that is used by the Inherited class */
23 class Used { };
24
25 /*! Super class that inherits a number of other classes */
26 class Inherited : public PublicBase,
27 protected ProtectedBase,
28 private PrivateBase,
29 public Undocumented,
30 public Templ<int>
31 {
32 private:
33 Used *m_usedClass;
34 };

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a gray border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Related Pages

Related Pages
Here is a list of all related documentation pages:
FSP OVERVIEW

FSP Overview

2.1 Technical Overview

The Intel® Firmware Support Package (FSP) provides chipset and processor initialization in a format that can easily be incorporated into many existing boot loaders
FSP INTEGRATION

3 FSP Integration

FSP PORTING RECOMMENDATION

4 FSP Porting Recommendation

Here listed some notes or recommendation when porting with FSP
UPD PORTING GUIDE

5 UPD porting guide

FSP OUTPUT

6 FSP Output

The FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon
FSP POSTCODE

7 FSP PostCode

The FSP outputs 16 bit postcode to indicate which API and in which module the execution is happening
Todo List
Deprecated List
Generated on Wed Aug 22 2018 17:48:56 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

AUDIO_AZALIA_VERB_TABLE Member List

This is the complete list of members for AUDIO_AZALIA_VERB_TABLE, including all inherited members.

Data | AUDIO_AZALIA_VERB_TABLE
Header | AUDIO_AZALIA_VERB_TABLE
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

AZALIA_HEADER Member List

This is the complete list of members for AZALIA_HEADER, including all inherited members.

DataDwords | AZALIA_HEADER
DeviceId | AZALIA_HEADER
Reserved | AZALIA_HEADER
RevisionId | AZALIA_HEADER
SdiNum | AZALIA_HEADER
VendorId | AZALIA_HEADER
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

CHIPSET_INIT_INFO Member List

This is the complete list of members for CHIPSET_INIT_INFO, including all inherited members.

BiosChipInitCrc | CHIPSET_INIT_INFO
MeChipInitCrc | CHIPSET_INIT_INFO
Revision | CHIPSET_INIT_INFO
Rsvd | CHIPSET_INIT_INFO
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

DIMM_INFO Member List

This is the complete list of members for DIMM_INFO, including all inherited members.

DimmCapacity | DIMM_INFO
ModulePartNum | DIMM_INFO
RankInDimm | DIMM_INFO
SpdDramDeviceType | DIMM_INFO
SpdModuleMemoryBusWidth | DIMM_INFO
SpdModuleType | DIMM_INFO
SpdSave | DIMM_INFO
Speed | DIMM_INFO
Status | DIMM_INFO
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FIRMWARE_VERSION Member List

This is the complete list of members for FIRMWARE_VERSION, including all inherited members.

Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FIRMWARE_VERSION_INFO Member List

This is the complete list of members for FIRMWARE_VERSION_INFO, including all inherited members.

ComponentNameIndex | FIRMWARE_VERSION_INFO
Version | FIRMWARE_VERSION_INFO
VersionStringIndex | FIRMWARE_VERSION_INFO
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FIRMWARE_VERSION_INFO_HOB Member List

This is the complete list of members for FIRMWARE_VERSION_INFO_HOB, including all inherited members.

Count | FIRMWARE_VERSION_INFO_HOB
Header | FIRMWARE_VERSION_INFO_HOB
SmbiosData | FIRMWARE_VERSION_INFO_HOB
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by doxygen 1.8.10


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_M_CONFIG Member List

This is the complete list of members for FSP_M_CONFIG, including all inherited members.

ActEnergyCh0Dimm0 | FSP_M_CONFIG
ActEnergyCh0Dimm1 | FSP_M_CONFIG
ActEnergyCh1Dimm0 | FSP_M_CONFIG
ActEnergyCh1Dimm1 | FSP_M_CONFIG
ActiveCoreCount | FSP_M_CONFIG
ALIASCHK | FSP_M_CONFIG
ApertureSize | FSP_M_CONFIG
ApStartupBase | FSP_M_CONFIG
Avx2RatioOffset | FSP_M_CONFIG
Avx3RatioOffset | FSP_M_CONFIG
BclkAdaptiveVoltage | FSP_M_CONFIG
BClkFrequency | FSP_M_CONFIG
BiosAcmBase | FSP_M_CONFIG
BiosAcmSize | FSP_M_CONFIG
BiosGuard | FSP_M_CONFIG
BiosGuardToolsInterface | FSP_M_CONFIG
BistOnReset | FSP_M_CONFIG
BootFrequency | FSP_M_CONFIG
CaVrefConfig | FSP_M_CONFIG
ChHashEnable | FSP_M_CONFIG
ChHashInterleaveBit | FSP_M_CONFIG
ChHashMask | FSP_M_CONFIG
CkeRankMapping | FSP_M_CONFIG
CleanMemory | FSP_M_CONFIG
CMDDSEQ | FSP_M_CONFIG
CMDNORM | FSP_M_CONFIG
CmdRanksTerminated | FSP_M_CONFIG
CMDSR | FSP_M_CONFIG
CMDVC | FSP_M_CONFIG
CoreMaxOcRatio | FSP_M_CONFIG
CorePllVoltageOffset | FSP_M_CONFIG
CoreVoltageAdaptive | FSP_M_CONFIG
CoreVoltageMode | FSP_M_CONFIG
CoreVoltageOffset | FSP_M_CONFIG
CoreVoltageOverride | FSP_M_CONFIG
CpuRatio | FSP_M_CONFIG
CpuTraceHubMemReg0Size | FSP_M_CONFIG
CpuTraceHubMemReg1Size | FSP_M_CONFIG
CpuTraceHubMode | FSP_M_CONFIG
DciUsb3TypecUfpDbg | FSP_M_CONFIG
Ddr4DdpSharedClock | FSP_M_CONFIG
Ddr4DdpSharedZq | FSP_M_CONFIG
Ddr4MixedUDimm2DpcLimit | FSP_M_CONFIG
DdrFreqLimit | FSP_M_CONFIG
DdrThermalSensor | FSP_M_CONFIG
DIMMODTT | FSP_M_CONFIG
DIMMRONT | FSP_M_CONFIG
DisableDimmChannel0 | FSP_M_CONFIG
DisableDimmChannel1 | FSP_M_CONFIG
DisableMtrrProgram | FSP_M_CONFIG
DllBwEn0 | FSP_M_CONFIG
DllBwEn1 | FSP_M_CONFIG
DllBwEn2 | FSP_M_CONFIG
DllBwEn3 | FSP_M_CONFIG
DmiDeEmphasis | FSP_M_CONFIG
DmiGen3EndPointHint | FSP_M_CONFIG
DmiGen3EndPointPreset | FSP_M_CONFIG
DmiGen3ProgramStaticEq | FSP_M_CONFIG
DmiGen3RootPortPreset | FSP_M_CONFIG
DmiGen3RxCtlePeaking | FSP_M_CONFIG
DqByteMapCh0 | FSP_M_CONFIG
DqByteMapCh1 | FSP_M_CONFIG
DqPinsInterleaved | FSP_M_CONFIG
DqsMapCpu2DramCh0 | FSP_M_CONFIG
DqsMapCpu2DramCh1 | FSP_M_CONFIG
DualDimmPerChannelBoardType | FSP_M_CONFIG
EccSupport | FSP_M_CONFIG
ECT | FSP_M_CONFIG
EnableC6Dram | FSP_M_CONFIG
EnableCltm | FSP_M_CONFIG
EnableExtts | FSP_M_CONFIG
EnableOltm | FSP_M_CONFIG
EnablePwrDn | FSP_M_CONFIG
EnablePwrDnLpddr | FSP_M_CONFIG
EnableSgx | FSP_M_CONFIG
EnBER | FSP_M_CONFIG
EnCmdRate | FSP_M_CONFIG
EnergyScaleFact | FSP_M_CONFIG
EnhancedInterleave | FSP_M_CONFIG
EpgEnable | FSP_M_CONFIG
ERDMPRTC2D | FSP_M_CONFIG
ERDTC2D | FSP_M_CONFIG
EWRDSEQ | FSP_M_CONFIG
EWRTC2D | FSP_M_CONFIG
ExitOnFailure | FSP_M_CONFIG
FClkFrequency | FSP_M_CONFIG
FivrEfficiency | FSP_M_CONFIG
FivrFaults | FSP_M_CONFIG
ForceOltmOrRefresh2x | FSP_M_CONFIG
FreqSaGvLow | FSP_M_CONFIG
FreqSaGvMid | FSP_M_CONFIG
GdxcEnable | FSP_M_CONFIG
GdxcIotSize | FSP_M_CONFIG
GdxcMotSize | FSP_M_CONFIG
GmAdr | FSP_M_CONFIG
GtExtraTurboVoltage | FSP_M_CONFIG
GtMaxOcRatio | FSP_M_CONFIG
GtPllVoltageOffset | FSP_M_CONFIG
GtPsmiSupport | FSP_M_CONFIG
GttMmAdr | FSP_M_CONFIG
GttSize | FSP_M_CONFIG
GtusExtraTurboVoltage | FSP_M_CONFIG
GtusMaxOcRatio | FSP_M_CONFIG
GtusVoltageMode | FSP_M_CONFIG
GtusVoltageOffset | FSP_M_CONFIG
GtusVoltageOverride | FSP_M_CONFIG
GtVoltageMode | FSP_M_CONFIG
GtVoltageOffset | FSP_M_CONFIG
GtVoltageOverride | FSP_M_CONFIG
Heci1BarAddress | FSP_M_CONFIG
Heci2BarAddress | FSP_M_CONFIG
Heci3BarAddress | FSP_M_CONFIG
HeciTimeouts | FSP_M_CONFIG
HobBufferSize | FSP_M_CONFIG
HotBudgetCh0Dimm0 | FSP_M_CONFIG
HotBudgetCh0Dimm1 | FSP_M_CONFIG
HotBudgetCh1Dimm0 | FSP_M_CONFIG
HotBudgetCh1Dimm1 | FSP_M_CONFIG
HotThresholdCh0Dimm0 | FSP_M_CONFIG
HotThresholdCh0Dimm1 | FSP_M_CONFIG
HotThresholdCh1Dimm0 | FSP_M_CONFIG
HotThresholdCh1Dimm1 | FSP_M_CONFIG
HyperThreading | FSP_M_CONFIG
Idd3n | FSP_M_CONFIG
Idd3p | FSP_M_CONFIG
IdleEnergyCh0Dimm0 | FSP_M_CONFIG
IdleEnergyCh0Dimm1 | FSP_M_CONFIG
IdleEnergyCh1Dimm0 | FSP_M_CONFIG
IdleEnergyCh1Dimm1 | FSP_M_CONFIG
IedSize | FSP_M_CONFIG
IgdDvmt50PreAlloc | FSP_M_CONFIG
ImrRpSelection | FSP_M_CONFIG
InitPcieAspmAfterOprom | FSP_M_CONFIG
InternalGfx | FSP_M_CONFIG
IsTPMPresence | FSP_M_CONFIG
IsvtIoPort | FSP_M_CONFIG
JtagC10PowerGateDisable | FSP_M_CONFIG
JWRL | FSP_M_CONFIG
LCT | FSP_M_CONFIG
LpDdrDqDqsReTraining | FSP_M_CONFIG
McPllVoltageOffset | FSP_M_CONFIG
MemorySpdDataLen | FSP_M_CONFIG
MemorySpdPtr00 | FSP_M_CONFIG
MemorySpdPtr01 | FSP_M_CONFIG
MemorySpdPtr10 | FSP_M_CONFIG
MemorySpdPtr11 | FSP_M_CONFIG
MemoryTrace | FSP_M_CONFIG
MemTestOnWarmBoot | FSP_M_CONFIG
MEMTST | FSP_M_CONFIG
MmioSize | FSP_M_CONFIG
MmioSizeAdjustment | FSP_M_CONFIG
MrcFastBoot | FSP_M_CONFIG
MrcSafeConfig | FSP_M_CONFIG
NModeSupport | FSP_M_CONFIG
OcLock | FSP_M_CONFIG
OcSupport | FSP_M_CONFIG
OddRatioMode | FSP_M_CONFIG
PcdDebugInterfaceFlags | FSP_M_CONFIG
PcdIsaSerialUartBase | FSP_M_CONFIG
PcdSerialDebugBaudRate | FSP_M_CONFIG
PcdSerialDebugLevel | FSP_M_CONFIG
PcdSerialIoUartNumber | FSP_M_CONFIG
PchHdaEnable | FSP_M_CONFIG
PchIshEnable | FSP_M_CONFIG
PchLpcEnhancePort8xhDecoding | FSP_M_CONFIG
PchNumRsvdSmbusAddresses | FSP_M_CONFIG
PchPcieHsioRxSetCtle | FSP_M_CONFIG
PchPcieHsioRxSetCtleEnable | FSP_M_CONFIG
PchPcieHsioTxGen1DeEmph | FSP_M_CONFIG
PchPcieHsioTxGen1DeEmphEnable | FSP_M_CONFIG
PchPcieHsioTxGen1DownscaleAmp | FSP_M_CONFIG
PchPcieHsioTxGen1DownscaleAmpEnable | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph3p5 | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph3p5Enable | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph6p0 | FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph6p0Enable | FSP_M_CONFIG
PchPcieHsioTxGen2DownscaleAmp | FSP_M_CONFIG
PchPcieHsioTxGen2DownscaleAmpEnable | FSP_M_CONFIG
PchPcieHsioTxGen3DownscaleAmp | FSP_M_CONFIG
PchPcieHsioTxGen3DownscaleAmpEnable | FSP_M_CONFIG
PchPort80Route | FSP_M_CONFIG
PchPreMemRsvd | FSP_M_CONFIG
PchSataHsioRxGen1EqBoostMag | FSP_M_CONFIG
PchSataHsioRxGen1EqBoostMagEnable | FSP_M_CONFIG
PchSataHsioRxGen2EqBoostMag | FSP_M_CONFIG
PchSataHsioRxGen2EqBoostMagEnable | FSP_M_CONFIG
PchSataHsioRxGen3EqBoostMag | FSP_M_CONFIG
PchSataHsioRxGen3EqBoostMagEnable | FSP_M_CONFIG
PchSataHsioTxGen1DeEmph | FSP_M_CONFIG
PchSataHsioTxGen1DeEmphEnable | FSP_M_CONFIG
PchSataHsioTxGen1DownscaleAmp | FSP_M_CONFIG
PchSataHsioTxGen1DownscaleAmpEnable | FSP_M_CONFIG
PchSataHsioTxGen2DeEmph | FSP_M_CONFIG
PchSataHsioTxGen2DeEmphEnable | FSP_M_CONFIG
PchSataHsioTxGen2DownscaleAmp | FSP_M_CONFIG
PchSataHsioTxGen2DownscaleAmpEnable | FSP_M_CONFIG
PchSataHsioTxGen3DeEmph | FSP_M_CONFIG
PchSataHsioTxGen3DeEmphEnable | FSP_M_CONFIG
PchSataHsioTxGen3DownscaleAmp | FSP_M_CONFIG
PchSataHsioTxGen3DownscaleAmpEnable | FSP_M_CONFIG
PchSmbAlertEnable | FSP_M_CONFIG
PchSmbusIoBase | FSP_M_CONFIG
PchTraceHubMemReg0Size | FSP_M_CONFIG
PchTraceHubMemReg1Size | FSP_M_CONFIG
PchTraceHubMode | FSP_M_CONFIG
PcieImrEnabled | FSP_M_CONFIG
PcieImrSize | FSP_M_CONFIG
PcieRpEnableMask | FSP_M_CONFIG
PdEnergyCh0Dimm0 | FSP_M_CONFIG
PdEnergyCh0Dimm1 | FSP_M_CONFIG
PdEnergyCh1Dimm0 | FSP_M_CONFIG
PdEnergyCh1Dimm1 | FSP_M_CONFIG
PeciC10Reset | FSP_M_CONFIG
PeciSxReset | FSP_M_CONFIG
Peg0Enable | FSP_M_CONFIG
Peg0MaxLinkSpeed | FSP_M_CONFIG
Peg0MaxLinkWidth | FSP_M_CONFIG
Peg0PowerDownUnusedLanes | FSP_M_CONFIG
Peg1Enable | FSP_M_CONFIG
Peg1MaxLinkSpeed | FSP_M_CONFIG
Peg1MaxLinkWidth | FSP_M_CONFIG
Peg1PowerDownUnusedLanes | FSP_M_CONFIG
Peg2Enable | FSP_M_CONFIG
Peg2MaxLinkSpeed | FSP_M_CONFIG
Peg2MaxLinkWidth | FSP_M_CONFIG
Peg2PowerDownUnusedLanes | FSP_M_CONFIG
Peg3Enable | FSP_M_CONFIG
Peg3MaxLinkSpeed | FSP_M_CONFIG
Peg3MaxLinkWidth | FSP_M_CONFIG
Peg3PowerDownUnusedLanes | FSP_M_CONFIG
PegDataPtr | FSP_M_CONFIG
PegDisableSpreadSpectrumClocking | FSP_M_CONFIG
PegGen3RxCtlePeaking | FSP_M_CONFIG
PegGpioData | FSP_M_CONFIG
PegRootPortHPE | FSP_M_CONFIG
PlatformDebugConsent | FSP_M_CONFIG
PlatformMemorySize | FSP_M_CONFIG
PostCodeOutputPort | FSP_M_CONFIG
PrimaryDisplay | FSP_M_CONFIG
PrmrrSize | FSP_M_CONFIG
ProbelessTrace | FSP_M_CONFIG
PsmiRegionSize | FSP_M_CONFIG
PwdwnIdleCounter | FSP_M_CONFIG
RankInterleave | FSP_M_CONFIG
RaplLim1Ena | FSP_M_CONFIG
RaplLim1Pwr | FSP_M_CONFIG
RaplLim1WindX | FSP_M_CONFIG
RaplLim1WindY | FSP_M_CONFIG
RaplLim2Ena | FSP_M_CONFIG
RaplLim2Lock | FSP_M_CONFIG
RaplLim2Pwr | FSP_M_CONFIG
RaplLim2WindX | FSP_M_CONFIG
RaplLim2WindY | FSP_M_CONFIG
RaplPwrFlCh0 | FSP_M_CONFIG
RaplPwrFlCh1 | FSP_M_CONFIG
Ratio | FSP_M_CONFIG
RcompResistor | FSP_M_CONFIG
RcompTarget | FSP_M_CONFIG
RCVENC1D | FSP_M_CONFIG
RCVET | FSP_M_CONFIG
RDAPT | FSP_M_CONFIG
RdEnergyCh0Dimm0 | FSP_M_CONFIG
RdEnergyCh0Dimm1 | FSP_M_CONFIG
RdEnergyCh1Dimm0 | FSP_M_CONFIG
RdEnergyCh1Dimm1 | FSP_M_CONFIG
RDEQT | FSP_M_CONFIG
RDMPRT | FSP_M_CONFIG
RDODTT | FSP_M_CONFIG
RDTC1D | FSP_M_CONFIG
RDTC2D | FSP_M_CONFIG
RDVC2D | FSP_M_CONFIG
RealtimeMemoryTiming | FSP_M_CONFIG
RefClk | FSP_M_CONFIG
Refresh2X | FSP_M_CONFIG
RemapEnable | FSP_M_CONFIG
ReservedFspmUpd | FSP_M_CONFIG
ReservedFspmUpdCfl | FSP_M_CONFIG
ReservedPchPreMem | FSP_M_CONFIG
ReservedSecurityPreMem | FSP_M_CONFIG
RhActProbability | FSP_M_CONFIG
RhPrevention | FSP_M_CONFIG
RhSolution | FSP_M_CONFIG
RingDownBin | FSP_M_CONFIG
RingMaxOcRatio | FSP_M_CONFIG
RingPllVoltageOffset | FSP_M_CONFIG
RingVoltageAdaptive | FSP_M_CONFIG
RingVoltageMode | FSP_M_CONFIG
RingVoltageOffset | FSP_M_CONFIG
RingVoltageOverride | FSP_M_CONFIG
RMC | FSP_M_CONFIG
RMT | FSP_M_CONFIG
RMTLoopCount | FSP_M_CONFIG
RmtPerTask | FSP_M_CONFIG
RootPortIndex | FSP_M_CONFIG
RsvdSmbusAddressTablePtr | FSP_M_CONFIG
RTL | FSP_M_CONFIG
SafeMode | FSP_M_CONFIG
SaGv | FSP_M_CONFIG
SaIpuEnable | FSP_M_CONFIG
SaIpuImrConfiguration | FSP_M_CONFIG
SaOcSupport | FSP_M_CONFIG
SaPllVoltageOffset | FSP_M_CONFIG
SaPreMemProductionRsvd | FSP_M_CONFIG
SaRtd3Pcie0Gpio | FSP_M_CONFIG
SaRtd3Pcie1Gpio | FSP_M_CONFIG
SaRtd3Pcie2Gpio | FSP_M_CONFIG
SaRtd3Pcie3Gpio | FSP_M_CONFIG
SaVoltageOffset | FSP_M_CONFIG
ScramblerSupport | FSP_M_CONFIG
SgDelayAfterHoldReset | FSP_M_CONFIG
SgDelayAfterPwrEn | FSP_M_CONFIG
SinitMemorySize | FSP_M_CONFIG
SkipMpInit | FSP_M_CONFIG
SkipStopPbet | FSP_M_CONFIG
SmbusArpEnable | FSP_M_CONFIG
SmbusEnable | FSP_M_CONFIG
SmramMask | FSP_M_CONFIG
SOT | FSP_M_CONFIG
SpdAddressTable | FSP_M_CONFIG
SpdProfileSelected | FSP_M_CONFIG
SrefCfgEna | FSP_M_CONFIG
TAT | FSP_M_CONFIG
tCL | FSP_M_CONFIG
tCWL | FSP_M_CONFIG
tFAW | FSP_M_CONFIG
TgaSize | FSP_M_CONFIG
ThrtCkeMinDefeat | FSP_M_CONFIG
ThrtCkeMinDefeatLpddr | FSP_M_CONFIG
ThrtCkeMinTmr | FSP_M_CONFIG
ThrtCkeMinTmrLpddr | FSP_M_CONFIG
TjMaxOffset | FSP_M_CONFIG
TrainTrace | FSP_M_CONFIG
tRAS | FSP_M_CONFIG
tRCDtRP | FSP_M_CONFIG
tREFI | FSP_M_CONFIG
tRFC | FSP_M_CONFIG
tRRD | FSP_M_CONFIG
tRTP | FSP_M_CONFIG
TsegSize | FSP_M_CONFIG
TsodAlarmwindowLockBit | FSP_M_CONFIG
TsodCriticalEventOnly | FSP_M_CONFIG
TsodCriticaltripLockBit | FSP_M_CONFIG
TsodEventMode | FSP_M_CONFIG
TsodEventOutputControl | FSP_M_CONFIG
TsodEventPolarity | FSP_M_CONFIG
TsodManualEnable | FSP_M_CONFIG
TsodShutdownMode | FSP_M_CONFIG
TsodTcritMax | FSP_M_CONFIG
TsodThigMax | FSP_M_CONFIG
TvbRatioClipping | FSP_M_CONFIG
TvbVoltageOptimization | FSP_M_CONFIG
tWR | FSP_M_CONFIG
tWTR | FSP_M_CONFIG
Txt | FSP_M_CONFIG
TxtDprMemoryBase | FSP_M_CONFIG
TxtDprMemorySize | FSP_M_CONFIG
TxtHeapMemorySize | FSP_M_CONFIG
TxtImplemented | FSP_M_CONFIG
TxtLcpPdBase | FSP_M_CONFIG
TxtLcpPdSize | FSP_M_CONFIG
UnusedUpdSpace0 | FSP_M_CONFIG
UnusedUpdSpace1 | FSP_M_CONFIG
UnusedUpdSpace2 | FSP_M_CONFIG
UnusedUpdSpace3 | FSP_M_CONFIG
UnusedUpdSpace4 | FSP_M_CONFIG
UnusedUpdSpace5 | FSP_M_CONFIG
UnusedUpdSpace6 | FSP_M_CONFIG
UserBd | FSP_M_CONFIG
UserBudgetEnable | FSP_M_CONFIG
UserPowerWeightsEn | FSP_M_CONFIG
UserThresholdEnable | FSP_M_CONFIG
VddVoltage | FSP_M_CONFIG
VmxEnable | FSP_M_CONFIG
WarmBudgetCh0Dimm0 | FSP_M_CONFIG
WarmBudgetCh0Dimm1 | FSP_M_CONFIG
WarmBudgetCh1Dimm0 | FSP_M_CONFIG
WarmBudgetCh1Dimm1 | FSP_M_CONFIG
WarmThresholdCh0Dimm0 | FSP_M_CONFIG
WarmThresholdCh0Dimm1 | FSP_M_CONFIG
WarmThresholdCh1Dimm0 | FSP_M_CONFIG
WarmThresholdCh1Dimm1 | FSP_M_CONFIG
WRDSEQT | FSP_M_CONFIG
WRDSUDT | FSP_M_CONFIG
WrEnergyCh0Dimm0 | FSP_M_CONFIG
WrEnergyCh0Dimm1 | FSP_M_CONFIG
WrEnergyCh1Dimm0 | FSP_M_CONFIG
WrEnergyCh1Dimm1 | FSP_M_CONFIG
WRSRT | FSP_M_CONFIG
WRTC1D | FSP_M_CONFIG
WRTC2D | FSP_M_CONFIG
WRVC1D | FSP_M_CONFIG
WRVC2D | FSP_M_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_M_TEST_CONFIG Member List

This is the complete list of members for FSP_M_TEST_CONFIG, including all inherited members.

BdatEnable | FSP_M_TEST_CONFIG
BdatTestType | FSP_M_TEST_CONFIG
BiosSize | FSP_M_TEST_CONFIG
BypassPhySyncReset | FSP_M_TEST_CONFIG
ChipsetInitMessage | FSP_M_TEST_CONFIG
DidInitStat | FSP_M_TEST_CONFIG
DisableCpuReplacedPolling | FSP_M_TEST_CONFIG
DisableHeciRetry | FSP_M_TEST_CONFIG
DisableMessageCheck | FSP_M_TEST_CONFIG
DmiGen3EqPh2Enable | FSP_M_TEST_CONFIG
DmiGen3EqPh3Method | FSP_M_TEST_CONFIG
DmiMaxLinkSpeed | FSP_M_TEST_CONFIG
Gen3SwEqAlwaysAttempt | FSP_M_TEST_CONFIG
Gen3SwEqEnableVocTest | FSP_M_TEST_CONFIG
Gen3SwEqJitterDwellTime | FSP_M_TEST_CONFIG
Gen3SwEqJitterErrorTarget | FSP_M_TEST_CONFIG
Gen3SwEqNumberOfPresets | FSP_M_TEST_CONFIG
Gen3SwEqVocDwellTime | FSP_M_TEST_CONFIG
Gen3SwEqVocErrorTarget | FSP_M_TEST_CONFIG
HeciCommunication2 | FSP_M_TEST_CONFIG
KtDeviceEnable | FSP_M_TEST_CONFIG
LockPTMregs | FSP_M_TEST_CONFIG
PanelPowerEnable | FSP_M_TEST_CONFIG
Peg0Gen3EqPh2Enable | FSP_M_TEST_CONFIG
Peg0Gen3EqPh3Method | FSP_M_TEST_CONFIG
Peg1Gen3EqPh2Enable | FSP_M_TEST_CONFIG
Peg1Gen3EqPh3Method | FSP_M_TEST_CONFIG
Peg2Gen3EqPh2Enable | FSP_M_TEST_CONFIG
Peg2Gen3EqPh3Method | FSP_M_TEST_CONFIG
Peg3Gen3EqPh2Enable | FSP_M_TEST_CONFIG
Peg3Gen3EqPh3Method | FSP_M_TEST_CONFIG
PegGen3EndPointHint | FSP_M_TEST_CONFIG
PegGen3EndPointPreset | FSP_M_TEST_CONFIG
PegGen3ProgramStaticEq | FSP_M_TEST_CONFIG
PegGen3RootPortPreset | FSP_M_TEST_CONFIG
PegGen3Rsvd | FSP_M_TEST_CONFIG
PegGen3RxCtleOverride | FSP_M_TEST_CONFIG
PegGenerateBdatMarginTable | FSP_M_TEST_CONFIG
PegRxCemLoopbackLane | FSP_M_TEST_CONFIG
PegRxCemNonProtocolAwareness | FSP_M_TEST_CONFIG
PegRxCemTestingMode | FSP_M_TEST_CONFIG
ReservedFspmTestUpd | FSP_M_TEST_CONFIG
SaPreMemTestRsvd | FSP_M_TEST_CONFIG
ScanExtGfxForLegacyOpRom | FSP_M_TEST_CONFIG
SecurityTestRsvd | FSP_M_TEST_CONFIG
SendDidMsg | FSP_M_TEST_CONFIG
Signature | FSP_M_TEST_CONFIG
SkipExtGfxScan | FSP_M_TEST_CONFIG
SkipMbpHob | FSP_M_TEST_CONFIG
SmbusDynamicPowerGating | FSP_M_TEST_CONFIG
SmbusSpdWriteDisable | FSP_M_TEST_CONFIG
TotalFlashSize | FSP_M_TEST_CONFIG
tRd2RdDD | FSP_M_TEST_CONFIG
tRd2RdDG | FSP_M_TEST_CONFIG
tRd2RdDR | FSP_M_TEST_CONFIG
tRd2RdSG | FSP_M_TEST_CONFIG
tRd2WrDD | FSP_M_TEST_CONFIG
tRd2WrDG | FSP_M_TEST_CONFIG
tRd2WrDR | FSP_M_TEST_CONFIG
tRd2WrSG | FSP_M_TEST_CONFIG
tRRD_L | FSP_M_TEST_CONFIG
tRRD_S | FSP_M_TEST_CONFIG
tWr2RdDD | FSP_M_TEST_CONFIG
tWr2RdDG | FSP_M_TEST_CONFIG
tWr2RdDR | FSP_M_TEST_CONFIG
tWr2RdSG | FSP_M_TEST_CONFIG
tWr2WrDD | FSP_M_TEST_CONFIG
tWr2WrDG | FSP_M_TEST_CONFIG
tWr2WrDR | FSP_M_TEST_CONFIG
tWr2WrSG | FSP_M_TEST_CONFIG
tWTR_L | FSP_M_TEST_CONFIG
tWTR_S | FSP_M_TEST_CONFIG
TxtAcheckRequest | FSP_M_TEST_CONFIG
UnusedUpdSpace8 | FSP_M_TEST_CONFIG
WdtDisableAndLock | FSP_M_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_S_CONFIG Member List

This is the complete list of members for FSP_S_CONFIG, including all inherited members.

AcLoadline | FSP_S_CONFIG
AcousticNoiseMitigation | FSP_S_CONFIG
AesEnable | FSP_S_CONFIG
AmtEnabled | FSP_S_CONFIG
AmtKvmEnabled | FSP_S_CONFIG
AmtSolEnabled | FSP_S_CONFIG
AsfEnabled | FSP_S_CONFIG
BgpdtHash | FSP_S_CONFIG
BiosGuardAttr | FSP_S_CONFIG
BiosGuardModulePtr | FSP_S_CONFIG
BltBufferAddress | FSP_S_CONFIG
BltBufferSize | FSP_S_CONFIG
CdClock | FSP_S_CONFIG
ChipsetInitBinLen | FSP_S_CONFIG
ChipsetInitBinPtr | FSP_S_CONFIG
CpuBistData | FSP_S_CONFIG
CpuMpHob | FSP_S_CONFIG
CpuMpPpi | FSP_S_CONFIG
CridEnable | FSP_S_CONFIG
DcLoadline | FSP_S_CONFIG
DdiPortBDdc | FSP_S_CONFIG
DdiPortBHpd | FSP_S_CONFIG
DdiPortCDdc | FSP_S_CONFIG
DdiPortCHpd | FSP_S_CONFIG
DdiPortDDdc | FSP_S_CONFIG
DdiPortDHpd | FSP_S_CONFIG
DdiPortEdp | FSP_S_CONFIG
DdiPortFDdc | FSP_S_CONFIG
DdiPortFHpd | FSP_S_CONFIG
DebugInterfaceEnable | FSP_S_CONFIG
DeltaT12PowerCycleDelay | FSP_S_CONFIG
Device4Enable | FSP_S_CONFIG
DevIntConfigPtr | FSP_S_CONFIG
DmiAspm | FSP_S_CONFIG
DmiSuggestedSetting | FSP_S_CONFIG
DmiTS0TW | FSP_S_CONFIG
DmiTS1TW | FSP_S_CONFIG
DmiTS2TW | FSP_S_CONFIG
DmiTS3TW | FSP_S_CONFIG
EcCmdLock | FSP_S_CONFIG
EcCmdProvisionEav | FSP_S_CONFIG
Enable8254ClockGating | FSP_S_CONFIG
Enable8254ClockGatingOnS3 | FSP_S_CONFIG
EnableTcoTimer | FSP_S_CONFIG
EsataSpeedLimit | FSP_S_CONFIG
FastPkgCRampDisableFivr | FSP_S_CONFIG
FastPkgCRampDisableGt | FSP_S_CONFIG
FastPkgCRampDisableIa | FSP_S_CONFIG
FastPkgCRampDisableSa | FSP_S_CONFIG
FivrRfiFrequency | FSP_S_CONFIG
FivrSpreadSpectrum | FSP_S_CONFIG
ForcMebxSyncUp | FSP_S_CONFIG
FwProgress | FSP_S_CONFIG
GnaEnable | FSP_S_CONFIG
GpioIrqRoute | FSP_S_CONFIG
GraphicsConfigPtr | FSP_S_CONFIG
Heci3Enabled | FSP_S_CONFIG
IccMax | FSP_S_CONFIG
ImonOffset | FSP_S_CONFIG
ImonSlope | FSP_S_CONFIG
ImonSlope1 | FSP_S_CONFIG
IslVrCmd | FSP_S_CONFIG
LogoPtr | FSP_S_CONFIG
LogoSize | FSP_S_CONFIG
ManageabilityMode | FSP_S_CONFIG
McivrRfiFrequencyAdjust | FSP_S_CONFIG
McivrRfiFrequencyPrefix | FSP_S_CONFIG
McivrSpreadSpectrum | FSP_S_CONFIG
MeUnconfigOnRtcClear | FSP_S_CONFIG
MicrocodeRegionBase | FSP_S_CONFIG
MicrocodeRegionSize | FSP_S_CONFIG
NumOfDevIntConfig | FSP_S_CONFIG
PavpEnable | FSP_S_CONFIG
PchCnviMfUart1Type | FSP_S_CONFIG
PchCnviMode | FSP_S_CONFIG
PchCrid | FSP_S_CONFIG
PchDmiAspm | FSP_S_CONFIG
PchDmiAspmCtrl | FSP_S_CONFIG
PchDmiTsawEn | FSP_S_CONFIG
PchEnableComplianceMode | FSP_S_CONFIG
PchEnableDbcObs | FSP_S_CONFIG
PchEspiBmeMasterSlaveEnabled | FSP_S_CONFIG
PchEspiLgmrEnable | FSP_S_CONFIG
PchHdaAudioLinkDmic0 | FSP_S_CONFIG
PchHdaAudioLinkDmic1 | FSP_S_CONFIG
PchHdaAudioLinkHda | FSP_S_CONFIG
PchHdaAudioLinkSndw1 | FSP_S_CONFIG
PchHdaAudioLinkSndw2 | FSP_S_CONFIG
PchHdaAudioLinkSndw3 | FSP_S_CONFIG
PchHdaAudioLinkSndw4 | FSP_S_CONFIG
PchHdaAudioLinkSsp0 | FSP_S_CONFIG
PchHdaAudioLinkSsp1 | FSP_S_CONFIG
PchHdaAudioLinkSsp2 | FSP_S_CONFIG
PchHdaCodecSxWakeCapability | FSP_S_CONFIG
PchHdaDspEnable | FSP_S_CONFIG
PchHdaDspUaaCompliance | FSP_S_CONFIG
PchHdaIDispCodecDisconnect | FSP_S_CONFIG
PchHdaIDispLinkFrequency | FSP_S_CONFIG
PchHdaIDispLinkTmode | FSP_S_CONFIG
PchHdaLinkFrequency | FSP_S_CONFIG
PchHdaPme | FSP_S_CONFIG
PchHdaSndwBufferRcomp | FSP_S_CONFIG
PchHdaVcType | FSP_S_CONFIG
PchHdaVerbTableEntryNum | FSP_S_CONFIG
PchHdaVerbTablePtr | FSP_S_CONFIG
PchHotEnable | FSP_S_CONFIG
PchIoApicEntry24_119 | FSP_S_CONFIG
PchIoApicId | FSP_S_CONFIG
PchIshGp0GpioAssign | FSP_S_CONFIG
PchIshGp1GpioAssign | FSP_S_CONFIG
PchIshGp2GpioAssign | FSP_S_CONFIG
PchIshGp3GpioAssign | FSP_S_CONFIG
PchIshGp4GpioAssign | FSP_S_CONFIG
PchIshGp5GpioAssign | FSP_S_CONFIG
PchIshGp6GpioAssign | FSP_S_CONFIG
PchIshGp7GpioAssign | FSP_S_CONFIG
PchIshI2c0GpioAssign | FSP_S_CONFIG
PchIshI2c1GpioAssign | FSP_S_CONFIG
PchIshI2c2GpioAssign | FSP_S_CONFIG
PchIshPdtUnlock | FSP_S_CONFIG
PchIshSpiGpioAssign | FSP_S_CONFIG
PchIshUart0GpioAssign | FSP_S_CONFIG
PchIshUart1GpioAssign | FSP_S_CONFIG
PchLanEnable | FSP_S_CONFIG
PchLanLtrEnable | FSP_S_CONFIG
PchLockDownBiosLock | FSP_S_CONFIG
PchLockDownRtcMemoryLock | FSP_S_CONFIG
PchMemoryC0TransmitEnable | FSP_S_CONFIG
PchMemoryPinSelection | FSP_S_CONFIG
PchMemoryPmsyncEnable | FSP_S_CONFIG
PchMemoryThrottlingEnable | FSP_S_CONFIG
PchPcieDeviceOverrideTablePtr | FSP_S_CONFIG
PchPmDeepSxPol | FSP_S_CONFIG
PchPmDisableDsxAcPresentPulldown | FSP_S_CONFIG
PchPmDisableNativePowerButton | FSP_S_CONFIG
PchPmLanWakeFromDeepSx | FSP_S_CONFIG
PchPmLpcClockRun | FSP_S_CONFIG
PchPmMeWakeSts | FSP_S_CONFIG
PchPmPciePllSsc | FSP_S_CONFIG
PchPmPcieWakeFromDeepSx | FSP_S_CONFIG
PchPmPmeB0S5Dis | FSP_S_CONFIG
PchPmPwrBtnOverridePeriod | FSP_S_CONFIG
PchPmPwrCycDur | FSP_S_CONFIG
PchPmSlpAMinAssert | FSP_S_CONFIG
PchPmSlpLanLowDc | FSP_S_CONFIG
PchPmSlpS0Enable | FSP_S_CONFIG
PchPmSlpS0Vm070VSupport | FSP_S_CONFIG
PchPmSlpS0Vm075VSupport | FSP_S_CONFIG
PchPmSlpS0VmRuntimeControl | FSP_S_CONFIG
PchPmSlpS3MinAssert | FSP_S_CONFIG
PchPmSlpS4MinAssert | FSP_S_CONFIG
PchPmSlpStrchSusUp | FSP_S_CONFIG
PchPmSlpSusMinAssert | FSP_S_CONFIG
PchPmVrAlert | FSP_S_CONFIG
PchPmWolEnableOverride | FSP_S_CONFIG
PchPmWolOvrWkSts | FSP_S_CONFIG
PchPmWoWlanDeepSxEnable | FSP_S_CONFIG
PchPmWoWlanEnable | FSP_S_CONFIG
PchPostMemRsvd | FSP_S_CONFIG
PchProtectedRangeBase | FSP_S_CONFIG
PchProtectedRangeLimit | FSP_S_CONFIG
PchPwrOptEnable | FSP_S_CONFIG
PchReadProtectionEnable | FSP_S_CONFIG
PchScsEmmcHs400DllDataValid | FSP_S_CONFIG
PchScsEmmcHs400DriverStrength | FSP_S_CONFIG
PchScsEmmcHs400RxStrobeDll1 | FSP_S_CONFIG
PchScsEmmcHs400TuningRequired | FSP_S_CONFIG
PchScsEmmcHs400TxDataDll | FSP_S_CONFIG
PchSerialIoI2cPadsTermination | FSP_S_CONFIG
PchSirqEnable | FSP_S_CONFIG
PchSirqMode | FSP_S_CONFIG
PchStartFramePulse | FSP_S_CONFIG
PchT0Level | FSP_S_CONFIG
PchT1Level | FSP_S_CONFIG
PchT2Level | FSP_S_CONFIG
PchTemperatureHotLevel | FSP_S_CONFIG
PchTsmicLock | FSP_S_CONFIG
PchTTEnable | FSP_S_CONFIG
PchTTLock | FSP_S_CONFIG
PchTTState13Enable | FSP_S_CONFIG
PchUsb2PhySusPgEnable | FSP_S_CONFIG
PchUsbHsioFilterSel | FSP_S_CONFIG
PchUsbHsioRxTuningEnable | FSP_S_CONFIG
PchUsbHsioRxTuningParameters | FSP_S_CONFIG
PchUsbOverCurrentEnable | FSP_S_CONFIG
PchWriteProtectionEnable | FSP_S_CONFIG
PcieClkSrcClkReq | FSP_S_CONFIG
PcieClkSrcUsage | FSP_S_CONFIG
PcieComplianceTestMode | FSP_S_CONFIG
PcieDisableRootPortClockGating | FSP_S_CONFIG
PcieEnablePeerMemoryWrite | FSP_S_CONFIG
PcieEqPh3LaneParamCm | FSP_S_CONFIG
PcieEqPh3LaneParamCp | FSP_S_CONFIG
PcieRootPortGen2PllL1CgDisable | FSP_S_CONFIG
PcieRpAcsEnabled | FSP_S_CONFIG
PcieRpAdvancedErrorReporting | FSP_S_CONFIG
PcieRpAspm | FSP_S_CONFIG
PcieRpClkReqDetect | FSP_S_CONFIG
PcieRpCompletionTimeout | FSP_S_CONFIG
PcieRpCorrectableErrorReport | FSP_S_CONFIG
PcieRpDetectTimeoutMs | FSP_S_CONFIG
PcieRpDpcExtensionsMask | FSP_S_CONFIG
PcieRpDpcMask | FSP_S_CONFIG
PcieRpEnableCpm | FSP_S_CONFIG
PcieRpExtSync | FSP_S_CONFIG
PcieRpFatalErrorReport | FSP_S_CONFIG
PcieRpFunctionSwap | FSP_S_CONFIG
PcieRpGen3EqPh3Method | FSP_S_CONFIG
PcieRpHotPlug | FSP_S_CONFIG
PcieRpImrEnabled | FSP_S_CONFIG
PcieRpImrSelection | FSP_S_CONFIG
PcieRpL1Substates | FSP_S_CONFIG
PcieRpLtrConfigLock | FSP_S_CONFIG
PcieRpLtrEnable | FSP_S_CONFIG
PcieRpMaxPayload | FSP_S_CONFIG
PcieRpNoFatalErrorReport | FSP_S_CONFIG
PcieRpPcieSpeed | FSP_S_CONFIG
PcieRpPhysicalSlotNumber | FSP_S_CONFIG
PcieRpPmSci | FSP_S_CONFIG
PcieRpPtmMask | FSP_S_CONFIG
PcieRpSlotImplemented | FSP_S_CONFIG
PcieRpSystemErrorOnCorrectableError | FSP_S_CONFIG
PcieRpSystemErrorOnFatalError | FSP_S_CONFIG
PcieRpSystemErrorOnNonFatalError | FSP_S_CONFIG
PcieRpTransmitterHalfSwing | FSP_S_CONFIG
PcieRpUnsupportedRequestReport | FSP_S_CONFIG
PcieSwEqCoeffListCm | FSP_S_CONFIG
PcieSwEqCoeffListCp | FSP_S_CONFIG
PegDeEmphasis | FSP_S_CONFIG
PegPhysicalSlotNumber | FSP_S_CONFIG
PegSlotPowerLimitScale | FSP_S_CONFIG
PegSlotPowerLimitValue | FSP_S_CONFIG
PeiGraphicsPeimInit | FSP_S_CONFIG
PmcCpuC10GatePinEnable | FSP_S_CONFIG
PmcDbgMsgEn | FSP_S_CONFIG
PmcModPhySusPgEnable | FSP_S_CONFIG
PmcPowerButtonDebounce | FSP_S_CONFIG
PortUsb20Enable | FSP_S_CONFIG
PortUsb30Enable | FSP_S_CONFIG
PreWake | FSP_S_CONFIG
Psi1Threshold | FSP_S_CONFIG
Psi2Threshold | FSP_S_CONFIG
Psi3Enable | FSP_S_CONFIG
Psi3Threshold | FSP_S_CONFIG
Psi4Enable | FSP_S_CONFIG
PsOnEnable | FSP_S_CONFIG
PsysOffset | FSP_S_CONFIG
PsysSlope | FSP_S_CONFIG
PxRcConfig | FSP_S_CONFIG
RampDown | FSP_S_CONFIG
RampUp | FSP_S_CONFIG
RemoteAssistance | FSP_S_CONFIG
Reserved2 | FSP_S_CONFIG
ReservedCpuPostMemProduction | FSP_S_CONFIG
ReservedForFuture1 | FSP_S_CONFIG
ReservedFspsUpd | FSP_S_CONFIG
SaPostMemProductionRsvd | FSP_S_CONFIG
SataEnable | FSP_S_CONFIG
SataLedEnable | FSP_S_CONFIG
SataMode | FSP_S_CONFIG
SataP0T1M | FSP_S_CONFIG
SataP0T2M | FSP_S_CONFIG
SataP0T3M | FSP_S_CONFIG
SataP0TDisp | FSP_S_CONFIG
SataP0TDispFinit | FSP_S_CONFIG
SataP0Tinact | FSP_S_CONFIG
SataP1T1M | FSP_S_CONFIG
SataP1T2M | FSP_S_CONFIG
SataP1T3M | FSP_S_CONFIG
SataP1TDisp | FSP_S_CONFIG
SataP1TDispFinit | FSP_S_CONFIG
SataP1Tinact | FSP_S_CONFIG
SataPortsDevSlp | FSP_S_CONFIG
SataPortsDitoVal | FSP_S_CONFIG
SataPortsDmVal | FSP_S_CONFIG
SataPortsEnable | FSP_S_CONFIG
SataPortsEnableDitoConfig | FSP_S_CONFIG
SataPortsExternal | FSP_S_CONFIG
SataPortsHotPlug | FSP_S_CONFIG
SataPortsInterlockSw | FSP_S_CONFIG
SataPortsSolidStateDrive | FSP_S_CONFIG
SataPortsSpinUp | FSP_S_CONFIG
SataPortsZpOdd | FSP_S_CONFIG
SataPwrOptEnable | FSP_S_CONFIG
SataRstCpuAttachedStorage | FSP_S_CONFIG
SataRstHddUnlock | FSP_S_CONFIG
SataRstInterrupt | FSP_S_CONFIG
SataRstIrrt | FSP_S_CONFIG
SataRstIrrtOnly | FSP_S_CONFIG
SataRstLedLocate | FSP_S_CONFIG
SataRstLegacyOrom | FSP_S_CONFIG
SataRstOptaneMemory | FSP_S_CONFIG
SataRstOromUiBanner | FSP_S_CONFIG
SataRstOromUiDelay | FSP_S_CONFIG
SataRstPcieDeviceResetDelay | FSP_S_CONFIG
SataRstPcieEnable | FSP_S_CONFIG
SataRstPcieStoragePort | FSP_S_CONFIG
SataRstRaid0 | FSP_S_CONFIG
SataRstRaid1 | FSP_S_CONFIG
SataRstRaid10 | FSP_S_CONFIG
SataRstRaid5 | FSP_S_CONFIG
SataRstRaidDeviceId | FSP_S_CONFIG
SataRstSmartStorage | FSP_S_CONFIG
SataSalpSupport | FSP_S_CONFIG
SataSpeedLimit | FSP_S_CONFIG
SataThermalSuggestedSetting | FSP_S_CONFIG
SciIrqSelect | FSP_S_CONFIG
ScsEmmcEnabled | FSP_S_CONFIG
ScsEmmcHs400Enabled | FSP_S_CONFIG
ScsSdCardEnabled | FSP_S_CONFIG
ScsUfsEnabled | FSP_S_CONFIG
SdCardPowerEnableActiveHigh | FSP_S_CONFIG
SendEcCmd | FSP_S_CONFIG
SendVrMbxCmd | FSP_S_CONFIG
SerialIoDebugUartNumber | FSP_S_CONFIG
SerialIoDevMode | FSP_S_CONFIG
SerialIoEnableDebugUartAfterPost | FSP_S_CONFIG
SerialIoSpiCsPolarity | FSP_S_CONFIG
SerialIoUart0PinMuxing | FSP_S_CONFIG
SerialIoUartHwFlowCtrl | FSP_S_CONFIG
SgxEpoch0 | FSP_S_CONFIG
SgxEpoch1 | FSP_S_CONFIG
SgxSinitNvsData | FSP_S_CONFIG
ShowSpiController | FSP_S_CONFIG
SiCsmFlag | FSP_S_CONFIG
SiNumberOfSsidTableEntry | FSP_S_CONFIG
SiSsidTablePtr | FSP_S_CONFIG
SkipMpInit | FSP_S_CONFIG
SkipS3CdClockInit | FSP_S_CONFIG
SlowSlewRateForFivr | FSP_S_CONFIG
SlowSlewRateForGt | FSP_S_CONFIG
SlowSlewRateForIa | FSP_S_CONFIG
SlowSlewRateForSa | FSP_S_CONFIG
SlpS0DisQForDebug | FSP_S_CONFIG
SlpS0Override | FSP_S_CONFIG
SlpS0WithGbeSupport | FSP_S_CONFIG
TcoIrqEnable | FSP_S_CONFIG
TcoIrqSelect | FSP_S_CONFIG
TdcEnable | FSP_S_CONFIG
TdcLock | FSP_S_CONFIG
TdcPowerLimit | FSP_S_CONFIG
TdcTimeWindow | FSP_S_CONFIG
TetonGlacierCR | FSP_S_CONFIG
TetonGlacierSupport | FSP_S_CONFIG
TraceHubMemBase | FSP_S_CONFIG
TTCrossThrottling | FSP_S_CONFIG
TTSuggestedSetting | FSP_S_CONFIG
TurboMode | FSP_S_CONFIG
TxtEnable | FSP_S_CONFIG
UnusedUpdSpace0 | FSP_S_CONFIG
UnusedUpdSpace1 | FSP_S_CONFIG
UnusedUpdSpace10 | FSP_S_CONFIG
UnusedUpdSpace11 | FSP_S_CONFIG
UnusedUpdSpace12 | FSP_S_CONFIG
UnusedUpdSpace13 | FSP_S_CONFIG
UnusedUpdSpace14 | FSP_S_CONFIG
UnusedUpdSpace15 | FSP_S_CONFIG
UnusedUpdSpace16 | FSP_S_CONFIG
UnusedUpdSpace17 | FSP_S_CONFIG
UnusedUpdSpace18 | FSP_S_CONFIG
UnusedUpdSpace19 | FSP_S_CONFIG
UnusedUpdSpace2 | FSP_S_CONFIG
UnusedUpdSpace20 | FSP_S_CONFIG
UnusedUpdSpace21 | FSP_S_CONFIG
UnusedUpdSpace22 | FSP_S_CONFIG
UnusedUpdSpace23 | FSP_S_CONFIG
UnusedUpdSpace3 | FSP_S_CONFIG
UnusedUpdSpace4 | FSP_S_CONFIG
UnusedUpdSpace5 | FSP_S_CONFIG
UnusedUpdSpace6 | FSP_S_CONFIG
UnusedUpdSpace7 | FSP_S_CONFIG
UnusedUpdSpace8 | FSP_S_CONFIG
UnusedUpdSpace9 | FSP_S_CONFIG
Usb2AfePehalfbit | FSP_S_CONFIG
Usb2AfePetxiset | FSP_S_CONFIG
Usb2AfePredeemp | FSP_S_CONFIG
Usb2AfeTxiset | FSP_S_CONFIG
Usb2OverCurrentPin | FSP_S_CONFIG
Usb3HsioTxDeEmph | FSP_S_CONFIG
Usb3HsioTxDeEmphEnable | FSP_S_CONFIG
Usb3HsioTxDownscaleAmp | FSP_S_CONFIG
Usb3HsioTxDownscaleAmpEnable | FSP_S_CONFIG
Usb3OverCurrentPin | FSP_S_CONFIG
UsbPdoProgramming | FSP_S_CONFIG
VrConfigEnable | FSP_S_CONFIG
VrPowerDeliveryDesign | FSP_S_CONFIG
VrVoltageLimit | FSP_S_CONFIG
VtdBaseAddress | FSP_S_CONFIG
WatchDog | FSP_S_CONFIG
WatchDogTimerBios | FSP_S_CONFIG
WatchDogTimerOs | FSP_S_CONFIG
X2ApicOptOut | FSP_S_CONFIG
XdciEnable | FSP_S_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_S_TEST_CONFIG Member List

This is the complete list of members for FSP_S_TEST_CONFIG, including all inherited members.

ApIdleManner | FSP_S_TEST_CONFIG
AutoThermalReporting | FSP_S_TEST_CONFIG
BiProcHot | FSP_S_TEST_CONFIG
C1e | FSP_S_TEST_CONFIG
C1StateAutoDemotion | FSP_S_TEST_CONFIG
C1StateUnDemotion | FSP_S_TEST_CONFIG
C3StateAutoDemotion | FSP_S_TEST_CONFIG
C3StateUnDemotion | FSP_S_TEST_CONFIG
CdynmaxClampEnable | FSP_S_TEST_CONFIG
ChapDeviceEnable | FSP_S_TEST_CONFIG
ConfigTdpBios | FSP_S_TEST_CONFIG
ConfigTdpLevel | FSP_S_TEST_CONFIG
ConfigTdpLock | FSP_S_TEST_CONFIG
CpuWakeUpTimer | FSP_S_TEST_CONFIG
CstateLatencyControl0Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl0TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl1Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl1TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl2Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl2TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl3Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl3TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl4Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl4TimeUnit | FSP_S_TEST_CONFIG
CstateLatencyControl5Irtl | FSP_S_TEST_CONFIG
CstateLatencyControl5TimeUnit | FSP_S_TEST_CONFIG
CStatePreWake | FSP_S_TEST_CONFIG
CstCfgCtrIoMwaitRedirection | FSP_S_TEST_CONFIG
Custom1ConfigTdpControl | FSP_S_TEST_CONFIG
Custom1PowerLimit1 | FSP_S_TEST_CONFIG
Custom1PowerLimit1Time | FSP_S_TEST_CONFIG
Custom1PowerLimit2 | FSP_S_TEST_CONFIG
Custom1TurboActivationRatio | FSP_S_TEST_CONFIG
Custom2ConfigTdpControl | FSP_S_TEST_CONFIG
Custom2PowerLimit1 | FSP_S_TEST_CONFIG
Custom2PowerLimit1Time | FSP_S_TEST_CONFIG
Custom2PowerLimit2 | FSP_S_TEST_CONFIG
Custom2TurboActivationRatio | FSP_S_TEST_CONFIG
Custom3ConfigTdpControl | FSP_S_TEST_CONFIG
Custom3PowerLimit1 | FSP_S_TEST_CONFIG
Custom3PowerLimit1Time | FSP_S_TEST_CONFIG
Custom3PowerLimit2 | FSP_S_TEST_CONFIG
Custom3TurboActivationRatio | FSP_S_TEST_CONFIG
Cx | FSP_S_TEST_CONFIG
DebugInterfaceEnable | FSP_S_TEST_CONFIG
DebugInterfaceLockEnable | FSP_S_TEST_CONFIG
DisableD0I3SettingForHeci | FSP_S_TEST_CONFIG
DisableProcHotOut | FSP_S_TEST_CONFIG
DisableTurboGt | FSP_S_TEST_CONFIG
DisableVrThermalAlert | FSP_S_TEST_CONFIG
DmiExtSync | FSP_S_TEST_CONFIG
DmiIot | FSP_S_TEST_CONFIG
EdramTestMode | FSP_S_TEST_CONFIG
EightCoreRatioLimit | FSP_S_TEST_CONFIG
Eist | FSP_S_TEST_CONFIG
EnableItbm | FSP_S_TEST_CONFIG
EnableItbmDriver | FSP_S_TEST_CONFIG
EndOfPostMessage | FSP_S_TEST_CONFIG
EnergyEfficientPState | FSP_S_TEST_CONFIG
EnergyEfficientTurbo | FSP_S_TEST_CONFIG
FiveCoreRatioLimit | FSP_S_TEST_CONFIG
FourCoreRatioLimit | FSP_S_TEST_CONFIG
GtFreqMax | FSP_S_TEST_CONFIG
HdcControl | FSP_S_TEST_CONFIG
Hwp | FSP_S_TEST_CONFIG
HwpInterruptControl | FSP_S_TEST_CONFIG
MachineCheckEnable | FSP_S_TEST_CONFIG
MaxRatio | FSP_S_TEST_CONFIG
MaxRingRatioLimit | FSP_S_TEST_CONFIG
MctpBroadcastCycle | FSP_S_TEST_CONFIG
MinRingRatioLimit | FSP_S_TEST_CONFIG
MlcSpatialPrefetcher | FSP_S_TEST_CONFIG
MlcStreamerPrefetcher | FSP_S_TEST_CONFIG
MonitorMwaitEnable | FSP_S_TEST_CONFIG
NumberOfEntries | FSP_S_TEST_CONFIG
OneCoreRatioLimit | FSP_S_TEST_CONFIG
PchHdaResetWaitTimer | FSP_S_TEST_CONFIG
PchLockDownBiosInterface | FSP_S_TEST_CONFIG
PchLockDownGlobalSmi | FSP_S_TEST_CONFIG
PchPciePort8xhDecodePortIndex | FSP_S_TEST_CONFIG
PchPmDisableEnergyReport | FSP_S_TEST_CONFIG
PchSbAccessUnlock | FSP_S_TEST_CONFIG
PchSbiUnlock | FSP_S_TEST_CONFIG
PchUnlockGpioPads | FSP_S_TEST_CONFIG
PchXhciOcLock | FSP_S_TEST_CONFIG
PcieEnablePort8xhDecode | FSP_S_TEST_CONFIG
PcieRpDptp | FSP_S_TEST_CONFIG
PcieRpLtrMaxNoSnoopLatency | FSP_S_TEST_CONFIG
PcieRpLtrMaxSnoopLatency | FSP_S_TEST_CONFIG
PcieRpNonSnoopLatencyOverrideMode | FSP_S_TEST_CONFIG
PcieRpNonSnoopLatencyOverrideMultiplier | FSP_S_TEST_CONFIG
PcieRpNonSnoopLatencyOverrideValue | FSP_S_TEST_CONFIG
PcieRpSlotPowerLimitScale | FSP_S_TEST_CONFIG
PcieRpSlotPowerLimitValue | FSP_S_TEST_CONFIG
PcieRpSnoopLatencyOverrideMode | FSP_S_TEST_CONFIG
PcieRpSnoopLatencyOverrideMultiplier | FSP_S_TEST_CONFIG
PcieRpSnoopLatencyOverrideValue | FSP_S_TEST_CONFIG
PcieRpUptp | FSP_S_TEST_CONFIG
PegMaxPayload | FSP_S_TEST_CONFIG
PkgCStateDemotion | FSP_S_TEST_CONFIG
PkgCStateLimit | FSP_S_TEST_CONFIG
PkgCStateUnDemotion | FSP_S_TEST_CONFIG
PmgCstCfgCtrlLock | FSP_S_TEST_CONFIG
PmSupport | FSP_S_TEST_CONFIG
PowerLimit1 | FSP_S_TEST_CONFIG
PowerLimit1Time | FSP_S_TEST_CONFIG
PowerLimit2 | FSP_S_TEST_CONFIG
PowerLimit2Power | FSP_S_TEST_CONFIG
PowerLimit3 | FSP_S_TEST_CONFIG
PowerLimit3DutyCycle | FSP_S_TEST_CONFIG
PowerLimit3Lock | FSP_S_TEST_CONFIG
PowerLimit3Time | FSP_S_TEST_CONFIG
PowerLimit4 | FSP_S_TEST_CONFIG
PowerLimit4Lock | FSP_S_TEST_CONFIG
PpmIrmSetting | FSP_S_TEST_CONFIG
ProcessorTraceEnable | FSP_S_TEST_CONFIG
ProcessorTraceMemBase | FSP_S_TEST_CONFIG
ProcessorTraceMemLength | FSP_S_TEST_CONFIG
ProcessorTraceOutputScheme | FSP_S_TEST_CONFIG
ProcHotLock | FSP_S_TEST_CONFIG
ProcHotResponse | FSP_S_TEST_CONFIG
PsysPmax | FSP_S_TEST_CONFIG
PsysPowerLimit1 | FSP_S_TEST_CONFIG
PsysPowerLimit1Power | FSP_S_TEST_CONFIG
PsysPowerLimit1Time | FSP_S_TEST_CONFIG
PsysPowerLimit2 | FSP_S_TEST_CONFIG
PsysPowerLimit2Power | FSP_S_TEST_CONFIG
RaceToHalt | FSP_S_TEST_CONFIG
RenderStandby | FSP_S_TEST_CONFIG
ReservedCpuPostMemTest | FSP_S_TEST_CONFIG
ReservedFspsTestUpd | FSP_S_TEST_CONFIG
SaPostMemTestRsvd | FSP_S_TEST_CONFIG
SataTestMode | FSP_S_TEST_CONFIG
SevenCoreRatioLimit | FSP_S_TEST_CONFIG
SgxSinitDataFromTpm | FSP_S_TEST_CONFIG
Signature | FSP_S_TEST_CONFIG
SixCoreRatioLimit | FSP_S_TEST_CONFIG
SkipPamLock | FSP_S_TEST_CONFIG
SkipPostBootSai | FSP_S_TEST_CONFIG
StateRatio | FSP_S_TEST_CONFIG
StateRatioMax16 | FSP_S_TEST_CONFIG
TccActivationOffset | FSP_S_TEST_CONFIG
TccOffsetClamp | FSP_S_TEST_CONFIG
TccOffsetLock | FSP_S_TEST_CONFIG
TccOffsetTimeWindowForRatl | FSP_S_TEST_CONFIG
ThermalMonitor | FSP_S_TEST_CONFIG
ThreeCoreRatioLimit | FSP_S_TEST_CONFIG
ThreeStrikeCounterDisable | FSP_S_TEST_CONFIG
TimedMwait | FSP_S_TEST_CONFIG
TStates | FSP_S_TEST_CONFIG
TurboPowerLimitLock | FSP_S_TEST_CONFIG
TwoCoreRatioLimit | FSP_S_TEST_CONFIG
UnusedUpdSpace24 | FSP_S_TEST_CONFIG
VoltageOptimization | FSP_S_TEST_CONFIG
VtdDisable | FSP_S_TEST_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSP_T_CONFIG Member List

This is the complete list of members for FSP_T_CONFIG, including all inherited members.

PcdPciExpressBaseAddress | FSP_T_CONFIG
PcdPciExpressRegionLength | FSP_T_CONFIG
PcdSerialIoUart0PinMuxing | FSP_T_CONFIG
PcdSerialIoUartDebugEnable | FSP_T_CONFIG
PcdSerialIoUartInputClock | FSP_T_CONFIG
PcdSerialIoUartNumber | FSP_T_CONFIG
ReservedFsptUpd1 | FSP_T_CONFIG
UnusedUpdSpace0 | FSP_T_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPM_UPD Member List

This is the complete list of members for FSPM_UPD, including all inherited members.

FspmArchUpd | FSPM_UPD
FspmConfig | FSPM_UPD
FspmTestConfig | FSPM_UPD
FspUpdHeader | FSPM_UPD
UnusedUpdSpace7 | FSPM_UPD
UpdTerminator | FSPM_UPD


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPS_UPD Member List

This is the complete list of members for FSPS_UPD, including all inherited members.

FspsConfig | FSPS_UPD
FspsTestConfig | FSPS_UPD
FspUpdHeader | FSPS_UPD
UpdTerminator | FSPS_UPD


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPT_CORE_UPD Member List

This is the complete list of members for FSPT_CORE_UPD, including all inherited members.

CodeRegionBase | FSPT_CORE_UPD
CodeRegionSize | FSPT_CORE_UPD
MicrocodeRegionBase | FSPT_CORE_UPD
MicrocodeRegionSize | FSPT_CORE_UPD
Reserved | FSPT_CORE_UPD


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

FSPT_UPD Member List

This is the complete list of members for FSPT_UPD, including all inherited members.

FsptConfig | FSPT_UPD
FsptCoreUpd | FSPT_UPD
FspUpdHeader | FSPT_UPD
UpdTerminator | FSPT_UPD


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

GPIO_CONFIG Member List

This is the complete list of members for GPIO_CONFIG, including all inherited members.

Direction | GPIO_CONFIG
ElectricalConfig | GPIO_CONFIG
HostSoftPadOwn | GPIO_CONFIG
InterruptConfig | GPIO_CONFIG
LockConfig | GPIO_CONFIG
OtherSettings | GPIO_CONFIG
OutputState | GPIO_CONFIG
PadMode | GPIO_CONFIG
PowerConfig | GPIO_CONFIG
RsvdBits | GPIO_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

HOB_USAGE_DATA_HOB Member List

This is the complete list of members for HOB_USAGE_DATA_HOB, including all inherited members.


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

MEMORY_PLATFORM_DATA Member List

This is the complete list of members for MEMORY_PLATFORM_DATA, including all inherited members.


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SI_PCH_DEVICE_INTERRUPT_CONFIG Member List

This is the complete list of members for SI_PCH_DEVICE_INTERRUPT_CONFIG, including all inherited members.

Device | SI_PCH_DEVICE_INTERRUPT_CONFIG
Function | SI_PCH_DEVICE_INTERRUPT_CONFIG
IntX | SI_PCH_DEVICE_INTERRUPT_CONFIG
Irq | SI_PCH_DEVICE_INTERRUPT_CONFIG


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SMBIOS_CACHE_INFO Member List

This is the complete list of members for SMBIOS_CACHE_INFO, including all inherited members.

Associativity | SMBIOS_CACHE_INFO
CacheConfiguration | SMBIOS_CACHE_INFO
CacheSpeed | SMBIOS_CACHE_INFO
CurrentSramType | SMBIOS_CACHE_INFO
ErrorCorrectionType | SMBIOS_CACHE_INFO
InstalledSize | SMBIOS_CACHE_INFO
InstalledSize2 | SMBIOS_CACHE_INFO
MaxCacheSize | SMBIOS_CACHE_INFO
MaximumCacheSize2 | SMBIOS_CACHE_INFO
NumberOfCacheLevels | SMBIOS_CACHE_INFO
SocketDesignationStrIndex | SMBIOS_CACHE_INFO
SupportedSramType | SMBIOS_CACHE_INFO
SystemCacheType | SMBIOS_CACHE_INFO


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SMBIOS_PROCESSOR_INFO Member List

This is the complete list of members for SMBIOS_PROCESSOR_INFO, including all inherited members.

CoreCount | SMBIOS_PROCESSOR_INFO
CurrentSpeedInMHz | SMBIOS_PROCESSOR_INFO
EnabledCoreCount | SMBIOS_PROCESSOR_INFO
ExternalClockInMHz | SMBIOS_PROCESSOR_INFO
ProcessorCharacteristics | SMBIOS_PROCESSOR_INFO
ProcessorFamily | SMBIOS_PROCESSOR_INFO
ProcessorId | SMBIOS_PROCESSOR_INFO
ProcessorManufacturerStrIndex | SMBIOS_PROCESSOR_INFO
ProcessorType | SMBIOS_PROCESSOR_INFO
ProcessorUpgrade | SMBIOS_PROCESSOR_INFO
ProcessorVersionStrIndex | SMBIOS_PROCESSOR_INFO
Status | SMBIOS_PROCESSOR_INFO
ThreadCount | SMBIOS_PROCESSOR_INFO
Voltage | SMBIOS_PROCESSOR_INFO


CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

SMBIOS_STRUCTURE Member List

This is the complete list of members for SMBIOS_STRUCTURE, including all inherited members.